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Code Issues Releases Wiki Activity

Turbo Tag: works, controls are strange (but similar to MAME)

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This commit is contained in:
Gyorgy Szombathelyi 2020-02-16 00:40:56 +01:00
parent 9a3bb64765
commit 7903cdcd66
13 changed files with 424 additions and 2985 deletions
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27
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/README.txt
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@ -1,26 +1,13 @@
---------------------------------------------------------------------------------
--
-- Arcade: Spy Hunter port to MiST by Gehstock
-- 16 November 2019
-- Arcade: Turbo Tag port to MiST by Slingshot
-- 16 February 2020
--
SHUNTER.ROM is required at the root of the SD-Card.
Controls
Joy Keyboard
up up : Accelerate
down down : Decelerate
left left : Left
right right : Right
ESC : Coin
start TAB : VAN
Y Z : Shift
X shift left : Oil
C ctrl left : Smoke
B alt left : Missle
A Space : Gun
-- Usage:
-- Create ROM file from MRA file and MAME spyhunt.zip file using the MRA utility
-- Copy the ROM and the RBF to the SD Card
-- MRA utility: https://github.com/sebdel/mra-tools-c
--
---------------------------------------------------------------------------------
-- DE10_lite Top level for Spy hunter (Midway MCR) by Dar (darfpga@aol.fr) (06/12/2019)
-- http://darfpga.blogspot.fr

81
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/TurboTag.qsf
View File

@ -41,7 +41,7 @@
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
@ -117,38 +117,7 @@ set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
@ -158,7 +127,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY SpyHunter_MiST
set_global_assignment -name TOP_LEVEL_ENTITY TurboTag_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
@ -210,9 +179,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# end ENTITY(Kickman_MiST)
# ------------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/csd.stp
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
@ -223,22 +189,53 @@ set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE OFF
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TurboTag_MiST.sv
set_global_assignment -name VHDL_FILE rtl/turbo_tag.vhd
set_global_assignment -name VHDL_FILE rtl/turbo_tag_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/cheap_squeak_deluxe.vhd
set_global_assignment -name VHDL_FILE rtl/turbo_tag_control.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_counter.vhd
set_global_assignment -name VHDL_FILE rtl/ctc_controler.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_ch_bits.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/ttag_bg_bits_1.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/rom/midssio_82s123.vhd
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/turbo_tag_control.vhd
set_global_assignment -name VHDL_FILE rtl/cmos_ram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name QIP_FILE ../../../common/IO/Z80CTC/z80ctc.qip
set_global_assignment -name VHDL_FILE ../../../common/IO/pia6821.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/68000/FX68k/fx68k.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip

38
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/meta/Turbo Tag.mra Normal file
View File

@ -0,0 +1,38 @@
<misterromdescription>
<name>Turbo Tag</name>
<mameversion>0216</mameversion>
<mratimestamp>202001010000</mratimestamp>
<year>1983</year>
<manufacturer>Bally Midway</manufacturer>
<category>Action</category>
<setname>turbotag</setname>
<rom index="0" zip="turbotag.zip" md5="83494589c7ec76729e0d776d999e3a70" type="merged|nonmerged">
<part name="ttprog0.bin"/>
<part name="ttprog1.bin"/>
<part name="ttprog2.bin"/>
<part name="ttprog3.bin"/>
<part name="ttprog4.bin"/>
<part name="ttprog5.bin"/>
<part name="ttprog5.bin"/>
<part name="ttprog5.bin"/>
<part name="ttu17.bin"/>
<part name="ttu18.bin"/>
<part name="ttu7.bin"/>
<part name="ttu8.bin"/>
<part name="ttfg1.bin"/>
<part name="ttfg0.bin"/>
<part name="ttfg3.bin"/>
<part name="ttfg2.bin"/>
<part name="ttfg5.bin"/>
<part name="ttfg4.bin"/>
<part name="ttfg7.bin"/>
<part name="ttfg6.bin"/>
<part name="ttbg0.bin"/>
<part name="ttbg1.bin"/>
<part name="ttbg2.bin"/>
<part name="ttbg3.bin"/>
<part name="ttan.bin"/>
</rom>
</misterromdescription>

233
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/TurboTag_MiST.sv
View File

@ -1,5 +1,5 @@
//============================================================================
// Arcade: Spy Hunter by DarFPGA
// Arcade: TurboTag, based on SpyHunter by Dar
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
@ -16,7 +16,7 @@
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module SpyHunter_MiST(
module TurboTag_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
@ -56,6 +56,10 @@ localparam CONF_STR = {
"V,v1.0.",`BUILD_DATE
};
wire rotate = status[2];
wire blend = status[5];
wire service = status[6];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_mem;
assign SDRAM_CKE = 1;
@ -77,11 +81,33 @@ wire [15:0] joystick_0;
wire [15:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [15:0] audio_l, audio_r;
wire [9:0] csd_audio;
wire hs, vs, cs;
wire blankn;
wire [2:0] g, r, b;
wire no_csync;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [15:0] rom_addr;
wire [15:0] rom_do;
wire [14:1] csd_addr;
@ -93,8 +119,6 @@ wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire [7:0] steering;
wire [7:0] gas;
data_io data_io(
.clk_sys ( clk_sys ),
@ -110,38 +134,16 @@ data_io data_io(
// ROM structure:
// 0000 - DFFF - Main ROM (8 bit)
// E000 - FFFF - Super Sound board ROM (8 bit)
// 10000 - 17FFF - CSD ROM (16 bit)
// 18000 - Sprite ROMs (32 bit)
// spy-hunter_cpu_pg0_2-9-84.6d
// spy-hunter_cpu_pg1_2-9-84.7d
// spy-hunter_cpu_pg2_2-9-84.8d
// spy-hunter_cpu_pg3_2-9-84.9d
// spy-hunter_cpu_pg4_2-9-84.10d
// spy-hunter_cpu_pg5_2-9-84.11d
// spy-hunter_snd_0_sd_11-18-83.a7
// spy-hunter_snd_1_sd_11-18-83.a8
// spy-hunter_cs_deluxe_u17_b_11-18-83.u17
// spy-hunter_cs_deluxe_u18_d_11-18-83.u18
// spy-hunter_cs_deluxe_u7_a_11-18-83.u7
// spy-hunter_cs_deluxe_u8_c_11-18-83.u8
// spy-hunter_video_1fg_11-18-83.a7
// spy-hunter_video_0fg_11-18-83.a8
// spy-hunter_video_3fg_11-18-83.a5
// spy-hunter_video_2fg_11-18-83.a6
// spy-hunter_video_5fg_11-18-83.a3
// spy-hunter_video_4fg_11-18-83.a4
// spy-hunter_video_7fg_11-18-83.a1
// spy-hunter_video_6fg_11-18-83.a2
// 0000 - DFFF - Main ROM (8 bit) ttprog0.bin ttprog1.bin ttprog2.bin ttprog3.bin ttprog4.bin ttprog5.bin ttprog5.bin
// E000 - FFFF - Super Sound board ROM (8 bit) empty
// 10000 - 17FFF - CSD ROM (16 bit) ttu17.bin ttu18.bin ttu7.bin ttu8.bin
// 18000 - 37FFF - Sprite ROMs (32 bit) ttfg1.bin ttfg0.bin ttfg3.bin ttfg2.bin ttfg5.bin ttfg4.bin ttfg7.bin ttfg6.bin
// 38000 - 3FFFF - BG
// 40000 - 40FFF - Char
wire [24:0] rom_ioctl_addr = ~ioctl_addr[16] ? ioctl_addr : // 8 bit ROMs
{ioctl_addr[24:16], ioctl_addr[15], ioctl_addr[13:0], ioctl_addr[14]}; // 16 bit ROM
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000;
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h18000;
reg port1_req, port2_req;
sdram sdram(
@ -161,7 +163,7 @@ sdram sdram(
.cpu1_addr ( ioctl_downl ? 16'hffff : {1'b0, rom_addr[15:1]} ),
.cpu1_q ( rom_do ),
// need higher priority for CSD
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h7000 + csd_addr[14:1]) ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h8000 + csd_addr[14:1]) ),
.cpu2_q ( csd_do ),
.cpu3_addr ( 16'hffff ),
.cpu3_q ( ),
@ -169,7 +171,7 @@ sdram sdram(
// port2 for sprite graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words
.port2_a ( {sp_ioctl_addr[23:17], sp_ioctl_addr[14:0], sp_ioctl_addr[16]} ), // merge sprite roms to 32-bit wide words
.port2_ds ( {sp_ioctl_addr[15], ~sp_ioctl_addr[15]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
@ -197,29 +199,18 @@ reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
reg [15:0] reset_count;
ioctl_downlD <= ioctl_downl;
// generate a second reset signal - needed for some reason
if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
else if (reset_count != 0) reset_count <= reset_count - 1'd1;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded | (reset_count == 16'h0001);
reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
end
turbo_tag_control turbo_tagcontrol(
.clock_40(clk_sys),
.reset(reset),
.vsync(vs),
.gas_plus(m_up),
.gas_minus(m_down),
.steering_plus(m_right),
.steering_minus(m_left),
.steering(steering),
.gas(gas)
);
wire [15:0] audio_l, audio_r;
wire [9:0] csd_audio;
wire hs, vs, cs;
wire blankn;
wire [2:0] g, r, b;
turbo_tag turbo_tag(
.clock_40(clk_sys),
@ -236,29 +227,34 @@ turbo_tag turbo_tag(
.audio_out_l(audio_l),
.audio_out_r(audio_r),
.csd_audio_out(csd_audio),
.coin1(btn_coin),
.coin2(1'b0),
.coin1(m_coin1),
.coin2(m_coin2),
.gas(gas),
.steering(steering),
.start1(btn_one_player),
.start2(btn_two_players),
.shift(m_fire1),
.left(m_left),
.center(btn_fire2),
.right(m_right),
.service(status[6]),
.start1(m_one_player | m_fireE),
.start2(m_two_players | m_fireF),
.shift(shift_state),
.left(m_fireB),
.center(m_fireC),
.right(m_fireD),
.service(service),
.cpu_rom_addr ( rom_addr ),
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.csd_rom_addr ( csd_addr ),
.csd_rom_do ( csd_do ),
.sp_addr ( sp_addr ),
.sp_graphx32_do ( sp_do )
.sp_graphx32_do ( sp_do ),
.dl_addr ( ioctl_addr[18:0]),
.dl_data ( ioctl_dout ),
.dl_wr ( ioctl_wr )
);
wire vs_out;
wire hs_out;
assign VGA_VS = scandoublerD | vs_out;
assign VGA_HS = scandoublerD ? cs : hs_out;
assign VGA_HS = ((~no_csync & scandoublerD) || ypbpr)? cs : hs_out;
assign VGA_VS = ((~no_csync & scandoublerD) || ypbpr)? 1'b1 : vs_out;
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
@ -275,35 +271,14 @@ mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.VGA_B ( VGA_B ),
.VGA_VS ( vs_out ),
.VGA_HS ( hs_out ),
.rotate ( {1'b1,status[2]} ),
.rotate ( { 1'b1, rotate } ),
.ce_divider ( 1 ),
.blend ( status[5] ),
.blend ( blend ),
.scandoubler_disable(1),//scandoublerD ),
.no_csync ( 1'b1 ),
.ypbpr ( ypbpr )
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(10))
dac_l(
@ -322,46 +297,42 @@ dac_r(
.dac_o(AUDIO_R)
);
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5];
wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6];
wire m_fire4 = btn_fire4 | joystick_0[7] | joystick_1[7];
wire [7:0] steering;
wire [7:0] gas;
turbo_tag_control turbo_tag_control
(
.clock_40(clk_sys),
.reset(reset),
.vsync(vs),
.gas_plus(m_up),
.gas_minus(m_down),
.steering_plus(m_right),
.steering_minus(m_left),
.steering(steering),
.gas(gas)
);
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_fire4 = 0;
reg btn_coin = 0;
reg btn_one_player = 0;
reg btn_two_players = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire shift_state;
input_toggle gearbox(clk_sys, m_coin1 | m_coin2, m_fireA, shift_state);
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h12: btn_fire4 <= key_pressed; // shift left
'h14: btn_fire3 <= key_pressed; // ctrl left
'h11: btn_fire2 <= key_pressed; // alt left
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( 1'b0 ),
.orientation ( 2'b10 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/ctc_controler.vhd
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@ -1,106 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC controler by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_controler is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
int_ack : in std_logic;
int_pulse_0 : in std_logic;
int_pulse_1 : in std_logic;
int_pulse_2 : in std_logic;
int_pulse_3 : in std_logic;
d_out : out std_logic_vector( 7 downto 0);
int_n : out std_logic
);
end ctc_controler;
architecture struct of ctc_controler is
signal int_vector : std_logic_vector(4 downto 0);
signal wait_for_time_constant : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
signal int_reg_0 : std_logic;
signal int_reg_1 : std_logic;
signal int_reg_2 : std_logic;
signal int_reg_3 : std_logic;
signal int_ack_r : std_logic;
begin
int_n <= '0' when (int_reg_0 or int_reg_1 or int_reg_2 or int_reg_3) = '1' else '1';
d_out <= int_vector & "000" when int_reg_0 = '1' else
int_vector & "010" when int_reg_1 = '1' else
int_vector & "100" when int_reg_2 = '1' else
int_vector & "110" when int_reg_3 = '1' else (others => '0');
process (reset, clock)
begin
if reset = '1' then -- hardware and software reset
wait_for_time_constant <= '0';
int_reg_0 <= '0';
int_reg_1 <= '0';
int_reg_2 <= '0';
int_reg_3 <= '0';
load_data_r <= load_data;
int_vector <= (others => '0');
else
if rising_edge(clock) then
if clock_ena = '1' then
load_data_r <= load_data;
int_ack_r <= int_ack;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
else
if d_in(0) = '1' then -- check if its a control world
wait_for_time_constant <= d_in(2);
-- if d_in(1) = '1' then -- software reset
-- wait_for_time_constant <= '0';
-- end if;
else -- its an interrupt vector
int_vector <= d_in(7 downto 3);
end if;
end if;
end if;
if int_pulse_0 = '1' then int_reg_0 <= '1'; end if;
if int_pulse_1 = '1' then int_reg_1 <= '1'; end if;
if int_pulse_2 = '1' then int_reg_2 <= '1'; end if;
if int_pulse_3 = '1' then int_reg_3 <= '1'; end if;
if int_ack_r = '1' and int_ack = '0' then
if int_reg_0 = '1' then int_reg_0 <= '0';
elsif int_reg_1 = '1' then int_reg_1 <= '0';
elsif int_reg_2 = '1' then int_reg_2 <= '0';
elsif int_reg_3 = '1' then int_reg_3 <= '0'; end if;
end if;
end if;
end if;
end if;
end process;
end struct;

152
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/ctc_counter.vhd
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@ -1,152 +0,0 @@
---------------------------------------------------------------------------------
-- Z80-CTC counter by Dar (darfpga@aol.fr) (19/10/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ctc_counter is
port(
clock : in std_logic;
clock_ena : in std_logic;
reset : in std_logic;
d_in : in std_logic_vector( 7 downto 0);
load_data : in std_logic;
clk_trg : in std_logic;
d_out : out std_logic_vector(7 downto 0);
zc_to : out std_logic;
int_pulse : out std_logic
);
end ctc_counter;
architecture struct of ctc_counter is
signal control_word : std_logic_vector(7 downto 0);
signal wait_for_time_constant : std_logic;
signal time_constant_loaded : std_logic;
signal restart_on_next_clock : std_logic;
signal restart_on_next_trigger : std_logic;
signal prescale_max : std_logic_vector(7 downto 0);
signal prescale_in : std_logic_vector(7 downto 0) := (others => '0');
signal count_max : std_logic_vector(8 downto 0);
signal count_in : std_logic_vector(8 downto 0) := (others => '0');
signal zc_to_in : std_logic;
signal clk_trg_r : std_logic;
signal trigger : std_logic;
signal count_ena : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
begin
prescale_max <=
(others => '0') when control_word(6) = '1' else -- counter mode (prescale max = 0)
X"0F" when control_word(6 downto 5) = "00" else -- timer mode prescale 16
X"FF"; -- timer mode prescale 256
trigger <=
'1' when (clk_trg = '0' and clk_trg_r = '1' and control_word(4) = '0') or -- falling edge
(clk_trg = '1' and clk_trg_r = '0' and control_word(4) = '1') else '0'; -- rising edge
d_out <= count_in(7 downto 0);
zc_to <= zc_to_in;
int_pulse <= zc_to_in when control_word(7) = '1' else '0';
process (reset, clock)
begin
if reset = '1' then -- hardware reset
count_ena <= '0';
wait_for_time_constant <= '0';
time_constant_loaded <= '0';
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_in <= (others=> '0');
zc_to_in <= '0';
clk_trg_r <= clk_trg;
else
if rising_edge(clock) then
if clock_ena = '1' then
clk_trg_r <= clk_trg;
load_data_r <= load_data;
if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
count_ena <= '1';
count_in <= count_max;
prescale_in <= prescale_max;
end if;
if load_data = '1' and load_data_r = '0' then
if wait_for_time_constant = '1' then
wait_for_time_constant <= '0';
time_constant_loaded <= '1';
if d_in = X"00" then
count_max <= '1'&X"00";
else
count_max <= '0'&d_in;
end if;
if control_word(6) = '0' and count_ena = '0' then -- in timer mode, if count was stooped
if control_word(3) = '0' then -- auto start when time_constant loaded
restart_on_next_clock <= '1';
else -- wait for trigger to start
restart_on_next_trigger <= '1';
end if;
end if;
else -- not waiting for time constant
if d_in(0) = '1' then -- check if its a control world
control_word <= d_in;
wait_for_time_constant <= d_in(2);
restart_on_next_clock <= '0';
restart_on_next_trigger <= '0';
if d_in(1) = '1' then -- software reset
count_ena <= '0';
time_constant_loaded <= '0';
zc_to_in <= '0';
-- zc_to_in_r <= '0';
clk_trg_r <= clk_trg;
end if;
end if;
end if;
end if; -- end load data
-- counter
zc_to_in <= '0';
if ((control_word(6) = '1' and trigger = '1' ) or
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
if prescale_in = 0 then
prescale_in <= '0'&prescale_max(7 downto 1); -- test divide by 2 !
if count_in = 0 then
zc_to_in <= '1';
count_in <= count_max;
else
count_in <= count_in - '1';
end if;
else
prescale_in <= prescale_in - '1';
end if;
end if;
end if;
end if;
end if;
end process;
end struct;

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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/dpram.vhd Normal file
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@ -0,0 +1,81 @@
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/ttag_bg_bits_1.vhd
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Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/ttag_bg_bits_2.vhd
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278
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/rom/ttag_ch_bits.vhd
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@ -1,278 +0,0 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity ttag_ch_bits is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of ttag_ch_bits is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"AB",X"AA",X"AA",X"EA",X"AB",X"AA",X"AF",X"FE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"3F",X"FC",X"C0",X"03",X"CC",X"33",X"CC",X"33",X"CC",X"33",X"CF",X"F3",X"C0",X"03",X"3F",X"FC",
X"AA",X"AA",X"AA",X"AE",X"AA",X"AE",X"AF",X"FE",X"AA",X"AA",X"AF",X"EA",X"AE",X"EA",X"AF",X"FE",
X"AA",X"AA",X"AF",X"EA",X"AA",X"FE",X"AF",X"EA",X"AA",X"AA",X"AB",X"FE",X"AF",X"BA",X"AB",X"FE",
X"AA",X"AA",X"AF",X"BE",X"AE",X"EA",X"AF",X"FE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE",
X"AF",X"FE",X"AE",X"AA",X"AE",X"AA",X"AF",X"EA",X"AE",X"EA",X"AF",X"FE",X"AA",X"AA",X"AF",X"FE",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AF",X"AA",X"AA",X"FE",X"AF",X"AA",X"AE",X"AA",X"AE",X"AA",
X"AF",X"EA",X"AE",X"EA",X"AF",X"FE",X"AA",X"AA",X"AE",X"FE",X"AE",X"EE",X"AF",X"EE",X"AA",X"AA",
X"AE",X"AE",X"AE",X"AE",X"AF",X"FE",X"AA",X"AA",X"AB",X"FE",X"AF",X"BA",X"AB",X"FE",X"AA",X"AA",
X"AE",X"FE",X"AE",X"EE",X"AF",X"EE",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE",X"AA",X"AA",
X"AC",X"00",X"AC",X"00",X"AC",X"FF",X"BC",X"EA",X"B0",X"FA",X"BC",X"3E",X"AF",X"0E",X"AB",X"FE",
X"00",X"0E",X"00",X"0E",X"FF",X"CE",X"AA",X"FE",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"AB",X"FE",X"AF",X"0E",X"BC",X"3E",X"B0",X"FA",X"BC",X"EA",X"AC",X"FF",X"AC",X"00",X"AC",X"00",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"FE",X"FF",X"CE",X"00",X"0E",X"00",X"0E",
X"AF",X"EA",X"AC",X"FF",X"AC",X"00",X"AC",X"00",X"AC",X"00",X"AC",X"00",X"AC",X"FF",X"AF",X"EA",
X"AB",X"CE",X"FF",X"0E",X"00",X"0E",X"00",X"0E",X"00",X"3E",X"00",X"FA",X"FF",X"EA",X"AA",X"AA",
X"AA",X"AA",X"AF",X"EA",X"AC",X"FF",X"AC",X"00",X"AC",X"00",X"AC",X"FF",X"AF",X"EA",X"AA",X"AA",
X"AA",X"AA",X"AA",X"AA",X"FF",X"EA",X"00",X"FA",X"00",X"3E",X"FF",X"0E",X"AB",X"CE",X"AA",X"CE",
X"AC",X"EA",X"AC",X"FA",X"AC",X"3F",X"AC",X"00",X"AC",X"00",X"AC",X"00",X"AC",X"FF",X"AF",X"EA",
X"B3",X"BE",X"F3",X"CE",X"00",X"0E",X"00",X"0E",X"00",X"0E",X"00",X"0E",X"FF",X"CE",X"AA",X"FE",
X"AA",X"AA",X"AA",X"FF",X"AB",X"C0",X"AB",X"00",X"AF",X"00",X"AC",X"03",X"AC",X"3F",X"AC",X"FA",
X"AA",X"FE",X"FA",X"CE",X"3E",X"CE",X"0F",X"0E",X"0C",X"0E",X"00",X"0E",X"C0",X"CE",X"F3",X"FE",
X"AC",X"EB",X"AC",X"FF",X"AC",X"00",X"AC",X"00",X"AC",X"00",X"AC",X"FF",X"AF",X"EA",X"AA",X"AA",
X"3A",X"CE",X"3F",X"CE",X"00",X"0E",X"00",X"0E",X"00",X"0E",X"FF",X"CE",X"AA",X"FE",X"AA",X"AA",
X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",X"AB",X"FF",X"AF",X"03",X"AC",X"00",X"AC",X"00",X"AC",X"FC",
X"AA",X"AA",X"BF",X"FA",X"F0",X"3E",X"C0",X"0E",X"00",X"0E",X"0F",X"0E",X"3F",X"CE",X"3A",X"CE",
X"AC",X"EA",X"AC",X"FA",X"AC",X"3F",X"AF",X"00",X"AB",X"00",X"AB",X"C0",X"AA",X"FC",X"AA",X"AF",
X"AA",X"CE",X"AB",X"CE",X"FF",X"0E",X"00",X"0E",X"00",X"3E",X"00",X"3A",X"00",X"FA",X"FF",X"EA",
X"AA",X"AF",X"AA",X"FC",X"AB",X"C0",X"AB",X"00",X"AF",X"00",X"AC",X"3F",X"AC",X"FA",X"AC",X"EA",
X"FF",X"EA",X"00",X"FA",X"00",X"3A",X"00",X"3E",X"00",X"0E",X"FF",X"0E",X"AB",X"CE",X"AA",X"CE",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"B0",X"00",X"B0",X"00",X"B0",X"00",X"B0",X"00",X"B0",X"00",X"B0",X"00",X"B0",X"00",X"B0",X"00",
X"FE",X"FE",X"9A",X"9A",X"55",X"56",X"75",X"D6",X"55",X"56",X"9A",X"9A",X"FE",X"FE",X"AA",X"AA",
X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"00",X"03",X"FF",X"FF",
X"AF",X"EA",X"AF",X"FE",X"AA",X"AA",X"AF",X"FE",X"AE",X"AE",X"AF",X"FE",X"AA",X"AA",X"AA",X"AA",
X"AA",X"AA",X"AA",X"AA",X"AE",X"EE",X"AE",X"EE",X"AF",X"FE",X"AA",X"AA",X"AF",X"FE",X"AA",X"BE",
X"AF",X"FF",X"BE",X"AB",X"BA",X"AB",X"BA",X"AB",X"BA",X"AB",X"BF",X"FF",X"BF",X"FF",X"AA",X"AA",
X"AA",X"AA",X"AA",X"AB",X"BF",X"FF",X"BF",X"FF",X"BA",X"AB",X"AA",X"AA",X"AA",X"AA",X"AA",X"AA",
X"BF",X"EB",X"BF",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"FF",X"BA",X"FF",X"AA",X"AA",
X"BF",X"FF",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"AB",X"BE",X"AF",X"BE",X"AF",X"AA",X"AA",
X"AA",X"EA",X"BF",X"FF",X"AA",X"EA",X"AA",X"EA",X"AA",X"EA",X"BF",X"EA",X"BF",X"EA",X"AA",X"AA",
X"BA",X"FF",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BF",X"EF",X"BF",X"EF",X"AA",X"AA",
X"BA",X"FF",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BF",X"FF",X"BF",X"FF",X"AA",X"AA",
X"BE",X"AA",X"BB",X"AA",X"BB",X"EA",X"BA",X"FF",X"BA",X"BF",X"BE",X"AA",X"BE",X"AA",X"AA",X"AA",
X"BF",X"FF",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BA",X"EB",X"BF",X"FF",X"BF",X"FF",X"AA",X"AA",
X"BF",X"FF",X"BF",X"FF",X"BA",X"EA",X"BA",X"EA",X"BA",X"EA",X"BA",X"EA",X"BF",X"EA",X"AA",X"AA",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

46
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/spinner.vhd Normal file
View File

@ -0,0 +1,46 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity spinner is
port(
clock_40 : in std_logic;
reset : in std_logic;
btn_left : in std_logic;
btn_right : in std_logic;
btn_acc : in std_logic; -- speed up button
ctc_zc_to_2 : in std_logic;
spin_angle : out std_logic_vector(7 downto 0)
);
end spinner;
architecture rtl of spinner is
signal ctc_zc_to_2_r : std_logic;
signal spin_count : std_logic_vector(9 downto 0);
begin
spin_angle <= spin_count(9 downto 2);
process (clock_40, reset)
begin
if reset = '1' then
spin_count <= (others => '0');
elsif rising_edge(clock_40) then
ctc_zc_to_2_r <= ctc_zc_to_2;
if ctc_zc_to_2_r ='0' and ctc_zc_to_2 = '1' then
if btn_acc = '0' then -- space -- speed up
if btn_left = '1' then spin_count <= spin_count - 20; end if; -- left
if btn_right = '1' then spin_count <= spin_count + 20; end if; -- right
else
if btn_left = '1' then spin_count <= spin_count - 55; end if;
if btn_right = '1' then spin_count <= spin_count + 55; end if;
end if;
end if;
end if;
end process;
end rtl;

251
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag.vhd
View File

@ -168,8 +168,11 @@ port(
csd_rom_addr : out std_logic_vector(14 downto 1);
csd_rom_do : in std_logic_vector(15 downto 0);
sp_addr : out std_logic_vector(14 downto 0);
sp_graphx32_do : in std_logic_vector(31 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0)
sp_graphx32_do : in std_logic_vector(31 downto 0);
-- internal ROM download
dl_addr : in std_logic_vector(18 downto 0);
dl_data : in std_logic_vector(7 downto 0);
dl_wr : in std_logic
);
end turbo_tag;
@ -193,6 +196,7 @@ architecture struct of turbo_tag is
signal cpu_ena : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_pc : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_wr_n : std_logic;
@ -201,31 +205,15 @@ architecture struct of turbo_tag is
signal cpu_ioreq_n : std_logic;
signal cpu_irq_n : std_logic;
signal cpu_m1_n : std_logic;
signal ctc_controler_we : std_logic;
signal ctc_controler_do : std_logic_vector(7 downto 0);
signal ctc_int_ack : std_logic;
signal cpu_int_ack_n : std_logic;
signal ctc_counter_0_we : std_logic;
-- signal ctc_counter_0_trg : std_logic;
signal ctc_counter_0_do : std_logic_vector(7 downto 0);
signal ctc_counter_0_int : std_logic;
signal ctc_ce : std_logic;
signal ctc_do : std_logic_vector(7 downto 0);
signal ctc_counter_1_we : std_logic;
-- signal ctc_counter_1_trg : std_logic;
signal ctc_counter_1_do : std_logic_vector(7 downto 0);
signal ctc_counter_1_int : std_logic;
signal ctc_counter_2_we : std_logic;
-- signal ctc_counter_2_trg : std_logic;
signal ctc_counter_2_do : std_logic_vector(7 downto 0);
signal ctc_counter_2_int : std_logic;
signal ctc_counter_3_we : std_logic;
signal ctc_counter_1_trg : std_logic;
signal ctc_counter_2_trg : std_logic;
signal ctc_counter_3_trg : std_logic;
signal ctc_counter_3_do : std_logic_vector(7 downto 0);
signal ctc_counter_3_int : std_logic;
-- signal cpu_rom_addr: std_logic_vector(15 downto 0);
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
@ -335,6 +323,10 @@ architecture struct of turbo_tag is
signal input_4 : std_logic_vector(7 downto 0);
signal output_4 : std_logic_vector(7 downto 0);
signal bg_graphics_1_we : std_logic;
signal bg_graphics_2_we : std_logic;
signal ch_graphics_we : std_logic;
begin
clock_vid <= clock_40;
@ -421,8 +413,8 @@ begin
if hcnt >= 2+16+16 and hcnt < 514+16-1 and
vcnt >= 1 and vcnt < 241 then video_blankn <= '1';end if;
if hs_cnt = 0 then hsync0 <= '0';
elsif hs_cnt = 47 then hsync0 <= '1';
if hs_cnt = 0 then hsync0 <= '0'; video_hs <= '0';
elsif hs_cnt = 47 then hsync0 <= '1'; video_hs <= '1';
end if;
if hs_cnt = 0 then hsync1 <= '0';
@ -479,7 +471,7 @@ end process;
--------------------
-- "11" for test & tilt & unused
input_0 <= not service & "11" & not shift & "11" & not coin2 & not coin1;
input_1 <= not service & "11" & not right & not start2 & not center & not left & not start1;
input_1 <= "111" & not right & not start2 & not center & not left & not start1;
input_2 <= steering when output_4(7) = '1' else gas;
input_3 <= x"FF";
input_4 <= x"FF";
@ -495,19 +487,15 @@ input_4 <= x"FF";
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------
cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E" else -- 0000-DFFF 56Ko
bg_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"F800") = x"E000" else -- video ram E000-E7FF 2Ko
ch_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- char ram E800-EBFF 1Ko + mirroring 0400
wram_do when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"F000" else -- work ram F000-F7FF 2Ko
sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FE00") = x"F800" else -- sprite ram F800-F9FF 512o
ctc_controler_do when cpu_ioreq_n = '0' and cpu_m1_n = '0' else -- ctc ctrl (interrupt vector)
ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
ctc_counter_3_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else
ctc_counter_2_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else
ctc_counter_1_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else
ctc_counter_0_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else
X"FF";
cpu_di <= x"82" when cpu_mreq_n = '0' and cpu_addr = x"0b53" and cpu_pc = x"0b2a" else -- checksum hack for bad ROM dump
cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) < X"E" else -- 0000-DFFF 56Ko
bg_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"F800") = x"E000" else -- video ram E000-E7FF 2Ko
ch_ram_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FC00") = x"E800" else -- char ram E800-EBFF 1Ko + mirroring 0400
wram_do when cpu_mreq_n = '0' and (cpu_addr and X"F800") = x"F000" else -- work ram F000-F7FF 2Ko
sp_ram_cache_do_r when cpu_mreq_n = '0' and (cpu_addr and x"FE00") = x"F800" else -- sprite ram F800-F9FF 512o
ctc_do when cpu_int_ack_n = '0' or ctc_ce = '1' else -- ctc (interrupt vector or counter data)
ssio_do when cpu_ioreq_n = '0' and cpu_addr(7 downto 5) = "000" else -- 0x00-0x1F
X"FF";
cpu_rom_addr <= cpu_addr when cpu_addr < x"A000" else cpu_addr xor x"6000"; -- last rom has upper/lower part swapped
@ -525,14 +513,10 @@ ssio_iowe <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' else '0';
------------------------------------------------------------------------
-- Misc registers : ctc write enable / interrupt acknowledge
------------------------------------------------------------------------
ctc_counter_3_trg <= '1' when (vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')else '0';
ctc_counter_3_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F3" else '0';
ctc_counter_2_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F2" else '0';
ctc_counter_1_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F1" else '0';
ctc_counter_0_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0';
ctc_controler_we <= '1' when cpu_wr_n = '0' and cpu_ioreq_n = '0' and cpu_addr(7 downto 0) = X"F0" else '0'; -- only channel 0 receive int vector
ctc_int_ack <= '1' when cpu_ioreq_n = '0' and cpu_m1_n = '0' else '0';
cpu_int_ack_n <= cpu_ioreq_n or cpu_m1_n;
ctc_ce <= '1' when cpu_ioreq_n = '0' and cpu_addr(7 downto 4) = x"F" else '0';
ctc_counter_2_trg <= '1' when (vcnt >= 240 and vcnt <= 262 and tv15Khz_mode = '1') or (vcnt >= 480 and tv15Khz_mode = '0') else '0';
ctc_counter_3_trg <= '1' when top_frame = '1' and ((vcnt = 246 and tv15Khz_mode = '1') or (vcnt = 493 and tv15Khz_mode = '0')) else '0';
process (clock_vid)
begin
@ -598,7 +582,7 @@ begin
sp_byte_cnt <= (others => '0');
when "000001" =>
sp_attr <= sp_ram_do;
when "000010" =>
when "000010" =>
sp_code <= sp_ram_do;
sp_addr <= sp_ram_do(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt xor sp_hflip); -- graphics rom addr
when "000011" =>
@ -607,10 +591,10 @@ when "000010" =>
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+1 xor sp_hflip); -- advance graphics rom addr
sp_on_line <= '1';
when "010010"|"011010"|"100010" => -- 18,26,34
when "010010"|"011010"|"100010" => -- 18,26,34
sp_graphx32_do_r <= sp_graphx32_do; -- latch incoming sprite data
sp_addr <= sp_code(7 downto 0) & (sp_line xor sp_vflip) & (sp_byte_cnt+2 xor sp_hflip); -- advance graphics rom addr
sp_byte_cnt <= sp_byte_cnt + 1;
sp_byte_cnt <= sp_byte_cnt + 1;
when "101010" => -- 42
sp_on_line <= '0';
sp_input_phase <= (others => '0');
@ -621,7 +605,7 @@ when "000010" =>
end case;
sp_mux_roms <= sp_input_phase(2 downto 1);
end if;
if pix_ena = '1' then
if hcnt(0) = '0' then
sp_buffer_ram1_do_r <= sp_buffer_ram1b_do & sp_buffer_ram1a_do;
@ -800,6 +784,17 @@ end process;
-- components & sound board --
------------------------------
process (clock_vid)
begin
if rising_edge(clock_vid) then
if cpu_ena = '1' then
if cpu_m1_n = '0' and cpu_mreq_n = '0' then
cpu_pc <= cpu_addr;
end if;
end if;
end if;
end process;
-- microprocessor Z80
cpu : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
@ -824,92 +819,28 @@ port map(
DO => cpu_do
);
-- CTC interrupt controler Z80-CTC (MK3882)
ctc_controler : entity work.ctc_controler
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_controler_we,
int_ack => ctc_int_ack,
int_pulse_0 => ctc_counter_0_int,
int_pulse_1 => ctc_counter_1_int,
int_pulse_2 => ctc_counter_2_int,
int_pulse_3 => ctc_counter_3_int,
d_out => ctc_controler_do,
int_n => cpu_irq_n
);
ctc_counter_0 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_0_we,
clk_trg => '0',
d_out => ctc_counter_0_do,
zc_to => open, -- zc/to #0 (pin 7) connected to clk_trg #1 (pin 22) on schematics (seems to be not used)
int_pulse => ctc_counter_0_int
);
ctc_counter_1 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_1_we,
clk_trg => '0',
d_out => ctc_counter_1_do,
zc_to => open,
int_pulse => ctc_counter_1_int
);
ctc_counter_2 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_2_we,
clk_trg => '0',
d_out => ctc_counter_2_do,
zc_to => open,
int_pulse => ctc_counter_2_int
);
ctc_counter_3 : entity work.ctc_counter
port map(
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
d_in => cpu_do,
load_data => ctc_counter_3_we,
clk_trg => ctc_counter_3_trg,
d_out => ctc_counter_3_do,
zc_to => open,
int_pulse => ctc_counter_3_int
-- Z80-CTC (MK3882)
z80ctc : entity work.z80ctc_top
port map (
clock => clock_vid,
clock_ena => cpu_ena,
reset => reset,
din => cpu_do,
cpu_din => cpu_di,
dout => ctc_do,
ce_n => not ctc_ce,
cs => cpu_addr(1 downto 0),
m1_n => cpu_m1_n,
iorq_n => cpu_ioreq_n,
rd_n => cpu_rd_n,
int_n => cpu_irq_n,
trg0 => '0',
to0 => ctc_counter_1_trg,
trg1 => ctc_counter_1_trg,
to1 => open,
trg2 => '0',
to2 => open,
trg3 => ctc_counter_3_trg
);
-- cpu program ROM 0x0000-0xDFFF
@ -1020,28 +951,46 @@ port map(
);
-- char graphics ROM 10G
ch_graphics : entity work.ttag_ch_bits
ch_graphics : entity work.dpram
generic map( dWidth => 8, aWidth => 12)
port map(
clk => clock_vidn,
addr => ch_code_line,
data => ch_graphx_do
clk_a => clock_vidn,
addr_a => ch_code_line,
q_a => ch_graphx_do,
clk_b => clock_vid,
we_b => ch_graphics_we,
addr_b => dl_addr(11 downto 0),
d_b => dl_data
);
ch_graphics_we <= '1' when dl_addr(18 downto 12) = "1000000" and dl_wr = '1' else '0'; -- 40000 - 40FFF
-- background graphics ROM 3A/4A
bg_graphics_1 : entity work.ttag_bg_bits_1
bg_graphics_1 : entity work.dpram
generic map( dWidth => 8, aWidth => 14)
port map(
clk => clock_vidn,
addr => bg_code_line,
data => bg_graphx1_do
clk_a => clock_vidn,
addr_a => bg_code_line,
q_a => bg_graphx1_do,
clk_b => clock_vid,
we_b => bg_graphics_1_we,
addr_b => dl_addr(13 downto 0),
d_b => dl_data
);
bg_graphics_1_we <= '1' when dl_addr(18 downto 14) = "01110" and dl_wr = '1' else '0'; -- 38000 - 3BFFF
-- background graphics ROM 5A/6A
bg_graphics_2 : entity work.ttag_bg_bits_2
bg_graphics_2 : entity work.dpram
generic map( dWidth => 8, aWidth => 14)
port map(
clk => clock_vidn,
addr => bg_code_line,
data => bg_graphx2_do
clk_a => clock_vidn,
addr_a => bg_code_line,
q_a => bg_graphx2_do,
clk_b => clock_vid,
we_b => bg_graphics_2_we,
addr_b => dl_addr(13 downto 0),
d_b => dl_data
);
bg_graphics_2_we <= '1' when dl_addr(18 downto 14) = "01111" and dl_wr = '1' else '0'; -- 3C000 - 3FFFF
-- background & sprite palette
palette : entity work.gen_ram

24
Arcade_MiST/Midway MCR Scroll/TurboTag_MiST/rtl/turbo_tag_sound_board.vhd
View File

@ -101,7 +101,7 @@ architecture struct of turbo_tag_sound_board is
signal cpu_irq_n : std_logic;
signal cpu_m1_n : std_logic;
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
signal cpu_rom_do : std_logic_vector( 7 downto 0) := x"FF";
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
@ -214,16 +214,16 @@ ena_4Mhz <= '1' when clock_cnt1 = "00000" or
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------
cpu_di <= --cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF
iram_0_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9000" else
iram_1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9001" else
iram_2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9002" else
iram_3_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9003" else
ay1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"A" else
ay2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"B" else
x"FF" when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"F" else -- 0xF000 (sw3 dip - D14)
X"FF";
cpu_di <= cpu_rom_do when cpu_mreq_n = '0' and cpu_addr(15 downto 14) = "00" else -- 0x0000-0x3FFF
wram_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12) = X"8" else -- 0x8000-0x83FF
iram_0_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9000" else
iram_1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9001" else
iram_2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9002" else
iram_3_do when cpu_mreq_n = '0' and cpu_addr(15 downto 0)= X"9003" else
ay1_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"A" else
ay2_do when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"B" else
x"FF" when cpu_mreq_n = '0' and cpu_addr(15 downto 12)= X"F" else -- 0xF000 (sw3 dip - D14)
X"FF";
------------------------------------------
-- write enable to working ram from CPU --
@ -443,8 +443,6 @@ port map(
-- data => cpu_rom_do
--);
--cpu_rom_addr <= cpu_addr(12 downto 0);
-- working RAM 0x8000-0x83FF
wram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 10)