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Rename extension

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This commit is contained in:
Marcel 2019-09-09 13:07:31 +02:00
parent 2da65ca655
commit 798fcbdb5d
3 changed files with 2 additions and 4 deletions
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2
Arcade_MiST/Bagman Hardware/Super Bagman_MiST/rtl/bagman_mist.sv
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@ -28,7 +28,7 @@ module bagman_mist (
);
`include "rtl\build_id.sv"
`include "rtl\build_id.v"
localparam CONF_STR = {
"SBAGMAN;;",

2
Arcade_MiST/Bagman Hardware/Super Bagman_MiST/rtl/build_id.sv
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@ -1,2 +0,0 @@
`define BUILD_DATE "190909"
`define BUILD_TIME "130142"

2
Arcade_MiST/Bagman Hardware/Super Bagman_MiST/rtl/build_id.tcl
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@ -17,7 +17,7 @@ proc generateBuildID_Verilog {} {
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.sv"
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source