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Arcade Jungler WIP

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Marcel
2019-10-02 21:44:23 +02:00
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31
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "Jungler"

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Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 16:37:48 September 22, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# RallyX_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name TOP_LEVEL_ENTITY jungler_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------
# start ENTITY(rallyX_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(rallyX_mist)
# -----------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/jungler_mist.sv
set_global_assignment -name VERILOG_FILE rtl/jng_top.v
set_global_assignment -name VERILOG_FILE rtl/jng_video.v
set_global_assignment -name VERILOG_FILE rtl/jng_hvgen.v
set_global_assignment -name VERILOG_FILE rtl/jng_sprite.v
set_global_assignment -name VHDL_FILE "rtl/jng _sound.vhd"
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
set_global_assignment -name VERILOG_FILE rtl/rams.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_prg_rom.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_dot_rom.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_chr_rom.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_pal_rom.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_col_rom.vhd
set_global_assignment -name VHDL_FILE rtl/roms/jng_snd_rom.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80s.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T65/T65.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/Jungler.srf Normal file
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{ "" "" "" "Variable or input pin \"data_b\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Found combinational loop of 47 nodes" { } { } 0 332125 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_hdmi:pll_hdmi\|pll_hdmi_0002:pll_hdmi_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Net \"soc_system:soc_system\|soc_system_Video_Output:video_output\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1\[1\]\" is missing source, defaulting to GND" { } { } 0 12110 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"zxspectrum:emu\|mist_io:mist_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|h_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_h_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|v_sync_polarity_reg\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_v_sync_polarity\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "No destination clock period was found satisfying the set_net_delay assignment from \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|interlaced_field_reg\[*\]\}\]\" to \"\[get_keepers \{soc_system\|video_output\|cvo_core\|mode_banks\|vid_interlaced_field\[*\]\}\]\". This assignment will be ignored." { } { } 0 17897 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "55 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_kbd_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Inferred RAM node \"emu:emu\|mister_io:mister_io\|ps2_mouse_fifo_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(97): object \"io_win\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at de10_top.v(102): object \"io_sdd\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Overwriting existing clock: vip\|hps\|fpga_interfaces\|clocks_resets\|h2f_user0_clk" { } { } 0 332043 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Variable or input pin \"data_a\" is defined but never used." { } { } 0 287013 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at T65.vhd(100): object \"D\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at T65.vhd(125): object \"B_o\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 169085 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 174073 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332174 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 13009 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 21300 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_mode_banks" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_pll.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_frame_counter.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_memphy.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_ldc.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0_acv_hard_io_pads.v" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hard_memory_controller_top_cyclonev.sv" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "genlock_enable_sync" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "u_calculate_mode" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "genlock_enable" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "reset_value" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_pll_video:pll_video\|altera_pll:altera_pll_i\|general\[0\].gpll" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_cvo_core.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_packet_transfer.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "hps_sdram_p0.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_common_dc_mixed_widths_fifo.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "altera_mem_if_hhp_qseq_synth_top" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_vout:vip_vout\|alt_vip_cvo_core:cvo_core\|genlock_enable_sync1" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_vip_fb:vip_fb\|alt_vip_packet_transfer:pkt_trans_rd\|alt_vip_packet_transfer_read_proc:READ_BLOCK.read_proc_instance\|alt_vip_common_fifo2:output_msg_queue\|scfifo:scfifo_component\|scfifo_scd1:auto_generated\|a_dpfifo_e471:dpfifo\|altsyncram_ums1:FIFOram\|q_b" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Video_Input:video_input\|alt_vip_cvi_core:cvi_core\|alt_vip_cvi_write_fifo_buffer:write_fifo_buffer" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system:soc_system\|soc_system_Frame_Buffer:frame_buffer\|alt_vip_packet_transfer:pkt_trans_rd" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system_hps_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "soc_system_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "RST" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_scaler_alg_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "cvo_core" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "vip_HPS_fpga_interfaces.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_vof_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "alt_vip_dil_scheduler.sdc" { } { } 0 9999 "" 0 0 "Quartus II" 0 -1 0 ""}

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Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/README.txt Normal file
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---------------------------------------------------------------------------------
--
-- Arcade: Jungler port to MiST
-- xx xxxx 20xx
-- From: https://github.com/MrX-8B/MiSTer-Arcade-RallyX
--
Todo: Sound ,GFX and some Controls
---------------------------------------------------------------------------------
-- FPGA New Rally-X for Spartan-3 Starter Board
------------------------------------------------
-- Copyright (c) 2005 MiSTer-X
---------------------------------------------------------------------------------
-- T80/T80s - Version : 0242
-----------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)

BIN
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 301 more merging
-- Ver 300 Bugfixes by ehenciak added, started tidyup *bust*
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
-- ehenciak 2-23-2005 : Added the enable signal so that one doesn't have to use
-- the ready signal to limit the CPU.
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Enable : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0) := x"00";
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal AddY : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
signal really_rdy : std_logic;
signal R_W_n_i : std_logic;
begin
-- ehenciak : gate Rdy with read/write to make an "OK, it's
-- really OK to stop the processor now if Rdy is
-- deasserted" signal
really_rdy <= Rdy or not(R_W_n_i);
-- ehenciak : Drive R_W_n_i off chip.
R_W_n <= R_W_n_i;
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "00" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
AddY => AddY,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write
);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q
);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n_i <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
R_W_n_i <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
--
-- jump control logic
--
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others => null;
end case;
end if;
end if;
end if;
end process;
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1'
else "0" & PC(7 downto 0);
process (Clk)
begin
if Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
--if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' and IRQCycle = '0' then
-- P(Flag_B) <= '1';
--end if;
--if IR = "00000000" and MCycle = "100" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
-- P(Flag_I) <= '1';
-- P(Flag_B) <= B_o;
--end if;
-- B=1 always on the 6502
P(Flag_B) <= '1';
if IR = "00000000" and RstCycle = '0' and (NMICycle = '1' or IRQCycle = '1') then
if MCycle = "011" then
-- B=0 in *copy* of P pushed onto the stack
P(Flag_B) <= '0';
elsif MCycle = "100" then
P(Flag_I) <= '1';
end if;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (Rdy = '1') then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
-- ehenciak : modified to use Y register as well (bugfix)
if ADAdd = '1' then
if (AddY = '1') then
AD <= std_logic_vector(unsigned(AD) + unsigned(Y(7 downto 0)));
else
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if (Enable = '1') then
if (really_rdy = '1') then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 6502 compatible microprocessor core
--
-- Version : 0245
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
-- 0245 : First version
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65_ALU is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end T65_ALU;
architecture rtl of T65_ALU is
-- AddSub variables (temporary signals)
signal ADC_Z : std_logic;
signal ADC_C : std_logic;
signal ADC_V : std_logic;
signal ADC_N : std_logic;
signal ADC_Q : std_logic_vector(7 downto 0);
signal SBC_Z : std_logic;
signal SBC_C : std_logic;
signal SBC_V : std_logic;
signal SBC_N : std_logic;
signal SBC_Q : std_logic_vector(7 downto 0);
begin
process (P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(6 downto 0);
variable C : std_logic;
begin
AL := resize(unsigned(BusA(3 downto 0) & P_In(Flag_C)), 7) + resize(unsigned(BusB(3 downto 0) & "1"), 7);
AH := resize(unsigned(BusA(7 downto 4) & AL(5)), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
ADC_Z <= '1';
else
ADC_Z <= '0';
end if;
if AL(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AL(6 downto 1) := AL(6 downto 1) + 6;
end if;
C := AL(6) or AL(5);
AH := resize(unsigned(BusA(7 downto 4) & C), 7) + resize(unsigned(BusB(7 downto 4) & "1"), 7);
ADC_N <= AH(4);
ADC_V <= (AH(4) xor BusA(7)) and not (BusA(7) xor BusB(7));
-- pragma translate_off
if is_x(std_logic_vector(AH)) then AH := "0000000"; end if;
-- pragma translate_on
if AH(5 downto 1) > 9 and P_In(Flag_D) = '1' then
AH(6 downto 1) := AH(6 downto 1) + 6;
end if;
ADC_C <= AH(6) or AH(5);
ADC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB)
variable AL : unsigned(6 downto 0);
variable AH : unsigned(5 downto 0);
variable C : std_logic;
begin
C := P_In(Flag_C) or not Op(0);
AL := resize(unsigned(BusA(3 downto 0) & C), 7) - resize(unsigned(BusB(3 downto 0) & "1"), 6);
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(5)), 6);
-- pragma translate_off
if is_x(std_logic_vector(AL)) then AL := "0000000"; end if;
if is_x(std_logic_vector(AH)) then AH := "000000"; end if;
-- pragma translate_on
if AL(4 downto 1) = 0 and AH(4 downto 1) = 0 then
SBC_Z <= '1';
else
SBC_Z <= '0';
end if;
SBC_C <= not AH(5);
SBC_V <= (AH(4) xor BusA(7)) and (BusA(7) xor BusB(7));
SBC_N <= AH(4);
if P_In(Flag_D) = '1' then
if AL(5) = '1' then
AL(5 downto 1) := AL(5 downto 1) - 6;
end if;
AH := resize(unsigned(BusA(7 downto 4) & "0"), 6) - resize(unsigned(BusB(7 downto 4) & AL(6)), 6);
if AH(5) = '1' then
AH(5 downto 1) := AH(5 downto 1) - 6;
end if;
end if;
SBC_Q <= std_logic_vector(AH(4 downto 1) & AL(4 downto 1));
end process;
process (Op, P_In, BusA, BusB,
ADC_Z, ADC_C, ADC_V, ADC_N, ADC_Q,
SBC_Z, SBC_C, SBC_V, SBC_N, SBC_Q)
variable Q_t : std_logic_vector(7 downto 0);
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
P_Out <= P_In;
Q_t := BusA;
case Op(3 downto 0) is
when "0000" =>
-- ORA
Q_t := BusA or BusB;
when "0001" =>
-- AND
Q_t := BusA and BusB;
when "0010" =>
-- EOR
Q_t := BusA xor BusB;
when "0011" =>
-- ADC
P_Out(Flag_V) <= ADC_V;
P_Out(Flag_C) <= ADC_C;
Q_t := ADC_Q;
when "0101" | "1101" =>
-- LDA
when "0110" =>
-- CMP
P_Out(Flag_C) <= SBC_C;
when "0111" =>
-- SBC
P_Out(Flag_V) <= SBC_V;
P_Out(Flag_C) <= SBC_C;
Q_t := SBC_Q;
when "1000" =>
-- ASL
Q_t := BusA(6 downto 0) & "0";
P_Out(Flag_C) <= BusA(7);
when "1001" =>
-- ROL
Q_t := BusA(6 downto 0) & P_In(Flag_C);
P_Out(Flag_C) <= BusA(7);
when "1010" =>
-- LSR
Q_t := "0" & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1011" =>
-- ROR
Q_t := P_In(Flag_C) & BusA(7 downto 1);
P_Out(Flag_C) <= BusA(0);
when "1100" =>
-- BIT
P_Out(Flag_V) <= BusB(6);
when "1110" =>
-- DEC
Q_t := std_logic_vector(unsigned(BusA) - 1);
when "1111" =>
-- INC
Q_t := std_logic_vector(unsigned(BusA) + 1);
when others =>
end case;
case Op(3 downto 0) is
when "0011" =>
P_Out(Flag_N) <= ADC_N;
P_Out(Flag_Z) <= ADC_Z;
when "0110" | "0111" =>
P_Out(Flag_N) <= SBC_N;
P_Out(Flag_Z) <= SBC_Z;
when "0100" =>
when "1100" =>
P_Out(Flag_N) <= BusB(7);
if (BusA and BusB) = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
when others =>
P_Out(Flag_N) <= Q_t(7);
if Q_t = "00000000" then
P_Out(Flag_Z) <= '1';
else
P_Out(Flag_Z) <= '0';
end if;
end case;
Q <= Q_t;
end process;
end;

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-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 Bugfixes by ehenciak added
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T65_Pack is
constant Flag_C : integer := 0;
constant Flag_Z : integer := 1;
constant Flag_I : integer := 2;
constant Flag_D : integer := 3;
constant Flag_B : integer := 4;
constant Flag_1 : integer := 5;
constant Flag_V : integer := 6;
constant Flag_N : integer := 7;
component T65_MCode
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in std_logic_vector(2 downto 0);
P : in std_logic_vector(7 downto 0);
LCycle : out std_logic_vector(2 downto 0);
ALU_Op : out std_logic_vector(3 downto 0);
Set_BusA_To : out std_logic_vector(2 downto 0); -- DI,A,X,Y,S,P
Set_Addr_To : out std_logic_vector(1 downto 0); -- PC Adder,S,AD,BA
Write_Data : out std_logic_vector(2 downto 0); -- DL,A,X,Y,S,P,PCL,PCH
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end component;
component T65_ALU
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Op : in std_logic_vector(3 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
P_In : in std_logic_vector(7 downto 0);
P_Out : out std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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--
-- Z80 compatible microprocessor core, synchronous top level
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed read with wait
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80s is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80s;
architecture rtl of T80s is
signal CEN : std_logic;
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end process;
end;

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-- changes for seperate audio outputs and enable now enables cpu access as well
--
-- A simulation model of YM2149 (AY-3-8910 with bells on)
-- Copyright (c) MikeJ - Jan 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: www.fpgaarcade.com
--
-- Email support@fpgaarcade.com
--
-- Revision list
--
-- version 001 initial release
--
-- Clues from MAME sound driver and Kazuhiro TSUJIKAWA
--
-- These are the measured outputs from a real chip for a single Isolated channel into a 1K load (V)
-- vol 15 .. 0
-- 3.27 2.995 2.741 2.588 2.452 2.372 2.301 2.258 2.220 2.198 2.178 2.166 2.155 2.148 2.141 2.132
-- As the envelope volume is 5 bit, I have fitted a curve to the not quite log shape in order
-- to produced all the required values.
-- (The first part of the curve is a bit steeper and the last bit is more linear than expected)
--
-- NOTE, this component uses LINEAR mixing of the three analogue channels, and is only
-- accurate for designs where the outputs are buffered and not simply wired together.
-- The ouput level is more complex in that case and requires a larger table.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity YM2149 is
port (
-- data bus
I_DA : in std_logic_vector(7 downto 0);
O_DA : out std_logic_vector(7 downto 0);
O_DA_OE_L : out std_logic;
-- control
I_A9_L : in std_logic;
I_A8 : in std_logic;
I_BDIR : in std_logic;
I_BC2 : in std_logic;
I_BC1 : in std_logic;
I_SEL_L : in std_logic;
O_AUDIO : out std_logic_vector(7 downto 0);
O_CHAN : out std_logic_vector(1 downto 0);
-- port a
I_IOA : in std_logic_vector(7 downto 0);
O_IOA : out std_logic_vector(7 downto 0);
O_IOA_OE_L : out std_logic;
-- port b
I_IOB : in std_logic_vector(7 downto 0);
O_IOB : out std_logic_vector(7 downto 0);
O_IOB_OE_L : out std_logic;
ENA : in std_logic; -- clock enable for higher speed operation
RESET_L : in std_logic;
CLK : in std_logic -- note 6 Mhz
);
end;
architecture RTL of YM2149 is
type array_16x8 is array (0 to 15) of std_logic_vector( 7 downto 0);
type array_3x12 is array (1 to 3) of std_logic_vector(11 downto 0);
signal cnt_div : std_logic_vector(3 downto 0) := (others => '0');
signal cnt_div_t1 : std_logic_vector(3 downto 0);
signal noise_div : std_logic := '0';
signal ena_div : std_logic;
signal ena_div_noise : std_logic;
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
-- registers
signal addr : std_logic_vector(7 downto 0);
signal busctrl_addr : std_logic;
signal busctrl_we : std_logic;
signal busctrl_re : std_logic;
signal reg : array_16x8;
signal env_reset : std_logic;
signal ioa_inreg : std_logic_vector(7 downto 0);
signal iob_inreg : std_logic_vector(7 downto 0);
signal noise_gen_cnt : std_logic_vector(4 downto 0);
signal noise_gen_op : std_logic;
signal tone_gen_cnt : array_3x12 := (others => (others => '0'));
signal tone_gen_op : std_logic_vector(3 downto 1) := "000";
signal env_gen_cnt : std_logic_vector(15 downto 0);
signal env_ena : std_logic;
signal env_hold : std_logic;
signal env_inc : std_logic;
signal env_vol : std_logic_vector(4 downto 0);
signal tone_ena_l : std_logic;
signal tone_src : std_logic;
signal noise_ena_l : std_logic;
signal chan_vol : std_logic_vector(4 downto 0);
signal dac_amp : std_logic_vector(7 downto 0);
begin
-- cpu i/f
p_busdecode : process(I_BDIR, I_BC2, I_BC1, addr, I_A9_L, I_A8)
variable cs : std_logic;
variable sel : std_logic_vector(2 downto 0);
begin
-- BDIR BC2 BC1 MODE
-- 0 0 0 inactive
-- 0 0 1 address
-- 0 1 0 inactive
-- 0 1 1 read
-- 1 0 0 address
-- 1 0 1 inactive
-- 1 1 0 write
-- 1 1 1 read
busctrl_addr <= '0';
busctrl_we <= '0';
busctrl_re <= '0';
cs := '0';
if (I_A9_L = '0') and (I_A8 = '1') and (addr(7 downto 4) = "0000") then
cs := '1';
end if;
sel := (I_BDIR & I_BC2 & I_BC1);
case sel is
when "000" => null;
when "001" => busctrl_addr <= '1';
when "010" => null;
when "011" => busctrl_re <= cs;
when "100" => busctrl_addr <= '1';
when "101" => null;
when "110" => busctrl_we <= cs;
when "111" => busctrl_addr <= '1';
when others => null;
end case;
end process;
p_oe : process(busctrl_re)
begin
-- if we are emulating a real chip, maybe clock this to fake up the tristate typ delay of 100ns
O_DA_OE_L <= not (busctrl_re);
end process;
--
-- CLOCKED
--
p_waddr : process(RESET_L, CLK)
begin
-- looks like registers are latches in real chip, but the address is caught at the end of the address state.
if (RESET_L = '0') then
addr <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
if (busctrl_addr = '1') then
addr <= I_DA;
end if;
end if;
end if;
end process;
p_wdata : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
reg <= (others => (others => '0'));
env_reset <= '1';
elsif rising_edge(CLK) then
if (ENA = '1') then
env_reset <= '0';
if (busctrl_we = '1') then
case addr(3 downto 0) is
when x"0" => reg(0) <= I_DA;
when x"1" => reg(1) <= I_DA;
when x"2" => reg(2) <= I_DA;
when x"3" => reg(3) <= I_DA;
when x"4" => reg(4) <= I_DA;
when x"5" => reg(5) <= I_DA;
when x"6" => reg(6) <= I_DA;
when x"7" => reg(7) <= I_DA;
when x"8" => reg(8) <= I_DA;
when x"9" => reg(9) <= I_DA;
when x"A" => reg(10) <= I_DA;
when x"B" => reg(11) <= I_DA;
when x"C" => reg(12) <= I_DA;
when x"D" => reg(13) <= I_DA; env_reset <= '1';
when x"E" => reg(14) <= I_DA;
when x"F" => reg(15) <= I_DA;
when others => null;
end case;
end if;
end if;
end if;
end process;
p_rdata : process(busctrl_re, addr, reg, ioa_inreg, iob_inreg)
begin
O_DA <= (others => '0'); -- 'X'
if (busctrl_re = '1') then -- not necessary, but useful for putting 'X's in the simulator
case addr(3 downto 0) is
when x"0" => O_DA <= reg(0) ;
when x"1" => O_DA <= "0000" & reg(1)(3 downto 0) ;
when x"2" => O_DA <= reg(2) ;
when x"3" => O_DA <= "0000" & reg(3)(3 downto 0) ;
when x"4" => O_DA <= reg(4) ;
when x"5" => O_DA <= "0000" & reg(5)(3 downto 0) ;
when x"6" => O_DA <= "000" & reg(6)(4 downto 0) ;
when x"7" => O_DA <= reg(7) ;
when x"8" => O_DA <= "000" & reg(8)(4 downto 0) ;
when x"9" => O_DA <= "000" & reg(9)(4 downto 0) ;
when x"A" => O_DA <= "000" & reg(10)(4 downto 0) ;
when x"B" => O_DA <= reg(11);
when x"C" => O_DA <= reg(12);
when x"D" => O_DA <= "0000" & reg(13)(3 downto 0);
when x"E" => if (reg(7)(6) = '0') then -- input
O_DA <= ioa_inreg;
else
O_DA <= reg(14); -- read output reg
end if;
when x"F" => if (Reg(7)(7) = '0') then
O_DA <= iob_inreg;
else
O_DA <= reg(15);
end if;
when others => null;
end case;
end if;
end process;
--
p_divider : process
begin
wait until rising_edge(CLK);
-- / 8 when SEL is high and /16 when SEL is low
if (ENA = '1') then
ena_div <= '0';
ena_div_noise <= '0';
if (cnt_div = "0000") then
cnt_div <= (not I_SEL_L) & "111";
ena_div <= '1';
noise_div <= not noise_div;
if (noise_div = '1') then
ena_div_noise <= '1';
end if;
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
p_noise_gen : process
variable noise_gen_comp : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
begin
wait until rising_edge(CLK);
if (reg(6)(4 downto 0) = "00000") then
noise_gen_comp := "00000";
else
noise_gen_comp := (reg(6)(4 downto 0) - "1");
end if;
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (ENA = '1') then
if (ena_div_noise = '1') then -- divider ena
if (noise_gen_cnt >= noise_gen_comp) then
noise_gen_cnt <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero) & poly17(16 downto 1);
else
noise_gen_cnt <= (noise_gen_cnt + "1");
end if;
end if;
end if;
end process;
noise_gen_op <= poly17(0);
p_tone_gens : process
variable tone_gen_freq : array_3x12;
variable tone_gen_comp : array_3x12;
begin
wait until rising_edge(CLK);
-- looks like real chips count up - we need to get the Exact behaviour ..
tone_gen_freq(1) := reg(1)(3 downto 0) & reg(0);
tone_gen_freq(2) := reg(3)(3 downto 0) & reg(2);
tone_gen_freq(3) := reg(5)(3 downto 0) & reg(4);
-- period 0 = period 1
for i in 1 to 3 loop
if (tone_gen_freq(i) = x"000") then
tone_gen_comp(i) := x"000";
else
tone_gen_comp(i) := (tone_gen_freq(i) - "1");
end if;
end loop;
if (ENA = '1') then
for i in 1 to 3 loop
if (ena_div = '1') then -- divider ena
if (tone_gen_cnt(i) >= tone_gen_comp(i)) then
tone_gen_cnt(i) <= x"000";
tone_gen_op(i) <= not tone_gen_op(i);
else
tone_gen_cnt(i) <= (tone_gen_cnt(i) + "1");
end if;
end if;
end loop;
end if;
end process;
p_envelope_freq : process
variable env_gen_freq : std_logic_vector(15 downto 0);
variable env_gen_comp : std_logic_vector(15 downto 0);
begin
wait until rising_edge(CLK);
env_gen_freq := reg(12) & reg(11);
-- envelope freqs 1 and 0 are the same.
if (env_gen_freq = x"0000") then
env_gen_comp := x"0000";
else
env_gen_comp := (env_gen_freq - "1");
end if;
if (ENA = '1') then
env_ena <= '0';
if (ena_div = '1') then -- divider ena
if (env_gen_cnt >= env_gen_comp) then
env_gen_cnt <= x"0000";
env_ena <= '1';
else
env_gen_cnt <= (env_gen_cnt + "1");
end if;
end if;
end if;
end process;
p_envelope_shape : process(env_reset, reg, CLK)
variable is_bot : boolean;
variable is_bot_p1 : boolean;
variable is_top_m1 : boolean;
variable is_top : boolean;
begin
-- envelope shapes
-- C AtAlH
-- 0 0 x x \___
--
-- 0 1 x x /___
--
-- 1 0 0 0 \\\\
--
-- 1 0 0 1 \___
--
-- 1 0 1 0 \/\/
-- ___
-- 1 0 1 1 \
--
-- 1 1 0 0 ////
-- ___
-- 1 1 0 1 /
--
-- 1 1 1 0 /\/\
--
-- 1 1 1 1 /___
if (env_reset = '1') then
-- load initial state
if (reg(13)(2) = '0') then -- attack
env_vol <= "11111";
env_inc <= '0'; -- -1
else
env_vol <= "00000";
env_inc <= '1'; -- +1
end if;
env_hold <= '0';
elsif rising_edge(CLK) then
is_bot := (env_vol = "00000");
is_bot_p1 := (env_vol = "00001");
is_top_m1 := (env_vol = "11110");
is_top := (env_vol = "11111");
if (ENA = '1') then
if (env_ena = '1') then
if (env_hold = '0') then
if (env_inc = '1') then
env_vol <= (env_vol + "00001");
else
env_vol <= (env_vol + "11111");
end if;
end if;
-- envelope shape control.
if (reg(13)(3) = '0') then
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
else
if is_top then env_hold <= '1'; end if;
end if;
else
if (reg(13)(0) = '1') then -- hold = 1
if (env_inc = '0') then -- down
if (reg(13)(1) = '1') then -- alt
if is_bot then env_hold <= '1'; end if;
else
if is_bot_p1 then env_hold <= '1'; end if;
end if;
else
if (reg(13)(1) = '1') then -- alt
if is_top then env_hold <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
end if;
end if;
elsif (reg(13)(1) = '1') then -- alternate
if (env_inc = '0') then -- down
if is_bot_p1 then env_hold <= '1'; end if;
if is_bot then env_hold <= '0'; env_inc <= '1'; end if;
else
if is_top_m1 then env_hold <= '1'; end if;
if is_top then env_hold <= '0'; env_inc <= '0'; end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
p_chan_mixer : process(cnt_div, reg, tone_gen_op)
begin
tone_ena_l <= '1'; tone_src <= '1';
noise_ena_l <= '1'; chan_vol <= "00000";
case cnt_div(1 downto 0) is
when "00" =>
tone_ena_l <= reg(7)(0); tone_src <= tone_gen_op(1); chan_vol <= reg(8)(4 downto 0);
noise_ena_l <= reg(7)(3);
when "01" =>
tone_ena_l <= reg(7)(1); tone_src <= tone_gen_op(2); chan_vol <= reg(9)(4 downto 0);
noise_ena_l <= reg(7)(4);
when "10" =>
tone_ena_l <= reg(7)(2); tone_src <= tone_gen_op(3); chan_vol <= reg(10)(4 downto 0);
noise_ena_l <= reg(7)(5);
when "11" => null; -- tone gen outputs become valid on this clock
when others => null;
end case;
end process;
p_op_mixer : process
variable chan_mixed : std_logic;
variable chan_amp : std_logic_vector(4 downto 0);
begin
wait until rising_edge(CLK);
if (ENA = '1') then
chan_mixed := (tone_ena_l or tone_src) and (noise_ena_l or noise_gen_op);
chan_amp := (others => '0');
if (chan_mixed = '1') then
if (chan_vol(4) = '0') then
if (chan_vol(3 downto 0) = "0000") then -- nothing is easy ! make sure quiet is quiet
chan_amp := "00000";
else
chan_amp := chan_vol(3 downto 0) & '1'; -- make sure level 31 (env) = level 15 (tone)
end if;
else
chan_amp := env_vol(4 downto 0);
end if;
end if;
dac_amp <= x"00";
case chan_amp is
when "11111" => dac_amp <= x"FF";
when "11110" => dac_amp <= x"D9";
when "11101" => dac_amp <= x"BA";
when "11100" => dac_amp <= x"9F";
when "11011" => dac_amp <= x"88";
when "11010" => dac_amp <= x"74";
when "11001" => dac_amp <= x"63";
when "11000" => dac_amp <= x"54";
when "10111" => dac_amp <= x"48";
when "10110" => dac_amp <= x"3D";
when "10101" => dac_amp <= x"34";
when "10100" => dac_amp <= x"2C";
when "10011" => dac_amp <= x"25";
when "10010" => dac_amp <= x"1F";
when "10001" => dac_amp <= x"1A";
when "10000" => dac_amp <= x"16";
when "01111" => dac_amp <= x"13";
when "01110" => dac_amp <= x"10";
when "01101" => dac_amp <= x"0D";
when "01100" => dac_amp <= x"0B";
when "01011" => dac_amp <= x"09";
when "01010" => dac_amp <= x"08";
when "01001" => dac_amp <= x"07";
when "01000" => dac_amp <= x"06";
when "00111" => dac_amp <= x"05";
when "00110" => dac_amp <= x"04";
when "00101" => dac_amp <= x"03";
when "00100" => dac_amp <= x"03";
when "00011" => dac_amp <= x"02";
when "00010" => dac_amp <= x"02";
when "00001" => dac_amp <= x"01";
when "00000" => dac_amp <= x"00";
when others => null;
end case;
cnt_div_t1 <= cnt_div;
end if;
end process;
p_audio_output : process(RESET_L, CLK)
begin
if (RESET_L = '0') then
O_AUDIO <= (others => '0');
O_CHAN <= (others => '0');
elsif rising_edge(CLK) then
if (ENA = '1') then
O_AUDIO <= dac_amp(7 downto 0);
O_CHAN <= cnt_div_t1(1 downto 0);
end if;
end if;
end process;
p_io_ports : process(reg)
begin
O_IOA <= reg(14);
O_IOA_OE_L <= not reg(7)(6);
O_IOB <= reg(15);
O_IOB_OE_L <= not reg(7)(7);
end process;
p_io_ports_inreg : process
begin
wait until rising_edge(CLK);
if (ENA = '1') then -- resync
ioa_inreg <= I_IOA;
iob_inreg <= I_IOB;
end if;
end process;
end architecture RTL;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
numwords_a : natural := 0; -- not used any more
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_b,
power_up_uninitialized => "FALSE",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
-- q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
---- qReg <= ram(to_integer(unsigned(addr)));
q <= ram(to_integer(unsigned(addr)));
end if;
end process;
--q <= ram(to_integer(unsigned(addr)));
end architecture;

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---------------------------------------------------------------------------------
-- burnin rubber sound by Dar (darfpga@aol.fr) (05/12/2017)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
--------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- T65(b) core.Ver 301 by MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
---------------------------------------------------------------------------------
-- YM2149 (AY-3-8910)
-- Copyright (c) MikeJ - Jan 2005
---------------------------------------------------------------------------------
-- Use burnin_rubber_de10_lite.sdc to compile (Timequest constraints)
-- /!\
-- Don't forget to set device configuration mode with memory initialization
-- (Assignments/Device/Pin options/Configuration mode)
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity jng_sound is
port
(
clock_12 : in std_logic;
reset : in std_logic;
sound_req : in std_logic;
sound_code_in : in std_logic_vector(7 downto 0);
sound_timing : in std_logic;
audio_out : out std_logic_vector(10 downto 0);
dbg_cpu_addr: out std_logic_vector(15 downto 0)
);
end jng_sound;
architecture syn of jng_sound is
-- clocks, reset
signal clock_12n : std_logic;
signal clock_div1 : std_logic_vector(8 downto 0) := (others =>'0');
signal clock_div2 : std_logic_vector(4 downto 0) := (others =>'0');
signal clock_500K : std_logic;
signal ayx_clock : std_logic;
signal reset_n : std_logic;
-- cpu signals
signal cpu_addr : std_logic_vector(23 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_di_dec : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw_n : std_logic;
signal cpu_nmi_n : std_logic;
signal cpu_irq_n : std_logic;
signal cpu_sync : std_logic;
-- program rom signals
signal prog_rom_cs : std_logic;
signal prog_rom_do : std_logic_vector(7 downto 0);
-- working ram signals
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector(7 downto 0);
-- sound req management
signal nmi_reg : std_logic;
signal nmi_reg_cs : std_logic;
signal nmi_reg_we : std_logic;
signal sound_code : std_logic_vector(7 downto 0);
signal sound_code_cs : std_logic;
-- ay-3-8910 signal
signal ay1_bc1 : std_logic;
signal ay1_bdir : std_logic;
signal ay1_audio_chan : std_logic_vector(1 downto 0);
signal ay1_audio_muxed: std_logic_vector(7 downto 0);
signal ay1_chan_a: std_logic_vector(7 downto 0);
signal ay1_chan_b: std_logic_vector(7 downto 0);
signal ay1_chan_c: std_logic_vector(7 downto 0);
signal ay2_bc1 : std_logic;
signal ay2_bdir : std_logic;
signal ay2_audio_chan : std_logic_vector(1 downto 0);
signal ay2_audio_muxed: std_logic_vector(7 downto 0);
signal ay2_chan_a: std_logic_vector(7 downto 0);
signal ay2_chan_b: std_logic_vector(7 downto 0);
signal ay2_chan_c: std_logic_vector(7 downto 0);
-- digital filtering AY2 channel A
signal uin : integer range -256 to 255;
signal u3 : integer range -32768 to 32767;
signal u4 : integer range -32768 to 32767;
signal du3 : integer range -32768*4096 to 32767*4096;
signal du4 : integer range -32768*4096 to 32767*4096;
signal uout : integer range -32768 to 32767;
signal uout_lim : integer range -128 to 127;
begin
process (clock_12, cpu_sync)
begin
if rising_edge(clock_12) then
if cpu_sync = '1' then
dbg_cpu_addr <= cpu_addr(15 downto 0);
end if;
end if;
end process;
reset_n <= not reset;
clock_12n <= not clock_12;
process (clock_12, reset)
begin
if reset='1' then
clock_div1 <= (others => '0');
clock_div2 <= (others => '0');
else
if rising_edge(clock_12) then
if clock_div1 = "111111111" then -- divide by 512 (23.437kHz)
clock_div1 <= "000000000";
else
clock_div1 <= clock_div1 + '1';
end if;
if clock_div2 = "10111" then -- divide by 24
clock_div2 <= "00000";
else
clock_div2 <= clock_div2 + '1';
end if;
end if;
end if;
end process;
clock_500K <= clock_div2(4); --12MHz/24 = 500kHz
ayx_clock <= clock_div1(2); --12MHz/8 = 1.5MHz
--static ADDRESS_MAP_START( audio_map, AS_PROGRAM, 8, btime_state )
-- AM_RANGE(0x0000, 0x03ff) AM_MIRROR(0x1c00) AM_RAM AM_SHARE("audio_rambase")
-- AM_RANGE(0x2000, 0x3fff) AM_DEVWRITE("ay1", ay8910_device, data_w)
-- AM_RANGE(0x4000, 0x5fff) AM_DEVWRITE("ay1", ay8910_device, address_w)
-- AM_RANGE(0x6000, 0x7fff) AM_DEVWRITE("ay2", ay8910_device, data_w)
-- AM_RANGE(0x8000, 0x9fff) AM_DEVWRITE("ay2", ay8910_device, address_w)
-- AM_RANGE(0xa000, 0xbfff) AM_READ(audio_command_r)
-- AM_RANGE(0xc000, 0xdfff) AM_WRITE(audio_nmi_enable_w)
-- AM_RANGE(0xe000, 0xefff) AM_MIRROR(0x1000) AM_ROM
--ADDRESS_MAP_END
-- chip select
wram_cs <= '1' when cpu_addr(15 downto 13) = "000" else '0'; -- working ram 0000-07ff .. 1fff
ay1_bc1 <= '1' when cpu_addr(15 downto 13) = "010" else '0';
ay1_bdir <= '1' when cpu_addr(15 downto 13) = "001" or ay1_bc1 = '1' else '0';
ay2_bc1 <= '1' when cpu_addr(15 downto 13) = "100" else '0';
ay2_bdir <= '1' when cpu_addr(15 downto 13) = "011" or ay2_bc1 = '1' else '0';
sound_code_cs <= '1' when cpu_addr(15 downto 13) = "101" else '0';
nmi_reg_cs <= '1' when cpu_addr(15 downto 13) = "110" else '0';
prog_rom_cs <= '1' when cpu_addr(15 downto 13) = "111" else '0';
-- write enable
wram_we <= '1' when wram_cs = '1' and cpu_rw_n = '0' else '0';
nmi_reg_we <= '1' when nmi_reg_cs = '1' and cpu_rw_n = '0' else '0';
-- cpu di mux
cpu_di <= wram_do when wram_cs = '1' else
prog_rom_do when prog_rom_cs = '1' else
sound_code when sound_code_cs = '1' else
X"FF";
-- regsiter sound code and irq management
process (clock_12)
begin
if rising_edge(clock_12) then
if sound_req = '1' then
sound_code <= sound_code_in;
cpu_irq_n <= '0';
end if;
if sound_code_cs = '1' then
cpu_irq_n <= '1';
end if;
end if;
end process;
-- nmi autorisation management
process (reset, clock_12)
begin
if reset = '1' then
nmi_reg <= '0';
else
if rising_edge(clock_12) then
if nmi_reg_we = '1' then
nmi_reg <= cpu_do(0);
end if;
end if;
end if;
end process;
-- nmi
cpu_nmi_n <= '0' when nmi_reg = '1' and sound_timing = '1' else '1';
-- demux AY chips output
process (ayx_clock)
begin
if rising_edge(ayx_clock) then
if ay1_audio_chan = "00" then ay1_chan_a <= ay1_audio_muxed; end if;
if ay1_audio_chan = "01" then ay1_chan_b <= ay1_audio_muxed; end if;
if ay1_audio_chan = "10" then ay1_chan_c <= ay1_audio_muxed; end if;
if ay2_audio_chan = "00" then ay2_chan_a <= ay2_audio_muxed; end if;
if ay2_audio_chan = "01" then ay2_chan_b <= ay2_audio_muxed; end if;
if ay2_audio_chan = "10" then ay2_chan_c <= ay2_audio_muxed; end if;
end if;
end process;
-- AOP Rauch passe bande filter
--
-- ----------o------------
-- u4^ | | |
-- | --- C4 | | R5 |
-- | --- | | |
-- | | C3 | |
-- --| R1 |----o----||---o------|\ |
-- ^ | ------> u3 | \__o---
-- | | | / ^
-- |uin | | R2 --|/ |
-- | | | | | uout
-- | | | |
-- ------------o--------------o----------
--
--
-- i1 = (sin+u3)/R1
-- i2 = -u3/R2
-- i3 = (u4-u3)/R5
-- i4 = i2-i1-i3
--
-- u3(t+dt) = u3(t) + i3(t)*dt/C3;
-- u4(t+dt) = u4(t) + i4(t)*dt/C4;
-- uout = u4-u3
-- R1 = 5000;
-- R2 = 10000;
-- C3 = 0.068e-6;
-- C4 = 0.068e-6;
-- R5 = 47000;
--
-- dt = 1/f_ech = 1/23437
-- dt/C3 = dt/C4 = 627
--
-- (i3(t)*dt/C3)*8192 = du3*8192 = ((u4-u3)/47000*627)*8192
-- = (u4-u3)*109
--
-- (i4(t)*dt/C4)*8192 = du4*8192 = (-u3/10000 -(uin+u3)/5000 -(u4-u3)/47000)*627*8192
-- = -u3(514+1027-109) - uin*1027 - u4*109
-- = -(u4*109 + u3*1432 + uin*1027)
--
-- down sample to 23.437kHz and filter AY2 channel A
uin <= to_integer(unsigned(ay2_chan_a));
process (clock_12)
begin
if rising_edge(clock_12) then
if clock_div1 = "000000000" then
du3 <= u4*109 - u3*109;
du4 <= u4*109 + u3*1432 + uin*1027*16; -- add gain(16) to uin
end if;
if clock_div1 = "000000001" then
u3 <= u3 + du3/8192;
u4 <= u4 - du4/8192;
end if;
if clock_div1 = "000000010" then
uout <= (u4 - u3) / 8; -- adjust output gain
end if;
-- limit signed dynamique before return to unsigned
if clock_div1 = "000000011" then
if uout > 127 then
uout_lim <= 127;
elsif uout < -127 then
uout_lim <= -127;
else
uout_lim <= uout;
end if;
end if;
if clock_div1 = "000000100" then
audio_out <= ("000"&ay1_chan_a(7 downto 0)) +
("000"&ay1_chan_b(7 downto 0)) +
("000"&ay1_chan_c(7 downto 0)) +
("000"&std_logic_vector(to_unsigned(uout_lim+128,8)))+
("000"&ay2_chan_b(7 downto 0)) +
("000"&ay2_chan_c(7 downto 0));
end if;
end if;
end process;
---------------------------
-- components
---------------------------
cpu_inst : entity work.T65
port map
(
Mode => "00", -- 6502
Res_n => reset_n,
Enable => '1',
Clk => clock_500K,
Rdy => '1',
Abort_n => '1',
IRQ_n => cpu_irq_n,
NMI_n => cpu_nmi_n,
SO_n => '1',--cpu_so_n,
R_W_n => cpu_rw_n,
Sync => cpu_sync, -- open
EF => open,
MF => open,
XF => open,
ML_n => open,
VP_n => open,
VDA => open,
VPA => open,
A => cpu_addr,
DI => cpu_di,
DO => cpu_do
);
-- working ram
wram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clock_12n,
we => wram_we,
addr => cpu_addr(10 downto 0),
d => cpu_do,
q => wram_do
);
-- program rom
program_rom: entity work.jng_snd_rom
port map(
clk => clock_12n,
addr => cpu_addr(11 downto 0),
data => prog_rom_do
);
-- AY-3-8910 #1
ay_3_8910_1 : entity work.YM2149
port map(
-- data bus
I_DA => cpu_do, -- in std_logic_vector(7 downto 0);
O_DA => open, -- out std_logic_vector(7 downto 0);
O_DA_OE_L => open, -- out std_logic;
-- control
I_A9_L => '0', -- in std_logic;
I_A8 => '1', -- in std_logic;
I_BDIR => ay1_bdir, -- in std_logic;
I_BC2 => '1', -- in std_logic;
I_BC1 => ay1_bc1, -- in std_logic;
I_SEL_L => '1', -- in std_logic;
O_AUDIO => ay1_audio_muxed, -- out std_logic_vector(7 downto 0);
O_CHAN => ay1_audio_chan, -- out std_logic_vector(1 downto 0);
-- port a
I_IOA => X"00", -- in std_logic_vector(7 downto 0);
O_IOA => open, -- out std_logic_vector(7 downto 0);
O_IOA_OE_L => open, -- out std_logic;
-- port b
I_IOB => X"00", -- in std_logic_vector(7 downto 0);
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
ENA => '1', -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
CLK => ayx_clock -- in std_logic -- note 6 Mhz
);
-- AY-3-8910 #2
ay_3_8910_2 : entity work.YM2149
port map(
-- data bus
I_DA => cpu_do, -- in std_logic_vector(7 downto 0);
O_DA => open, -- out std_logic_vector(7 downto 0);
O_DA_OE_L => open, -- out std_logic;
-- control
I_A9_L => '0', -- in std_logic;
I_A8 => '1', -- in std_logic;
I_BDIR => ay2_bdir, -- in std_logic;
I_BC2 => '1', -- in std_logic;
I_BC1 => ay2_bc1, -- in std_logic;
I_SEL_L => '1', -- in std_logic;
O_AUDIO => ay2_audio_muxed, -- out std_logic_vector(7 downto 0);
O_CHAN => ay2_audio_chan, -- out std_logic_vector(1 downto 0);
-- port a
I_IOA => (others => '0'), -- in std_logic_vector(7 downto 0);
O_IOA => open, -- out std_logic_vector(7 downto 0);
O_IOA_OE_L => open, -- out std_logic;
-- port b
I_IOB => (others => '0'), -- in std_logic_vector(7 downto 0);
O_IOB => open, -- out std_logic_vector(7 downto 0);
O_IOB_OE_L => open, -- out std_logic;
ENA => '1', --cpu_ena, -- in std_logic; -- clock enable for higher speed operation
RESET_L => reset_n, -- in std_logic;
CLK => ayx_clock -- in std_logic -- note 6 Mhz
);
end SYN;

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module jng_hvgen
(
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt;
assign VPOS = vcnt;
always @(posedge PCLK) begin
case (hcnt)
287: begin HBLK <= 1; HSYN <= 0; hcnt <= hcnt+1; end
311: begin HSYN <= 1; hcnt <= hcnt+1; end
383: begin
HBLK <= 0; HSYN <= 1; hcnt <= 0;
case (vcnt)
223: begin VBLK <= 1; vcnt <= vcnt+1; end
226: begin VSYN <= 0; vcnt <= vcnt+1; end
233: begin VSYN <= 1; vcnt <= vcnt+1; end
242: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+1;
endcase
end
default: hcnt <= hcnt+1;
endcase
end
endmodule

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module jng_sprite
(
input VCLKx4,
input HBLK,
input [8:0] HPOS,
input [8:0] VPOS,
output reg [10:0] SPRAADRS,
input [15:0] SPRADATA,
output [3:0] ARAMADRS,
input [7:0] ARAMDATA,
output [11:0] SPCHRADR,
input [7:0] SPCHRDAT,
output [7:0] DROMAD,
input [7:0] DROMDT,
output reg [8:0] SPCOL
);
reg [1:0] clkcnt;
always @( posedge VCLKx4 ) clkcnt<=clkcnt+1;
wire VCLKx2 = clkcnt[0];
wire VCLK = clkcnt[1];
wire SIDE = VPOS[0];
reg [19:0] SPATR0;
reg [36:0] SPATRS[0:31];
reg [3:0] WWADR;
reg bHit;
assign ARAMADRS = SPRAADRS[3:0];
reg [7:0] WRADR;
reg [8:0] HPOSW;
reg [8:0] SPWCL;
wire [36:0] SPA = SPATRS[{~SIDE,WRADR[7:4]}];
wire [3:0] SH = WRADR[3:0]+4'h4;
wire [3:0] SV = SPA[35:32];
wire [2:0] SPFY = { 3{SPA[1]} };
wire [1:0] SPFX = { 1'b0, SPA[0] };
wire [5:0] SPPL = SPA[29:24];
assign SPCHRADR = { SPA[7:2], ( SV[3] ^ SPA[1] ), ( SH[3:2] ^ SPFX ), ( SV[2:0] ^ SPFY ) };
wire [7:0] CHRO = SPCHRDAT;
wire [8:0] YM = ( SPRADATA[15:8] + 8'h10 ) + VPOS[7:0];
assign DROMAD = { 1'b0, (~SPA[19:17]), SPA[33:32], WRADR[3:2] };
always @ ( posedge VCLKx2 ) begin
// in H-BLANK
if ( HBLK ) begin
// Sprite V-hit check & list-up
if ( SPRAADRS < 10'h20 ) begin
if ( SPRAADRS[0] ) begin
if ( bHit ) begin
SPATRS[{SIDE,WWADR}] <= { 1'b1, SPATR0[3:0], SPRADATA, SPATR0[19:4] };
WWADR <= WWADR+1;
end
end
else begin
if ( YM[7:4] == 4'b1111 ) begin
bHit <= 1;
SPATR0 <= { SPRADATA, YM[3:0] };
end
else bHit <= 0;
end
SPRAADRS <= ( SPRAADRS == 10'h1F ) ? 10'h34 : (SPRAADRS+1);
end
// Rader-dot V-hit check & list-up
else begin
if ( SPRAADRS < 10'h40 ) begin
if ( YM[7:2] == 6'b111111 ) begin
SPATRS[{SIDE,WWADR}] <= { 1'b0, 2'b00, YM[1:0], 8'h0, ARAMDATA, SPRADATA };
WWADR <= WWADR+1;
end
SPRAADRS <= SPRAADRS+1;
end
else SPATRS[{SIDE,WWADR}] <= 0;
end
if ( SPA ) begin
// Rend Sprite
if ( SPA[36] ) begin
HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : { SPA[31], SPA[23:16] };
case ( SH[1:0] ^ {2{SPFX[0]}} )
2'b00: SPWCL <= { 1'b0, SPPL, CHRO[7], CHRO[3] };
2'b01: SPWCL <= { 1'b0, SPPL, CHRO[6], CHRO[2] };
2'b10: SPWCL <= { 1'b0, SPPL, CHRO[5], CHRO[1] };
2'b11: SPWCL <= { 1'b0, SPPL, CHRO[4], CHRO[0] };
endcase
WRADR <= WRADR+1;
end
// Rend Rader-dot
else begin
HPOSW <= ( WRADR[3:0] ) ? (HPOSW+1) : ({ (~SPA[16]), SPA[7:0] });
SPWCL <= ( DROMDT[1:0] != 2'b11 ) ? { 1'b1, 6'b000100, DROMDT[1:0] } : 0;
WRADR <= WRADR+4;
end
end
else SPWCL <= 0;
end
// in H-DISP
else begin
SPRAADRS <= 10'h14;
WWADR <= 0;
WRADR <= 0;
SPWCL <= 0;
end
end
reg [9:0] radr0=0,radr1=1;
wire [8:0] SPCOLi;
dpram #(
.widthad_a(10),
.width_a(9))
linebuffer(
.address_a({SIDE,HPOS}),
.address_b({~SIDE,HPOSW}),
.clock_a(VCLKx2),
.clock_b(VCLKx2),
.data_a(9'h0),
.data_b(SPWCL),
.wren_a(radr0==radr1),
.wren_b((SPWCL[0]|SPWCL[1])),
.q_a(SPCOLi),
.q_b()
);
always @(posedge VCLK) radr0 <= {SIDE,HPOS};
always @(negedge VCLK) begin
if (radr0!=radr1) SPCOL <= SPCOLi;
radr1 <= radr0;
end
endmodule

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/**************************************************************
FPGA Jungler (Main part)
***************************************************************/
module jng_top
(
input RESET, // RESET
input CLK24M, // Clock 24.576MHz
output hsync,
output vsync,
output hblank,
output vblank,
output [2:0] r,
output [2:0] g,
output [1:0] b,
output [10:0] SND, // Sound (unsigned PCM)
input [7:0] DSW1, // DipSW
input [7:0] DSW2, // DipSW
input [7:0] CTR1, // Controler (Negative logic)
input [7:0] CTR2
);
//--------------------------------------------------
// Clock Generators
//--------------------------------------------------
reg [2:0] _CCLK;
always @( posedge CLK24M ) _CCLK <= _CCLK+1;
wire CLK = CLK24M; // 24MHz
wire CCLKx4 = _CCLK[0]; // CPU CLOCKx4 : 12.0MHz
wire CCLK = _CCLK[2]; // CPU CLOCK : 3.0MHz
//--------------------------------------------------
// CPU
//--------------------------------------------------
// memory access signals
wire rd, wr, me, ie, rf, m1;
wire [15:0] ad;
wire [7:0] odt, viddata;
wire mx = rf & (~me);
wire mr = mx & (~rd);
wire mw = mx & (~wr);
// interrupt signal/vector generator & other latches
reg inte = 1'b0;
reg intl = 1'b0;
reg [7:0] intv = 8'h0;
reg out1r = 1'b0;
reg out2r = 1'b0;
reg out3r = 1'b0;
reg sonr = 1'b0;//sound On
wire vblk = (VP==224)&(HP<=8);
wire lat_Wce = ( ad[15:4] == 12'hA18 ) & mw;
wire sndw = ( lat_Wce & ( ad[3:0] == 4'h0 ) );
wire iewr = ( lat_Wce & ( ad[3:0] == 4'h1 ) );
wire mute = ( lat_Wce & ( ad[3:0] == 4'h1 ) );//mute
wire flip = ( lat_Wce & ( ad[3:0] == 4'h3 ) );//flip
wire out1w = ( lat_Wce & ( ad[3:0] == 4'h4 ) );
//wire out2w = ( lat_Wce & ( ad[3:0] == 4'h5 ) );//NOP
wire out3w = ( lat_Wce & ( ad[3:0] == 4'h6 ) );
//wire starw = ( lat_Wce & ( ad[3:0] == 4'h7 ) );//not used
wire iowr = ( (~wr) & (~ie) & m1 );
always @( posedge CCLK ) begin
if ( iowr ) intv <= odt;
if ( vblk ) intl <= 1'b1;
if ( iewr ) begin
inte <= odt[0];
intl <= 1'b0;
end
if ( sndw ) sonr <= odt[0];
if ( out1w ) out1r <= odt[0];
// if ( out2w ) out2r <= odt[0];
if ( out3w ) out3r <= odt[0];
end
wire irq_n = ~( intl & inte );
// address decoders
wire rom_Rce = ( ( ad[15] == 1'b0 ) & mr ); // $0000-$7FFF(R)
wire ram_Rce = ( ( ad[15:11] == 5'b1001_1 ) & mr ); // $9800-$9FFF(R)
wire ram_Wce = ( ( ad[15:11] == 5'b1001_1 ) & mw ); // $9800-$9FFF(W)
wire inp_Rce = ( ( ad[15:12] == 4'b1010 ) & mr ); // $A000-$AFFF(R)
wire snd_Wce = ( ( ad[15:8] == 8'b1010_0001 ) & mw ); // $A100-$A1FF(W)
wire vid_Rce;
wire [7:0] romdata;
jng_prg_rom jng_prg_rom (
.clk(CCLK),
.addr(ad[13:0]),
.data(romdata)
);
// Work RAM (2KB)
wire [7:0] ramdata;
GSPRAM #(11,8) workram(
.CL(CCLK),
.AD(ad[10:0]),
.WE(ram_Wce),
.DI(odt),
.DO(ramdata)
);
// Controler/DipSW input
wire [7:0] in0data = CTR1;
wire [7:0] in1data = CTR2;
wire [7:0] in2data = DSW1;
wire [7:0] in3data = DSW2;
wire [7:0] inpdata = (ad[8:7] == 2'b11) ? in3data : (ad[8:7] == 2'b10) ? in2data : (ad[8:7] == 2'b01) ? in1data : in0data;
// databus selector
wire [7:0] romd = rom_Rce ? romdata : 8'h00;
wire [7:0] ramd = ram_Rce ? ramdata : 8'h00;
wire [7:0] vidd = vid_Rce ? viddata : 8'h00;
wire [7:0] inpd = inp_Rce ? inpdata : 8'h00;
wire [7:0] irqv = ( (~m1) & (~ie) ) ? intv : 8'h00;
wire [7:0] idt = romd | ramd | irqv | vidd | inpd;
T80s z80(
.RESET_n(~RESET),
.CLK_n(CCLK),
.WAIT_n(1'b1),
.INT_n(1'b1),
.NMI_n(irq_n),
.BUSRQ_n(1'b1),
.DI(idt),
.M1_n(m1),
.MREQ_n(me),
.IORQ_n(ie),
.RD_n(rd),
.WR_n(wr),
.RFSH_n(rf),
.HALT_n(),
.BUSAK_n(),
.A(ad),
.DO(odt)
);
//--------------------------------------------------
// VIDEO
//--------------------------------------------------
wire [8:0] HP;
wire [8:0] VP;
wire PCLK;
jng_video video(
.VCLKx4(CLK),
.HPOS(HP+3),
.VPOS(VP+1),
.PCLK(PCLK),
.POUT({b,g,r}),
.CPUCLK(CCLK),
.CPUADDR(ad),
.CPUDI(odt),
.CPUDO(viddata),
.CPUME(mx),
.CPUWE(mw),
.CPUDT(vid_Rce)
);
jng_hvgen hvgen(
.HPOS(HP),
.VPOS(VP),
.PCLK(PCLK),
.HBLK(hblank),
.VBLK(vblank),
.HSYN(hsync),
.VSYN(vsync)
);
//--------------------------------------------------
// SOUND
//--------------------------------------------------
jng_sound jng_sound(
.clock_12(CCLKx4),
.reset(RESET),
.sound_req(sonr),
.sound_code_in(odt),
.sound_timing(snd_Wce),
.audio_out(SND)
);
endmodule

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module jng_video
(
input VCLKx4, // 24.976MHz
input [8:0] HPOS,
input [8:0] VPOS,
output PCLK,
output reg [7:0] POUT,
input CPUCLK,
input [15:0] CPUADDR,
input [7:0] CPUDI,
output [7:0] CPUDO,
input CPUME,
input CPUWE,
output CPUDT
);
//-----------------------------------------
// Clock generators
//-----------------------------------------
reg VCLKx2;
always @( posedge VCLKx4 ) begin
VCLKx2 <= ~VCLKx2;
end
reg VCLK;
always @( posedge VCLKx2 ) begin
VCLK <= ~VCLK;
end
//-----------------------------------------
// BG scroll registers
//-----------------------------------------
reg [7:0] BGHSCR;
reg [7:0] BGVSCR;
always @ ( posedge CPUCLK ) begin
if ( ( CPUADDR == 16'hA130 ) & CPUME & CPUWE ) begin
BGHSCR <= CPUDI-3;
end
if ( ( CPUADDR == 16'hA140 ) & CPUME & CPUWE ) begin
BGVSCR <= CPUDI;
end
end
//-----------------------------------------
// HV
//-----------------------------------------
wire [8:0] BGHPOS = HPOS + { 1'b0, BGHSCR };
wire [8:0] BGVPOS = VPOS + { 1'b0, BGVSCR };
wire oHB = ( HPOS > 288 ) ? 1 : 0;
wire oVB = ( VPOS > 224 ) ? 1 : 0;
//----------------------------------------
// VideoRAM Scanner
//----------------------------------------
wire BF = ( HPOS >= 224 );
wire [8:0] HP = BF ? HPOS : BGHPOS;
wire [8:0] VP = ( BF ? VPOS : BGVPOS ) + 9'h0F;
wire [10:0] SPRAADRS;
wire [3:0] ARAMADRS;
reg [10:0] VRAMADRS;
always @ ( HPOS ) begin
VRAMADRS <= oHB ?
SPRAADRS :
BF ? { 1'b0, VP[7:3], 2'b00, HP[5:3] } : { 1'b1, VP[7:3], HP[7:3] };
end
wire [7:0] CHRC;
wire [7:0] ATTR;
wire [7:0] ARDT;
wire [7:0] V0DO, V1DO;
wire CEV0 = ( ( CPUADDR[15:12] == 4'b1000 ) & (~CPUADDR[11]) ) & CPUME;
wire CEV1 = ( ( CPUADDR[15:12] == 4'b1000 ) & CPUADDR[11] ) & CPUME;
wire CEAT = ( CPUADDR[15:4] == 12'b1010_0000_0000 ) & CPUME;
wire [7:0] DTV0 = CEV0 ? V0DO : 8'h00;
wire [7:0] DTV1 = CEV1 ? V1DO : 8'h00;
assign CPUDO = DTV0 | DTV1;
assign CPUDT = ( ~CPUWE ) & ( CEV0 | CEV1 );
GDPRAM #(11,8) vram0( VCLKx4, VRAMADRS, CHRC, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV0 ), CPUDI, V0DO );
/*dpram #(
.widthad_a(11),
.width_a(8))
vram0(
.address_a(VRAMADRS),
.address_b(CPUADDR[10:0]),
.clock_a(VCLKx4),
.clock_b(CPUCLK),
.data_a(),
.data_b(CPUDI),
.wren_a(),
.wren_b(( CPUWE & CEV0 )),
.q_a(CHRC),
.q_b(V0DO)
);*/
GDPRAM #(11,8) vram1( VCLKx4, VRAMADRS, ATTR, CPUCLK, CPUADDR[10:0], ( CPUWE & CEV1 ), CPUDI, V1DO );
/*dpram #(
.widthad_a(11),
.width_a(8))
vram1(
.address_a(VRAMADRS),
.address_b(CPUADDR[10:0]),
.clock_a(VCLKx4),
.clock_b(CPUCLK),
.data_a(),
.data_b(CPUDI),
.wren_a(),
.wren_b(( CPUWE & CEV1 )),
.q_a(ATTR),
.q_b(V1DO)
); */
GDPRAM #(4,8) aram0( VCLKx4, ARAMADRS, ARDT, CPUCLK, CPUADDR[3:0], ( CPUWE & CEAT ), CPUDI );
/*dpram #(
.widthad_a(8),
.width_a(4))
aram0(
.address_a(ARAMADRS),
.address_b(CPUADDR[3:0]),
.clock_a(VCLKx4),
.clock_b(CPUCLK),
.data_a(),
.data_b(CPUDI),
.wren_a(),
.wren_b(( CPUWE & CEAT )),
.q_a(ARDT),
.q_b()
); */
wire BGF = ATTR[5];
//----------------------------------------
// BG/Sprite chip data reader
//----------------------------------------
wire BGFX = ATTR[6];
wire [2:0] BGFY = { ATTR[7], ATTR[7], ATTR[7] };
wire [11:0] SPCHRADR;
wire [11:0] CHRA = oHB ? SPCHRADR : { CHRC, ( HP[2] ^ BGFX ), ( VP[2:0] ^ BGFY ) };
wire [7:0] CHRO;
jng_chr_rom chrrom(
.clk(VCLKx4),
.addr(CHRA),
.data(CHRO)
);
//----------------------------------------
// Rader-dot chip ROM
//----------------------------------------
wire [7:0] DROMAD;
wire [7:0] DROMDT;
jng_dot_rom dotrom(
.clk(VCLKx4),
.addr(DROMAD),
.data(DROMDT)
);
//----------------------------------------
// BG/FG scanline generator
//----------------------------------------
wire [5:0] BGPL = ATTR[5:0];
reg [7:0] BGCOL;
always @ ( posedge VCLK ) begin
case ( HP[1:0]^{2{BGFX}} )
2'b00: BGCOL <= { BGPL, CHRO[4], CHRO[0] };
2'b01: BGCOL <= { BGPL, CHRO[5], CHRO[1] };
2'b10: BGCOL <= { BGPL, CHRO[6], CHRO[2] };
2'b11: BGCOL <= { BGPL, CHRO[7], CHRO[3] };
endcase
end
//----------------------------------------
// Sprite Engine
//----------------------------------------
wire [8:0] SPCOL;
jng_sprite speng(
.VCLKx4(VCLKx4),
.HBLK(oHB),
.HPOS(HPOS),
.VPOS(VPOS),
.SPRAADRS(SPRAADRS),
.SPRADATA({ ATTR, CHRC }),
.ARAMADRS(ARAMADRS),
.ARAMDATA(ARDT),
.SPCHRADR(SPCHRADR),
.SPCHRDAT(CHRO),
.DROMAD(DROMAD),
.DROMDT(DROMDT),
.SPCOL(SPCOL)
);
//----------------------------------------
// Color mixer
//----------------------------------------
wire bBGOPAQUE = ( ( BF | BGF ) & (~SPCOL[8]) );
wire bSPTRANSP = ( SPCOL[1:0] == 2'b00 );
wire [7:0] OUTCOL = ( bBGOPAQUE | bSPTRANSP ) ? BGCOL : SPCOL[7:0];
wire [3:0] CLUT;
jng_col_rom colrom(
.clk(~VCLKx4),
.addr(OUTCOL),
.data(CLUT)
);
wire [4:0] PALA = SPCOL[8] ? SPCOL[4:0] : { 1'b0, CLUT };
wire [7:0] PALO;
jng_pal_rom palrom(
.clk(VCLKx4),
.addr(PALA),
.data(PALO)
);
//----------------------------------------
// Color output
//----------------------------------------
always @ ( posedge PCLK ) POUT <= (oHB|oVB) ? 8'h0 : PALO;
assign PCLK = VCLK;
endmodule

175
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/jungler_mist.sv Normal file
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module jungler_mist (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Jungler;;",
"O2,Rotate,Off,On;",
"O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
"O5,Test,Off,On;",
"O6,Service,Off,On;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clock_24, clock_12;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_24)//24.576MHz
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] audio;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [7:0] iDSW1 = ~{ m_down1,"0000000"};
wire [7:0] iDSW2 = ~{ status[5], 1'b1, "000", "000"};//Test,Cab,CoinB,CoinA
wire [7:0] iCTR1 = ~{ btn_coin, 1'b0, m_right1, m_left1, m_fire1, status[6], 1'b0, m_up2};
wire [7:0] iCTR2 = ~{ btn_one_player, btn_two_players, m_left2, m_right2, m_fire2, 1'b0, m_down2, m_up1};
jng_top jng_top(
.RESET(status[0] | status[6] | buttons[1]),
.CLK24M(clock_24),
.hsync(hs),
.vsync(vs),
.hblank(hb),
.vblank(vb),
.r(r),
.g(g),
.b(b),
.SND(audio),
.DSW1(iDSW1),
.DSW2(iDSW2),
.CTR1(iCTR1),
.CTR2(iCTR2),
.LAMP()
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clock_24 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? {b,1'b0} : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ({1'b1,status[2]} ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_24 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(.C_bits(16))dac(
.clk_i(clock_24),
.res_n_i(1),
.dac_i({audio,audio[4:0]}),
.dac_o(AUDIO_L)
);
wire m_up1 = btn_up | joystick_0[3];
wire m_down1 = btn_down | joystick_0[2];
wire m_left1 = btn_left | joystick_0[1];
wire m_right1 = btn_right | joystick_0[0];
wire m_fire1 = btn_fire1 | joystick_0[4];
wire m_up2 = btn_up | joystick_1[3];
wire m_down2 = btn_down | joystick_1[2];
wire m_left2 = btn_left | joystick_1[1];
wire m_right2 = btn_right | joystick_1[0];
wire m_fire2 = btn_fire1 | joystick_1[4];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
//reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clock_24) begin
reg old_state;
old_state <= key_strobe;
if(old_state != key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
// 'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

4
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

309
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/pll.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
locked);
input inclk0;
output c0;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire5 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire locked = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 78,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 71,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "78"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.576923"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.57600000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "78"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

64
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/rams.v Normal file
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@@ -0,0 +1,64 @@
module GSPRAM #(parameter AW,parameter DW)
(
input CL,
input [(AW-1):0] AD,
input WE,
input [(DW-1):0] DI,
output reg [(DW-1):0] DO
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL) begin
DO <= core[AD];
if (WE) core[AD] <= DI;
end
endmodule
module GDPRAM #(parameter AW,parameter DW)
(
input CL0,
input [(AW-1):0] AD0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input WE1,
input [(DW-1):0] DI1,
output reg [(DW-1):0] DO1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) DO0 <= core[AD0];
always @(posedge CL1) begin DO1 <= core[AD1]; if (WE1) core[AD1] <= DI1; end
endmodule
/*
module GLINEBUF #(parameter AW,parameter DW)
(
input CL0,
input [(AW-1):0] AD0,
input WE0,
output reg [(DW-1):0] DO0,
input CL1,
input [(AW-1):0] AD1,
input WE1,
input [(DW-1):0] DI1
);
reg [(DW-1):0] core[0:((2**AW)-1)];
always @(posedge CL0) begin DO0 <= core[AD0]; if (WE0) core[AD0] <= 0; end
always @(posedge CL1) if (WE1) core[AD1] <= DI1;
endmodule*/

278
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_chr_rom.vhd Normal file
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@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity jng_chr_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of jng_chr_rom is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"80",X"C0",X"20",X"20",X"60",X"C0",X"80",X"00",X"30",X"70",X"C0",X"80",X"80",X"70",X"30",X"00",
X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"00",X"00",X"F0",X"F0",X"40",X"00",X"00",X"00",
X"20",X"20",X"A0",X"A0",X"E0",X"E0",X"60",X"00",X"60",X"F0",X"B0",X"90",X"90",X"C0",X"40",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"80",X"D0",X"F0",X"B0",X"90",X"80",X"00",X"00",
X"80",X"E0",X"E0",X"80",X"80",X"80",X"80",X"00",X"00",X"F0",X"F0",X"C0",X"60",X"30",X"10",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"10",X"B0",X"A0",X"A0",X"A0",X"E0",X"E0",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"00",X"90",X"90",X"90",X"D0",X"70",X"30",X"00",
X"00",X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"C0",X"E0",X"B0",X"90",X"80",X"C0",X"C0",X"00",
X"C0",X"E0",X"A0",X"A0",X"20",X"20",X"C0",X"00",X"00",X"60",X"90",X"90",X"B0",X"F0",X"60",X"00",
X"80",X"C0",X"60",X"20",X"20",X"20",X"00",X"00",X"70",X"F0",X"90",X"90",X"90",X"F0",X"60",X"00",
X"40",X"40",X"20",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"80",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"10",X"20",X"20",
X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"40",X"40",X"40",
X"80",X"80",X"00",X"00",X"00",X"00",X"00",X"00",X"20",X"20",X"10",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"20",X"40",X"40",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"40",
X"00",X"00",X"00",X"00",X"90",X"F0",X"52",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"F0",X"A4",X"68",
X"30",X"20",X"28",X"28",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"40",X"41",X"41",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"0C",X"00",X"F0",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"30",X"E0",X"A4",X"78",
X"10",X"F0",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"78",X"A4",X"E0",X"30",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"28",X"28",X"20",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"41",X"41",X"40",X"E0",
X"61",X"52",X"F0",X"90",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"A4",X"F0",X"90",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"C0",X"70",X"52",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"F0",X"80",
X"E1",X"52",X"70",X"C0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"F0",X"00",X"03",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"81",X"F0",X"D2",X"61",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"18",X"F0",X"B4",X"68",
X"30",X"10",X"18",X"18",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"80",X"81",X"81",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"0C",X"00",X"10",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"70",X"E0",X"A4",X"69",
X"F0",X"10",X"00",X"0C",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"69",X"A4",X"E0",X"70",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"18",X"18",X"10",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"81",X"81",X"80",X"C0",
X"61",X"D2",X"F0",X"81",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"68",X"B4",X"F0",X"18",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"E0",X"70",X"52",X"69",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"03",X"00",X"80",X"F0",
X"69",X"52",X"70",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"80",X"00",X"03",X"00",X"00",X"00",X"00",
X"00",X"77",X"44",X"44",X"77",X"00",X"77",X"44",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"22",X"22",X"EE",X"00",X"EE",X"22",
X"44",X"77",X"00",X"55",X"55",X"55",X"77",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"22",X"EE",X"00",X"EE",X"22",X"22",X"22",X"00",
X"00",X"E0",X"C0",X"C2",X"C2",X"C0",X"E0",X"00",X"00",X"04",X"10",X"61",X"61",X"10",X"04",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",X"F0",
X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"E0",X"E0",X"80",X"80",X"80",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"C0",X"70",X"30",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"E0",X"E0",X"00",X"60",X"F0",X"90",X"90",X"90",X"F0",X"F0",X"00",
X"40",X"60",X"20",X"20",X"60",X"C0",X"80",X"00",X"40",X"C0",X"80",X"80",X"C0",X"70",X"30",X"00",
X"80",X"C0",X"60",X"20",X"20",X"E0",X"E0",X"00",X"30",X"70",X"C0",X"80",X"80",X"F0",X"F0",X"00",
X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"80",X"90",X"90",X"90",X"F0",X"F0",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"E0",X"E0",X"00",X"80",X"90",X"90",X"90",X"90",X"F0",X"F0",X"00",
X"E0",X"E0",X"20",X"20",X"60",X"C0",X"80",X"00",X"90",X"90",X"90",X"80",X"C0",X"70",X"30",X"00",
X"E0",X"E0",X"00",X"00",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"10",X"10",X"F0",X"F0",X"00",
X"20",X"20",X"E0",X"E0",X"20",X"20",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"F0",X"F0",X"00",X"00",X"00",X"00",X"00",X"00",
X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"80",X"C0",X"60",X"30",X"10",X"F0",X"F0",X"00",
X"20",X"20",X"20",X"20",X"E0",X"E0",X"00",X"00",X"00",X"00",X"00",X"00",X"F0",X"F0",X"00",X"00",
X"E0",X"E0",X"00",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"70",X"30",X"70",X"F0",X"F0",X"00",
X"E0",X"E0",X"C0",X"80",X"00",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"70",X"F0",X"F0",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00",
X"00",X"80",X"80",X"80",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"F0",X"00",
X"A0",X"C0",X"E0",X"A0",X"20",X"E0",X"C0",X"00",X"70",X"F0",X"80",X"80",X"80",X"F0",X"70",X"00",
X"20",X"60",X"E0",X"C0",X"80",X"E0",X"E0",X"00",X"70",X"F0",X"90",X"80",X"80",X"F0",X"F0",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"60",X"40",X"00",X"00",X"50",X"D0",X"90",X"90",X"F0",X"60",X"00",
X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"80",X"80",X"F0",X"F0",X"80",X"80",X"00",X"00",
X"C0",X"E0",X"20",X"20",X"20",X"E0",X"C0",X"00",X"F0",X"F0",X"00",X"00",X"00",X"F0",X"F0",X"00",
X"00",X"80",X"C0",X"E0",X"C0",X"80",X"00",X"00",X"F0",X"F0",X"10",X"00",X"10",X"F0",X"F0",X"00",
X"E0",X"E0",X"C0",X"80",X"C0",X"E0",X"E0",X"00",X"F0",X"F0",X"10",X"30",X"10",X"F0",X"F0",X"00",
X"60",X"E0",X"C0",X"80",X"C0",X"E0",X"60",X"00",X"C0",X"E0",X"70",X"30",X"70",X"E0",X"C0",X"00",
X"00",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"E0",X"F0",X"10",X"10",X"F0",X"E0",X"00",X"00",
X"20",X"20",X"20",X"A0",X"E0",X"E0",X"60",X"00",X"C0",X"E0",X"F0",X"B0",X"90",X"80",X"80",X"00",
X"00",X"00",X"00",X"60",X"60",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"C0",X"20",X"10",X"50",X"50",X"90",X"20",X"C0",X"30",X"40",X"80",X"A0",X"A0",X"90",X"40",X"30",
X"C0",X"E8",X"E4",X"E0",X"E0",X"E0",X"C0",X"00",X"30",X"79",X"78",X"FC",X"78",X"78",X"30",X"00",
X"E0",X"C0",X"68",X"E0",X"68",X"C0",X"E0",X"00",X"00",X"10",X"F0",X"21",X"F0",X"10",X"00",X"00",
X"C0",X"20",X"80",X"C0",X"80",X"20",X"C0",X"00",X"10",X"30",X"70",X"F0",X"70",X"30",X"10",X"00",
X"00",X"00",X"00",X"00",X"10",X"00",X"3F",X"56",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"11",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"08",X"08",X"4F",X"A6",
X"25",X"2A",X"8B",X"26",X"15",X"00",X"00",X"00",X"11",X"11",X"01",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"A2",X"4C",X"84",X"82",X"88",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"3B",X"AC",X"8A",X"98",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",
X"00",X"00",X"00",X"04",X"08",X"88",X"88",X"00",X"00",X"00",X"00",X"04",X"15",X"8B",X"14",X"18",
X"51",X"46",X"0D",X"A9",X"66",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"00",X"00",
X"04",X"08",X"00",X"00",X"00",X"00",X"00",X"00",X"8B",X"E2",X"26",X"C6",X"09",X"08",X"00",X"00",
X"00",X"00",X"11",X"2A",X"49",X"21",X"95",X"45",X"00",X"02",X"01",X"00",X"00",X"11",X"23",X"22",
X"00",X"00",X"00",X"00",X"02",X"0C",X"88",X"88",X"00",X"02",X"8A",X"45",X"C6",X"11",X"AD",X"C4",
X"5C",X"26",X"90",X"04",X"8A",X"01",X"01",X"00",X"11",X"01",X"02",X"13",X"04",X"00",X"00",X"00",
X"00",X"06",X"08",X"00",X"00",X"08",X"08",X"00",X"A8",X"0A",X"91",X"66",X"81",X"00",X"00",X"00",
X"00",X"18",X"AC",X"84",X"13",X"38",X"91",X"23",X"01",X"00",X"11",X"2E",X"47",X"54",X"40",X"06",
X"09",X"0A",X"02",X"05",X"08",X"00",X"0C",X"03",X"04",X"04",X"05",X"CE",X"3E",X"31",X"39",X"89",
X"2F",X"59",X"42",X"A8",X"6F",X"10",X"01",X"01",X"3A",X"32",X"11",X"05",X"08",X"01",X"01",X"01",
X"88",X"C4",X"4C",X"8E",X"01",X"00",X"00",X"00",X"BA",X"32",X"4D",X"06",X"B3",X"4A",X"01",X"01",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"02",X"04",X"00",X"64",X"00",X"40",X"02",X"00",X"18",X"40",X"01",X"D5",X"01",X"04",X"18",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"18",X"F0",X"B4",X"68",X"C0",X"80",X"81",X"81",X"81",X"F0",X"D2",X"61",X"30",X"10",X"18",X"18",
X"90",X"F0",X"A4",X"68",X"C0",X"40",X"41",X"41",X"90",X"F0",X"52",X"61",X"30",X"20",X"28",X"28",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"21",X"43",X"53",X"E1",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"88",X"0C",X"0E",X"4F",
X"D3",X"61",X"43",X"21",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"0F",X"2E",X"8C",X"08",X"00",X"00",X"00",X"00",
X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00",
X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"03",
X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"03",X"07",
X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07",
X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0E",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"07",
X"80",X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"30",X"00",X"00",X"01",X"03",X"07",X"07",X"07",
X"00",X"00",X"0C",X"0E",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"07",X"03",
X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00",
X"00",X"00",X"80",X"81",X"81",X"01",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00",
X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00",
X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",
X"00",X"03",X"07",X"0F",X"0F",X"07",X"03",X"00",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",
X"00",X"0E",X"0F",X"0F",X"0F",X"0F",X"07",X"00",X"00",X"00",X"01",X"81",X"81",X"80",X"00",X"00",
X"00",X"0C",X"0E",X"0F",X"0F",X"0F",X"0E",X"00",X"00",X"01",X"03",X"03",X"03",X"01",X"00",X"00",
X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00",
X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00",
X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00",
X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00",
X"C0",X"83",X"07",X"0F",X"0F",X"07",X"03",X"00",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00",
X"80",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"00",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00",
X"00",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"00",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",
X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",
X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00",
X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",
X"0E",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"07",X"07",X"03",X"01",X"00",X"00",X"00",X"00",
X"0C",X"0E",X"0E",X"1C",X"18",X"00",X"00",X"00",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"00",
X"08",X"0C",X"0E",X"0E",X"0C",X"08",X"00",X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",
X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00",
X"C0",X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"70",X"70",X"70",X"30",X"10",X"00",X"00",X"01",
X"E0",X"E0",X"E0",X"C0",X"00",X"00",X"08",X"0C",X"70",X"70",X"30",X"10",X"00",X"00",X"01",X"03",
X"E0",X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"70",X"30",X"10",X"00",X"00",X"01",X"03",X"07",
X"C0",X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"30",X"10",X"00",X"00",X"01",X"03",X"07",X"0F",
X"80",X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"30",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",
X"00",X"00",X"08",X"0C",X"0E",X"0F",X"0D",X"09",X"00",X"00",X"01",X"03",X"07",X"0F",X"0B",X"09",
X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",X"00",X"30",X"70",X"F0",X"F0",X"70",X"30",X"00",
X"00",X"00",X"80",X"81",X"81",X"00",X"00",X"00",X"00",X"70",X"F0",X"F0",X"F0",X"F0",X"E0",X"00",
X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",X"00",X"E0",X"F0",X"F0",X"F0",X"E0",X"C0",X"00",
X"00",X"01",X"03",X"07",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",
X"01",X"03",X"07",X"0F",X"0F",X"07",X"03",X"01",X"00",X"00",X"80",X"C0",X"C0",X"80",X"00",X"00",
X"03",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"00",X"00",X"00",X"81",X"81",X"80",X"00",X"00",
X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",
X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
X"80",X"C0",X"E0",X"E0",X"C0",X"80",X"00",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",X"00",
X"C0",X"E0",X"E0",X"C1",X"81",X"00",X"00",X"00",X"30",X"70",X"70",X"30",X"10",X"00",X"00",X"00",
X"E0",X"E0",X"C1",X"83",X"03",X"01",X"00",X"00",X"70",X"70",X"30",X"10",X"00",X"00",X"00",X"00",
X"E0",X"C1",X"83",X"07",X"07",X"03",X"01",X"00",X"70",X"30",X"10",X"00",X"00",X"00",X"00",X"00",
X"C1",X"83",X"07",X"0F",X"0F",X"07",X"03",X"01",X"30",X"10",X"00",X"00",X"00",X"00",X"00",X"00",
X"83",X"06",X"0F",X"0F",X"0F",X"0F",X"06",X"03",X"10",X"00",X"00",X"01",X"01",X"00",X"00",X"00",
X"07",X"0C",X"0E",X"0F",X"0F",X"0E",X"0C",X"07",X"00",X"00",X"01",X"03",X"03",X"01",X"00",X"00",
X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",X"00",
X"00",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"00",X"00",X"00",X"10",X"30",X"30",X"10",X"00",X"00",
X"08",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"00",X"01",X"00",X"00",X"10",X"10",X"00",X"00",X"00",
X"0C",X"38",X"70",X"F0",X"F0",X"70",X"30",X"00",X"03",X"01",X"00",X"00",X"00",X"00",X"00",X"00",
X"0E",X"1C",X"38",X"70",X"70",X"30",X"10",X"00",X"07",X"03",X"01",X"00",X"00",X"00",X"00",X"00",
X"0F",X"0E",X"1C",X"38",X"30",X"10",X"00",X"00",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",X"00",
X"0D",X"0F",X"0E",X"1C",X"18",X"00",X"00",X"00",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",X"00",
X"09",X"0D",X"0F",X"0E",X"0C",X"08",X"00",X"00",X"09",X"0B",X"0F",X"07",X"03",X"01",X"00",X"00",
X"00",X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",
X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",
X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",
X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",
X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00",
X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",X"00",X"10",X"30",X"70",X"70",X"30",X"10",X"00",
X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",X"10",X"30",X"70",X"F0",X"F0",X"70",X"30",X"10",
X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",X"30",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"30",
X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",X"70",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"70",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"E0",X"90",X"C0",X"E0",X"E0",X"C0",X"90",X"E0",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"C0",X"20",X"80",X"C0",X"C0",X"80",X"20",X"C0",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"40",X"00",X"80",X"80",X"00",X"40",X"80",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"80",X"00",X"00",X"00",X"00",X"80",X"00",
X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
X"80",X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"10",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",
X"C0",X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"30",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",
X"E0",X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"70",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",
X"F0",X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"F0",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",
X"D0",X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"B0",X"90",X"40",X"00",X"00",X"00",X"00",X"00",
X"90",X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"90",X"40",X"00",X"00",X"00",X"00",X"00",X"00",
X"20",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"40",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",
X"80",X"C0",X"E0",X"F0",X"F0",X"E0",X"C0",X"80",X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",
X"C0",X"60",X"F0",X"F0",X"F0",X"F0",X"60",X"C0",X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",
X"E0",X"30",X"70",X"F0",X"F0",X"70",X"30",X"E0",X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",
X"70",X"90",X"30",X"70",X"70",X"30",X"90",X"70",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"30",X"40",X"10",X"30",X"30",X"10",X"40",X"30",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"10",X"20",X"00",X"10",X"10",X"00",X"20",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"10",X"00",X"00",X"00",X"00",X"10",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"50",X"A0",X"50",X"A0",X"50",X"A0",X"F0",X"00",X"50",X"60",X"50",X"60",X"50",X"20",X"10",X"00",
X"00",X"F0",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"00",X"10",X"20",X"50",X"60",X"50",X"60",X"50",
X"A0",X"60",X"A0",X"60",X"A0",X"40",X"80",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",
X"00",X"80",X"40",X"A0",X"60",X"A0",X"60",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"F0",X"00",
X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"00",X"F0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"60",X"50",X"60",X"50",X"60",X"50",X"60",X"50",
X"60",X"A0",X"60",X"A0",X"60",X"A0",X"60",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",
X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
X"40",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",
X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",X"A0",X"50",
X"C0",X"20",X"50",X"90",X"90",X"50",X"20",X"C0",X"30",X"40",X"A0",X"90",X"90",X"A0",X"40",X"30",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"20",X"40",X"20",X"90",X"20",X"40",X"20",X"90",X"50",X"A0",X"50",X"20",X"50",X"A0",X"50",X"20",
X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",X"20",X"50",X"A0",X"50",X"80",X"20",X"50",X"80",
X"20",X"50",X"A0",X"50",X"00",X"20",X"10",X"A0",X"20",X"90",X"40",X"20",X"50",X"A0",X"50",X"20",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_col_rom.vhd Normal file
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@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity jng_col_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of jng_col_rom is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"0F",X"00",X"00",X"01",X"0F",X"00",X"00",X"02",X"0F",X"00",X"00",X"04",X"0F",
X"00",X"00",X"0C",X"0F",X"00",X"00",X"0E",X"0F",X"00",X"00",X"0F",X"0F",X"00",X"01",X"00",X"0F",
X"00",X"01",X"01",X"0F",X"00",X"01",X"02",X"0F",X"00",X"01",X"04",X"0F",X"00",X"01",X"0C",X"0F",
X"00",X"01",X"0E",X"0F",X"00",X"01",X"0F",X"0F",X"00",X"02",X"00",X"0F",X"00",X"02",X"01",X"0F",
X"00",X"02",X"02",X"0F",X"00",X"02",X"04",X"0F",X"00",X"02",X"0C",X"0F",X"00",X"02",X"0E",X"0F",
X"00",X"02",X"0F",X"0F",X"00",X"04",X"00",X"0F",X"00",X"04",X"01",X"0F",X"00",X"04",X"02",X"0F",
X"00",X"04",X"04",X"0F",X"00",X"04",X"0C",X"0F",X"00",X"04",X"0E",X"0F",X"00",X"04",X"0F",X"0F",
X"00",X"0C",X"00",X"0F",X"00",X"0C",X"01",X"0F",X"00",X"0C",X"02",X"0F",X"00",X"0C",X"04",X"0F",
X"00",X"0C",X"0C",X"0F",X"00",X"0C",X"0E",X"0F",X"00",X"0C",X"0F",X"0F",X"00",X"0E",X"00",X"0F",
X"00",X"0E",X"01",X"0F",X"00",X"0E",X"02",X"0F",X"00",X"0E",X"04",X"0F",X"00",X"0E",X"0C",X"0F",
X"00",X"0E",X"0E",X"0F",X"00",X"0E",X"0F",X"0F",X"00",X"0F",X"00",X"0F",X"00",X"0F",X"01",X"0F",
X"00",X"0F",X"02",X"0F",X"00",X"0F",X"04",X"0F",X"00",X"0F",X"0C",X"0F",X"00",X"0F",X"0E",X"0F",
X"00",X"0F",X"0F",X"0F",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"02",X"09",X"00",X"0F",X"09",X"02",X"00",X"02",X"01",X"04",
X"00",X"0C",X"0F",X"0A",X"00",X"07",X"05",X"08",X"00",X"0D",X"04",X"06",X"00",X"02",X"04",X"0B");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_dot_rom.vhd Normal file
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@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity jng_dot_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of jng_dot_rom is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00",
X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00",
X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00",
X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",X"01",X"01",X"00",
X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"00",X"00",X"02",X"02",X"00",X"00",X"00",X"00",X"00",
X"00",X"02",X"02",X"00",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"02",X"00",X"02",X"02",X"00",
X"00",X"02",X"02",X"00",X"02",X"01",X"01",X"02",X"02",X"01",X"01",X"02",X"00",X"02",X"02",X"00",
X"00",X"00",X"00",X"00",X"00",X"02",X"00",X"00",X"02",X"02",X"02",X"00",X"00",X"02",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",
X"00",X"01",X"01",X"00",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"01",X"00",X"01",X"01",X"00",
X"00",X"01",X"01",X"00",X"01",X"02",X"02",X"01",X"01",X"02",X"02",X"01",X"00",X"01",X"01",X"00",
X"00",X"00",X"00",X"00",X"00",X"01",X"00",X"00",X"01",X"01",X"01",X"00",X"00",X"01",X"00",X"00");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

24
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_pal_rom.vhd Normal file
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@@ -0,0 +1,24 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity jng_pal_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of jng_pal_rom is
type rom is array(0 to 31) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"07",X"38",X"3C",X"3F",X"8C",X"E0",X"27",X"AA",X"8C",X"1F",X"B6",X"C0",X"C7",X"F8",X"FE",
X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67",X"00",X"3F",X"FE",X"67");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

1046
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_prg_rom.vhd Normal file
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File diff suppressed because it is too large Load Diff

278
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jng_snd_rom.vhd Normal file
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@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity jng_snd_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of jng_snd_rom is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"21",X"00",X"20",X"06",X"00",X"C3",X"B2",X"01",X"32",X"00",X"50",X"3A",X"00",X"40",X"C9",X"FF",
X"32",X"00",X"70",X"3A",X"00",X"60",X"C9",X"FF",X"78",X"CF",X"79",X"32",X"00",X"40",X"C9",X"FF",
X"78",X"D7",X"79",X"32",X"00",X"60",X"C9",X"FF",X"87",X"85",X"6F",X"7C",X"CE",X"00",X"67",X"7E",
X"23",X"66",X"6F",X"E9",X"FF",X"FF",X"FF",X"FF",X"D9",X"08",X"CD",X"40",X"00",X"08",X"D9",X"C9",
X"3E",X"0E",X"CF",X"B7",X"28",X"09",X"F2",X"79",X"00",X"CB",X"BF",X"CD",X"6C",X"00",X"C9",X"21",
X"00",X"20",X"06",X"0C",X"AF",X"77",X"23",X"10",X"FC",X"C9",X"21",X"00",X"20",X"06",X"06",X"0E",
X"07",X"BE",X"28",X"05",X"23",X"23",X"10",X"F9",X"41",X"79",X"90",X"C9",X"CD",X"5A",X"00",X"C8",
X"AF",X"77",X"23",X"77",X"C9",X"13",X"23",X"22",X"28",X"32",X"1A",X"20",X"CD",X"5A",X"00",X"28",
X"04",X"23",X"36",X"00",X"C9",X"3A",X"1A",X"20",X"21",X"75",X"00",X"06",X"02",X"BE",X"28",X"19",
X"23",X"10",X"FA",X"06",X"02",X"BE",X"28",X"21",X"23",X"10",X"FA",X"AF",X"CD",X"5A",X"00",X"28",
X"3A",X"3A",X"1A",X"20",X"77",X"23",X"36",X"00",X"C9",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE",
X"04",X"FA",X"C9",X"00",X"CD",X"37",X"01",X"18",X"58",X"AF",X"CD",X"5A",X"00",X"28",X"05",X"FE",
X"04",X"F2",X"C9",X"00",X"CD",X"62",X"01",X"18",X"40",X"21",X"1A",X"20",X"46",X"0E",X"00",X"21",
X"00",X"20",X"3D",X"87",X"5F",X"51",X"19",X"70",X"23",X"71",X"C9",X"CD",X"37",X"01",X"CD",X"62",
X"01",X"B7",X"28",X"2D",X"3A",X"17",X"20",X"B7",X"28",X"1F",X"3A",X"18",X"20",X"21",X"06",X"20",
X"CD",X"26",X"01",X"CD",X"2E",X"01",X"57",X"3A",X"17",X"20",X"21",X"00",X"20",X"CD",X"26",X"01",
X"CD",X"2E",X"01",X"BA",X"F2",X"09",X"01",X"18",X"08",X"3A",X"18",X"20",X"21",X"06",X"20",X"18",
X"06",X"3A",X"17",X"20",X"21",X"00",X"20",X"B7",X"C8",X"3D",X"87",X"4F",X"06",X"00",X"09",X"3A",
X"1A",X"20",X"77",X"23",X"70",X"C9",X"3D",X"87",X"4F",X"06",X"00",X"09",X"7E",X"C9",X"21",X"87",
X"07",X"06",X"00",X"4F",X"09",X"7E",X"C9",X"3A",X"00",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20",
X"3A",X"02",X"20",X"CD",X"2E",X"01",X"32",X"13",X"20",X"3A",X"04",X"20",X"CD",X"2E",X"01",X"32",
X"14",X"20",X"3A",X"1A",X"20",X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"17",
X"20",X"C9",X"3A",X"06",X"20",X"CD",X"2E",X"01",X"32",X"12",X"20",X"3A",X"08",X"20",X"CD",X"2E",
X"01",X"32",X"13",X"20",X"3A",X"0A",X"20",X"CD",X"2E",X"01",X"32",X"14",X"20",X"3A",X"1A",X"20",
X"CD",X"2E",X"01",X"32",X"15",X"20",X"CD",X"8D",X"01",X"32",X"18",X"20",X"C9",X"21",X"12",X"20",
X"3A",X"15",X"20",X"06",X"03",X"4F",X"7E",X"B9",X"F2",X"9C",X"01",X"4F",X"23",X"10",X"F7",X"79",
X"06",X"03",X"0E",X"01",X"21",X"12",X"20",X"BE",X"28",X"06",X"0C",X"23",X"10",X"F9",X"0E",X"00",
X"79",X"C9",X"70",X"23",X"7C",X"FE",X"24",X"20",X"F9",X"F9",X"ED",X"56",X"21",X"00",X"30",X"22",
X"0C",X"20",X"77",X"01",X"3F",X"07",X"DF",X"E7",X"32",X"0E",X"20",X"32",X"0F",X"20",X"CD",X"C8",
X"02",X"CD",X"CC",X"02",X"CD",X"D0",X"02",X"CD",X"D6",X"02",X"CD",X"DA",X"02",X"CD",X"DE",X"02",
X"FB",X"3E",X"0F",X"CF",X"E6",X"80",X"20",X"F9",X"3E",X"0F",X"CF",X"E6",X"80",X"28",X"F9",X"F3",
X"3E",X"01",X"32",X"10",X"20",X"3A",X"01",X"20",X"B7",X"3A",X"00",X"20",X"CA",X"04",X"02",X"CD",
X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"02",X"32",X"10",X"20",
X"3A",X"03",X"20",X"B7",X"3A",X"02",X"20",X"CA",X"1F",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD",
X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"03",X"32",X"10",X"20",X"3A",X"05",X"20",X"B7",X"3A",
X"04",X"20",X"CA",X"3A",X"02",X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",
X"F3",X"3E",X"04",X"32",X"10",X"20",X"3A",X"07",X"20",X"B7",X"3A",X"06",X"20",X"CA",X"55",X"02",
X"CD",X"AC",X"02",X"18",X"03",X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"05",X"32",X"10",
X"20",X"3A",X"09",X"20",X"B7",X"3A",X"08",X"20",X"CA",X"70",X"02",X"CD",X"AC",X"02",X"18",X"03",
X"CD",X"92",X"02",X"FB",X"00",X"00",X"F3",X"3E",X"06",X"32",X"10",X"20",X"3A",X"0B",X"20",X"B7",
X"3A",X"0A",X"20",X"CA",X"8C",X"02",X"CD",X"AC",X"02",X"C3",X"E0",X"01",X"CD",X"92",X"02",X"C3",
X"E0",X"01",X"21",X"A1",X"07",X"EF",X"B7",X"20",X"1B",X"E5",X"21",X"01",X"20",X"3A",X"10",X"20",
X"3D",X"87",X"D5",X"5F",X"16",X"00",X"19",X"D1",X"36",X"01",X"E1",X"C9",X"B7",X"C8",X"21",X"D5",
X"07",X"EF",X"B7",X"C8",X"57",X"21",X"00",X"20",X"3A",X"10",X"20",X"3D",X"4F",X"06",X"00",X"09",
X"09",X"15",X"28",X"01",X"70",X"23",X"70",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",
X"06",X"0A",X"0E",X"00",X"DF",X"C9",X"06",X"08",X"18",X"06",X"06",X"09",X"18",X"02",X"06",X"0A",
X"0E",X"00",X"E7",X"C9",X"3A",X"10",X"20",X"3D",X"21",X"ED",X"02",X"EF",X"C9",X"F9",X"02",X"02",
X"03",X"0B",X"03",X"14",X"03",X"1D",X"03",X"26",X"03",X"CD",X"C8",X"02",X"0E",X"09",X"CD",X"2F",
X"03",X"C9",X"CD",X"CC",X"02",X"0E",X"12",X"CD",X"2F",X"03",X"C9",X"CD",X"D0",X"02",X"0E",X"24",
X"CD",X"2F",X"03",X"C9",X"CD",X"D6",X"02",X"0E",X"09",X"CD",X"3B",X"03",X"C9",X"CD",X"DA",X"02",
X"0E",X"12",X"CD",X"3B",X"03",X"C9",X"CD",X"DE",X"02",X"0E",X"24",X"CD",X"3B",X"03",X"C9",X"3A",
X"0E",X"20",X"B1",X"32",X"0E",X"20",X"06",X"07",X"4F",X"DF",X"C9",X"3A",X"0F",X"20",X"B1",X"32",
X"0F",X"20",X"06",X"07",X"4F",X"E7",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"53",
X"03",X"E7",X"C9",X"DF",X"C9",X"06",X"06",X"3A",X"10",X"20",X"FE",X"04",X"FA",X"63",X"03",X"78",
X"D7",X"4F",X"C9",X"78",X"CF",X"4F",X"C9",X"3A",X"0E",X"20",X"A0",X"B1",X"32",X"0E",X"20",X"4F",
X"06",X"07",X"DF",X"C9",X"3A",X"0F",X"20",X"A0",X"B1",X"32",X"0F",X"20",X"4F",X"06",X"07",X"E7",
X"C9",X"3A",X"10",X"20",X"3D",X"21",X"8A",X"03",X"EF",X"C9",X"96",X"03",X"9D",X"03",X"A4",X"03",
X"AB",X"03",X"B2",X"03",X"B9",X"03",X"01",X"08",X"FE",X"CD",X"67",X"03",X"C9",X"01",X"10",X"FD",
X"CD",X"67",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"67",X"03",X"C9",X"01",X"08",X"FE",X"CD",X"74",
X"03",X"C9",X"01",X"10",X"FD",X"CD",X"74",X"03",X"C9",X"01",X"20",X"FB",X"CD",X"74",X"03",X"C9",
X"3A",X"10",X"20",X"3D",X"21",X"C9",X"03",X"EF",X"C9",X"D5",X"03",X"DC",X"03",X"E3",X"03",X"EA",
X"03",X"F1",X"03",X"F8",X"03",X"01",X"01",X"F7",X"CD",X"67",X"03",X"C9",X"01",X"02",X"EF",X"CD",
X"67",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"67",X"03",X"C9",X"01",X"01",X"F7",X"CD",X"74",X"03",
X"C9",X"01",X"02",X"EF",X"CD",X"74",X"03",X"C9",X"01",X"04",X"DF",X"CD",X"74",X"03",X"C9",X"3A",
X"10",X"20",X"3D",X"21",X"08",X"04",X"EF",X"C9",X"14",X"04",X"1B",X"04",X"22",X"04",X"29",X"04",
X"30",X"04",X"37",X"04",X"01",X"00",X"F6",X"CD",X"67",X"03",X"C9",X"01",X"00",X"ED",X"CD",X"67",
X"03",X"C9",X"01",X"00",X"DB",X"CD",X"67",X"03",X"C9",X"01",X"00",X"F6",X"CD",X"74",X"03",X"C9",
X"01",X"00",X"ED",X"CD",X"74",X"03",X"C9",X"01",X"00",X"DB",X"CD",X"74",X"03",X"C9",X"3A",X"10",
X"20",X"FE",X"04",X"30",X"05",X"C6",X"07",X"47",X"DF",X"C9",X"C6",X"04",X"47",X"E7",X"C9",X"3A",
X"10",X"20",X"FE",X"04",X"30",X"04",X"C6",X"07",X"CF",X"C9",X"C6",X"04",X"D7",X"C9",X"3A",X"10",
X"20",X"FE",X"04",X"30",X"09",X"3D",X"87",X"47",X"4D",X"DF",X"4C",X"04",X"DF",X"C9",X"D6",X"04",
X"87",X"47",X"4D",X"E7",X"4C",X"04",X"E7",X"C9",X"3A",X"10",X"20",X"FE",X"04",X"30",X"0A",X"3D",
X"87",X"67",X"24",X"CF",X"6F",X"7C",X"CF",X"67",X"C9",X"D6",X"04",X"87",X"67",X"24",X"D7",X"6F",
X"7C",X"D7",X"67",X"C9",X"FE",X"04",X"D0",X"F5",X"CD",X"E4",X"04",X"F1",X"B7",X"20",X"02",X"77",
X"C9",X"21",X"B4",X"04",X"87",X"87",X"4F",X"87",X"81",X"4F",X"06",X"00",X"09",X"3A",X"10",X"20",
X"3D",X"EF",X"77",X"C9",X"07",X"05",X"0C",X"05",X"11",X"05",X"16",X"05",X"1B",X"05",X"20",X"05",
X"25",X"05",X"2A",X"05",X"2F",X"05",X"34",X"05",X"39",X"05",X"3E",X"05",X"43",X"05",X"48",X"05",
X"4D",X"05",X"52",X"05",X"57",X"05",X"5C",X"05",X"61",X"05",X"66",X"05",X"6B",X"05",X"70",X"05",
X"75",X"05",X"7A",X"05",X"21",X"B4",X"04",X"3A",X"10",X"20",X"3D",X"EF",X"C9",X"2A",X"0C",X"20",
X"7B",X"A5",X"6F",X"7A",X"A4",X"67",X"22",X"0C",X"20",X"C9",X"2A",X"0C",X"20",X"7B",X"B5",X"6F",
X"7A",X"B4",X"67",X"22",X"0C",X"20",X"C9",X"11",X"3F",X"FF",X"18",X"E1",X"11",X"FF",X"FC",X"18",
X"DC",X"11",X"FF",X"F3",X"18",X"D7",X"11",X"FC",X"FF",X"18",X"D2",X"11",X"F3",X"FF",X"18",X"CD",
X"11",X"CF",X"FF",X"18",X"C8",X"11",X"80",X"00",X"18",X"D0",X"11",X"00",X"02",X"18",X"CB",X"11",
X"00",X"08",X"18",X"C6",X"11",X"02",X"00",X"18",X"C1",X"11",X"08",X"00",X"18",X"BC",X"11",X"20",
X"00",X"18",X"B7",X"11",X"40",X"00",X"18",X"B2",X"11",X"00",X"01",X"18",X"AD",X"11",X"00",X"04",
X"18",X"A8",X"11",X"01",X"00",X"18",X"A3",X"11",X"04",X"00",X"18",X"9E",X"11",X"10",X"00",X"18",
X"99",X"11",X"C0",X"00",X"18",X"94",X"11",X"00",X"03",X"18",X"8F",X"11",X"00",X"0C",X"18",X"8A",
X"11",X"03",X"00",X"18",X"85",X"11",X"0C",X"00",X"18",X"80",X"11",X"30",X"00",X"C3",X"FA",X"04",
X"DD",X"7E",X"00",X"FE",X"FF",X"C8",X"CD",X"8B",X"05",X"AF",X"C9",X"DD",X"35",X"01",X"C0",X"3A",
X"42",X"20",X"DD",X"77",X"01",X"DD",X"CB",X"00",X"46",X"C2",X"AB",X"05",X"DD",X"7E",X"07",X"D6",
X"01",X"FA",X"AB",X"05",X"DD",X"77",X"07",X"4F",X"CD",X"3E",X"04",X"DD",X"35",X"00",X"C0",X"DD",
X"6E",X"02",X"DD",X"66",X"03",X"7E",X"47",X"E6",X"1F",X"CA",X"46",X"06",X"FE",X"1F",X"C2",X"62",
X"06",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"78",X"E6",X"E0",X"0F",X"0F",X"0F",X"0F",X"4F",
X"06",X"00",X"21",X"DB",X"05",X"09",X"5E",X"23",X"56",X"EB",X"E9",X"EB",X"05",X"09",X"06",X"1F",
X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"3C",X"06",X"DD",X"6E",X"02",X"DD",X"66",
X"03",X"4E",X"CB",X"21",X"06",X"00",X"21",X"95",X"06",X"09",X"5E",X"23",X"56",X"ED",X"53",X"40",
X"20",X"DD",X"73",X"04",X"DD",X"72",X"05",X"18",X"23",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"4E",
X"06",X"00",X"21",X"2D",X"07",X"09",X"7E",X"32",X"42",X"20",X"DD",X"77",X"01",X"18",X"0D",X"DD",
X"6E",X"02",X"DD",X"66",X"03",X"7E",X"DD",X"77",X"06",X"DD",X"77",X"07",X"DD",X"6E",X"02",X"DD",
X"66",X"03",X"23",X"DD",X"75",X"02",X"DD",X"74",X"03",X"C3",X"AF",X"05",X"0E",X"00",X"CD",X"3E",
X"04",X"DD",X"36",X"00",X"FF",X"C9",X"CD",X"50",X"06",X"0E",X"00",X"CD",X"3E",X"04",X"18",X"37",
X"78",X"E6",X"E0",X"07",X"07",X"07",X"47",X"3E",X"01",X"18",X"01",X"07",X"10",X"FD",X"DD",X"77",
X"00",X"C9",X"C5",X"CD",X"50",X"06",X"C1",X"78",X"E6",X"1F",X"3D",X"07",X"4F",X"06",X"00",X"DD",
X"6E",X"04",X"DD",X"66",X"05",X"09",X"5E",X"23",X"56",X"EB",X"CD",X"5E",X"04",X"DD",X"4E",X"06",
X"79",X"DD",X"77",X"07",X"CD",X"3E",X"04",X"DD",X"6E",X"02",X"DD",X"66",X"03",X"23",X"DD",X"75",
X"02",X"DD",X"74",X"03",X"C9",X"B5",X"06",X"B9",X"06",X"BD",X"06",X"C1",X"06",X"C5",X"06",X"C9",
X"06",X"CD",X"06",X"D1",X"06",X"D5",X"06",X"D9",X"06",X"DD",X"06",X"E1",X"06",X"E5",X"06",X"E9",
X"06",X"ED",X"06",X"F1",X"06",X"6B",X"08",X"F2",X"07",X"80",X"07",X"14",X"07",X"AE",X"06",X"4E",
X"06",X"F3",X"05",X"9E",X"05",X"4E",X"05",X"01",X"05",X"B9",X"04",X"76",X"04",X"36",X"04",X"F9",
X"03",X"C0",X"03",X"8A",X"03",X"57",X"03",X"27",X"03",X"FA",X"02",X"CF",X"02",X"A7",X"02",X"81",
X"02",X"5D",X"02",X"3B",X"02",X"1B",X"02",X"FD",X"01",X"E0",X"01",X"C5",X"01",X"AC",X"01",X"94",
X"01",X"7D",X"01",X"68",X"01",X"53",X"01",X"40",X"01",X"2E",X"01",X"1D",X"01",X"0D",X"01",X"FE",
X"00",X"F0",X"00",X"E3",X"00",X"D6",X"00",X"CA",X"00",X"BE",X"00",X"B4",X"00",X"AA",X"00",X"A0",
X"00",X"97",X"00",X"8F",X"00",X"87",X"00",X"7F",X"00",X"78",X"00",X"71",X"00",X"6B",X"00",X"65",
X"00",X"5F",X"00",X"5A",X"00",X"55",X"00",X"50",X"00",X"4C",X"00",X"47",X"00",X"57",X"42",X"34",
X"2C",X"25",X"21",X"1D",X"1A",X"0C",X"0B",X"0A",X"09",X"08",X"07",X"06",X"05",X"21",X"6F",X"07",
X"11",X"20",X"20",X"01",X"18",X"00",X"ED",X"B0",X"3A",X"43",X"20",X"07",X"4F",X"07",X"81",X"4F",
X"06",X"00",X"21",X"01",X"0D",X"09",X"11",X"22",X"20",X"CD",X"65",X"07",X"11",X"2A",X"20",X"CD",
X"65",X"07",X"11",X"32",X"20",X"7E",X"12",X"CD",X"6C",X"07",X"7E",X"12",X"23",X"13",X"C9",X"01",
X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"01",
X"01",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"10",X"0E",X"07",X"06",X"01",X"04",X"03",X"05",
X"0C",X"02",X"0A",X"09",X"08",X"0D",X"0F",X"11",X"12",X"13",X"14",X"15",X"16",X"17",X"18",X"19",
X"0B",X"E4",X"02",X"09",X"08",X"43",X"08",X"71",X"08",X"D3",X"08",X"1A",X"09",X"AB",X"09",X"F5",
X"09",X"57",X"0A",X"BC",X"0A",X"FD",X"0A",X"60",X"0B",X"B0",X"0B",X"F7",X"0B",X"2E",X"0C",X"74",
X"0C",X"13",X"0D",X"17",X"0D",X"19",X"0D",X"21",X"0D",X"25",X"0D",X"27",X"0D",X"2F",X"0D",X"33",
X"0D",X"35",X"0D",X"C5",X"0C",X"00",X"00",X"24",X"08",X"64",X"08",X"92",X"08",X"EB",X"08",X"40",
X"09",X"C3",X"09",X"12",X"0A",X"77",X"0A",X"D5",X"0A",X"1F",X"0B",X"7A",X"0B",X"CA",X"0B",X"11",
X"0C",X"4B",X"0C",X"8F",X"0C",X"1B",X"0D",X"1D",X"0D",X"1F",X"0D",X"29",X"0D",X"2B",X"0D",X"2D",
X"0D",X"37",X"0D",X"39",X"0D",X"3B",X"0D",X"E2",X"0C",X"3E",X"03",X"CD",X"94",X"04",X"CD",X"81",
X"03",X"21",X"00",X"01",X"CD",X"5E",X"04",X"0E",X"0C",X"CD",X"3E",X"04",X"AF",X"32",X"51",X"20",
X"32",X"50",X"20",X"C9",X"3A",X"50",X"20",X"3D",X"32",X"50",X"20",X"E6",X"03",X"20",X"12",X"CD",
X"78",X"04",X"3A",X"51",X"20",X"C6",X"DB",X"32",X"51",X"20",X"AD",X"E6",X"7F",X"6F",X"CD",X"5E",
X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"10",X"CD",X"3E",X"04",
X"21",X"40",X"0D",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"3D",X"FE",X"04",X"28",X"11",X"4F",X"CD",
X"3E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"2D",X"28",X"E6",X"CD",X"5E",X"04",X"AF",X"C9",X"3D",
X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"FF",X"03",X"01",X"1F",X"06",X"CD",X"49",X"03",X"21",
X"00",X"04",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"32",X"53",X"20",X"32",X"52",
X"20",X"C9",X"21",X"52",X"20",X"35",X"56",X"CD",X"78",X"04",X"3A",X"53",X"20",X"C6",X"B5",X"32",
X"53",X"20",X"AD",X"6F",X"7A",X"E6",X"0F",X"20",X"05",X"25",X"20",X"02",X"26",X"01",X"CD",X"5E",
X"04",X"7A",X"E6",X"3F",X"20",X"19",X"7C",X"FE",X"01",X"20",X"14",X"06",X"06",X"CD",X"57",X"03",
X"0D",X"0D",X"CD",X"49",X"03",X"CD",X"4F",X"04",X"3D",X"28",X"06",X"4F",X"CD",X"3E",X"04",X"AF",
X"C9",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E",
X"04",X"3E",X"20",X"32",X"55",X"20",X"AF",X"32",X"54",X"20",X"C9",X"3A",X"55",X"20",X"3D",X"32",
X"55",X"20",X"20",X"02",X"3D",X"C9",X"CB",X"47",X"28",X"07",X"0E",X"0C",X"CD",X"3E",X"04",X"AF",
X"C9",X"CD",X"78",X"04",X"3A",X"54",X"20",X"3C",X"32",X"54",X"20",X"85",X"6F",X"30",X"01",X"24",
X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81",
X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"00",X"CD",X"3E",X"04",X"3E",X"08",X"32",X"59",
X"20",X"32",X"58",X"20",X"3E",X"DB",X"32",X"56",X"20",X"3E",X"AA",X"32",X"57",X"20",X"AF",X"C9",
X"3A",X"56",X"20",X"3D",X"32",X"56",X"20",X"20",X"02",X"3D",X"C9",X"FE",X"C3",X"38",X"24",X"28",
X"15",X"FE",X"CF",X"38",X"0A",X"CD",X"4F",X"04",X"3C",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",
X"00",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0C",X"CD",X"3E",X"04",X"21",X"1F",X"00",X"CD",X"5E",
X"04",X"AF",X"C9",X"3A",X"58",X"20",X"3D",X"32",X"58",X"20",X"28",X"02",X"AF",X"C9",X"3A",X"59",
X"20",X"32",X"58",X"20",X"21",X"57",X"20",X"CB",X"0E",X"38",X"0C",X"CD",X"78",X"04",X"3E",X"20",
X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"E0",X"85",X"6F",X"CD",X"5E",
X"04",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"00",X"CD",X"94",X"04",
X"CD",X"81",X"03",X"21",X"30",X"00",X"CD",X"5E",X"04",X"0E",X"08",X"CD",X"3E",X"04",X"AF",X"32",
X"5A",X"20",X"C9",X"21",X"5A",X"20",X"35",X"7E",X"28",X"29",X"57",X"FE",X"E8",X"28",X"0C",X"38",
X"11",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",
X"AF",X"C9",X"CD",X"78",X"04",X"01",X"02",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"0F",X"28",
X"E0",X"AF",X"C9",X"3D",X"C9",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0C",X"CD",X"3E",
X"04",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"5B",X"20",X"3E",X"AA",X"32",X"5C",X"20",
X"AF",X"C9",X"21",X"5C",X"20",X"CB",X"0E",X"30",X"02",X"AF",X"C9",X"3A",X"5B",X"20",X"3D",X"32",
X"5B",X"20",X"FE",X"EC",X"38",X"18",X"FE",X"F6",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85",
X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"21",X"90",X"00",X"CD",X"5E",X"04",X"AF",X"C9",X"CD",X"78",
X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"CD",X"4F",X"04",X"D6",X"02",X"20",X"02",X"3D",
X"C9",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",
X"00",X"05",X"CD",X"5E",X"04",X"0E",X"0E",X"CD",X"3E",X"04",X"3E",X"02",X"32",X"5E",X"20",X"AF",
X"32",X"5F",X"20",X"32",X"5D",X"20",X"C9",X"3A",X"5E",X"20",X"3D",X"32",X"5E",X"20",X"20",X"28",
X"3E",X"02",X"32",X"5E",X"20",X"21",X"5D",X"20",X"35",X"28",X"1F",X"7E",X"57",X"CD",X"78",X"04",
X"7A",X"FE",X"E0",X"38",X"18",X"E6",X"07",X"20",X"01",X"25",X"3A",X"5F",X"20",X"C6",X"C3",X"32",
X"5F",X"20",X"AA",X"AD",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"FF",X"C9",X"E6",X"0F",X"20",
X"E9",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"C3",X"9A",X"0A",X"AF",X"CD",X"94",X"04",
X"CD",X"81",X"03",X"21",X"C0",X"01",X"CD",X"5E",X"04",X"0E",X"0F",X"CD",X"3E",X"04",X"3E",X"48",
X"32",X"60",X"20",X"AF",X"C9",X"3A",X"60",X"20",X"3D",X"32",X"60",X"20",X"20",X"02",X"3D",X"C9",
X"FE",X"02",X"38",X"12",X"E6",X"07",X"28",X"02",X"AF",X"C9",X"CD",X"78",X"04",X"01",X"D4",X"FF",
X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",
X"94",X"04",X"CD",X"81",X"03",X"21",X"40",X"00",X"CD",X"5E",X"04",X"0E",X"03",X"CD",X"3E",X"04",
X"3E",X"20",X"32",X"61",X"20",X"32",X"62",X"20",X"3E",X"08",X"32",X"63",X"20",X"AF",X"C9",X"3A",
X"62",X"20",X"3D",X"32",X"62",X"20",X"28",X"25",X"FE",X"1A",X"28",X"0C",X"38",X"11",X"CD",X"4F",
X"04",X"C6",X"02",X"CD",X"3E",X"04",X"AF",X"C9",X"0E",X"0F",X"CD",X"3E",X"04",X"AF",X"C9",X"E6",
X"01",X"28",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",X"04",X"AF",X"C9",X"3A",X"63",X"20",
X"3D",X"32",X"63",X"20",X"20",X"02",X"3D",X"C9",X"3A",X"61",X"20",X"32",X"62",X"20",X"AF",X"C9",
X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD",X"3E",X"04",X"21",X"FF",X"00",
X"CD",X"5E",X"04",X"3E",X"40",X"32",X"64",X"20",X"AF",X"C9",X"3A",X"64",X"20",X"3D",X"32",X"64",
X"20",X"20",X"02",X"3D",X"C9",X"E6",X"07",X"20",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",
X"04",X"3A",X"64",X"20",X"E6",X"08",X"28",X"0C",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"6F",X"CD",
X"5E",X"04",X"AF",X"C9",X"CD",X"78",X"04",X"3E",X"10",X"85",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",
X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"7C",X"00",X"CD",X"5E",X"04",X"0E",X"0F",
X"CD",X"3E",X"04",X"3E",X"3F",X"32",X"65",X"20",X"AF",X"C9",X"21",X"65",X"20",X"35",X"7E",X"28",
X"24",X"FE",X"11",X"38",X"15",X"FE",X"30",X"38",X"08",X"CD",X"4F",X"04",X"3D",X"4F",X"CD",X"3E",
X"04",X"CD",X"78",X"04",X"2D",X"CD",X"5E",X"04",X"AF",X"C9",X"E6",X"02",X"0E",X"07",X"28",X"EE",
X"0E",X"0F",X"C3",X"DE",X"0B",X"3D",X"C9",X"3E",X"00",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",
X"0D",X"CD",X"3E",X"04",X"21",X"FF",X"00",X"CD",X"5E",X"04",X"3E",X"0F",X"32",X"66",X"20",X"AF",
X"C9",X"3A",X"66",X"20",X"3D",X"32",X"66",X"20",X"28",X"02",X"AF",X"C9",X"3E",X"0F",X"32",X"66",
X"20",X"CD",X"78",X"04",X"3E",X"F0",X"85",X"D0",X"6F",X"CD",X"5E",X"04",X"AF",X"C9",X"3E",X"00",
X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"90",X"00",X"CD",X"5E",X"04",X"0E",X"09",X"CD",X"3E",
X"04",X"3E",X"F4",X"32",X"68",X"20",X"AF",X"32",X"67",X"20",X"C9",X"21",X"67",X"20",X"35",X"7E",
X"E6",X"07",X"20",X"11",X"CD",X"78",X"04",X"3A",X"68",X"20",X"3C",X"28",X"15",X"32",X"68",X"20",
X"85",X"6F",X"CD",X"5E",X"04",X"7E",X"E6",X"08",X"0E",X"09",X"20",X"01",X"4F",X"CD",X"3E",X"04",
X"AF",X"C9",X"3D",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"21",X"D0",X"00",X"CD",
X"5E",X"04",X"3E",X"08",X"32",X"69",X"20",X"32",X"6A",X"20",X"AF",X"32",X"6B",X"20",X"C9",X"3A",
X"6A",X"20",X"3D",X"57",X"32",X"6A",X"20",X"20",X"1E",X"3A",X"69",X"20",X"32",X"6A",X"20",X"CD",
X"78",X"04",X"3A",X"6B",X"20",X"3C",X"32",X"6B",X"20",X"FE",X"4E",X"20",X"03",X"3E",X"FF",X"C9",
X"4F",X"06",X"00",X"09",X"CD",X"5E",X"04",X"7A",X"E6",X"02",X"0E",X"03",X"28",X"02",X"0E",X"0C",
X"CD",X"3E",X"04",X"AF",X"C9",X"3E",X"01",X"CD",X"94",X"04",X"CD",X"81",X"03",X"0E",X"0E",X"CD",
X"3E",X"04",X"3E",X"05",X"32",X"6D",X"20",X"21",X"04",X"00",X"CD",X"5E",X"04",X"AF",X"32",X"6C",
X"20",X"C9",X"21",X"6C",X"20",X"35",X"7E",X"28",X"16",X"FE",X"DA",X"20",X"06",X"21",X"6D",X"20",
X"35",X"20",X"E4",X"CD",X"78",X"04",X"01",X"0C",X"00",X"09",X"CD",X"5E",X"04",X"AF",X"C9",X"3D",
X"C9",X"6A",X"0D",X"91",X"0D",X"B6",X"0D",X"D7",X"0D",X"17",X"0E",X"37",X"0E",X"49",X"0E",X"5E",
X"0E",X"71",X"0E",X"3E",X"00",X"18",X"26",X"18",X"33",X"18",X"31",X"18",X"38",X"18",X"3D",X"18",
X"42",X"3E",X"01",X"18",X"18",X"18",X"25",X"18",X"23",X"18",X"2A",X"18",X"2F",X"18",X"34",X"3E",
X"02",X"18",X"0A",X"18",X"17",X"18",X"15",X"18",X"1C",X"18",X"21",X"18",X"26",X"32",X"43",X"20",
X"CD",X"3D",X"07",X"AF",X"CD",X"94",X"04",X"CD",X"81",X"03",X"AF",X"C9",X"AF",X"CD",X"94",X"04",
X"CD",X"81",X"03",X"AF",X"C9",X"DD",X"21",X"20",X"20",X"C3",X"80",X"05",X"DD",X"21",X"28",X"20",
X"C3",X"80",X"05",X"DD",X"21",X"30",X"20",X"C3",X"80",X"05",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",
X"6D",X"6F",X"72",X"6D",X"6F",X"72",X"6D",X"6F",X"6F",X"71",X"74",X"6F",X"71",X"74",X"6F",X"74",
X"72",X"72",X"72",X"74",X"74",X"74",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"36",X"B6",X"A0",
X"FF",X"1F",X"0E",X"5F",X"09",X"6A",X"6B",X"6F",X"6A",X"6B",X"6F",X"6A",X"6B",X"6C",X"6D",X"71",
X"6C",X"6D",X"71",X"6C",X"6D",X"6F",X"6F",X"6F",X"70",X"70",X"70",X"32",X"32",X"32",X"32",X"32",
X"32",X"32",X"32",X"B2",X"A0",X"FF",X"1F",X"05",X"5F",X"09",X"8C",X"60",X"8C",X"60",X"6C",X"6C",
X"8E",X"60",X"8E",X"60",X"6E",X"6E",X"69",X"69",X"69",X"6A",X"6A",X"6A",X"2C",X"2C",X"2C",X"2C",
X"2C",X"2C",X"2C",X"2C",X"AC",X"A0",X"FF",X"1F",X"0E",X"3F",X"0C",X"5F",X"09",X"70",X"70",X"60",
X"70",X"90",X"71",X"71",X"60",X"71",X"91",X"93",X"91",X"70",X"71",X"70",X"71",X"90",X"71",X"73",
X"71",X"73",X"91",X"93",X"91",X"2E",X"2F",X"30",X"31",X"2F",X"30",X"31",X"32",X"30",X"31",X"32",
X"33",X"31",X"32",X"33",X"34",X"32",X"33",X"34",X"35",X"33",X"34",X"35",X"36",X"34",X"35",X"36",
X"37",X"35",X"36",X"37",X"38",X"A0",X"FF",X"1F",X"0E",X"5F",X"09",X"6C",X"6C",X"60",X"6C",X"8C",
X"6E",X"6E",X"60",X"6E",X"8E",X"90",X"8E",X"6C",X"6E",X"6C",X"6E",X"8C",X"6E",X"70",X"6E",X"70",
X"8E",X"90",X"8E",X"A0",X"A0",X"A0",X"FF",X"1F",X"08",X"5F",X"09",X"AC",X"A0",X"A0",X"80",X"87",
X"AC",X"A0",X"A0",X"80",X"87",X"A0",X"A0",X"A0",X"FF",X"1F",X"0E",X"3F",X"0B",X"5F",X"09",X"69",
X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5",X"FF",X"1F",X"08",
X"5F",X"09",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",X"70",X"73",X"B5",
X"FF",X"1F",X"02",X"5F",X"08",X"69",X"69",X"60",X"6C",X"60",X"69",X"60",X"67",X"89",X"8C",X"6E",
X"70",X"73",X"B5",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",
X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

BIN
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/jungler.zip Normal file
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15
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_jungler_proms.bat Normal file
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@@ -0,0 +1,15 @@
copy /B jungr1 + jungr2 + jungr3 + jungr4 JUNGLER.ROM
make_vhdl_prom JUNGLER.ROM jng_prg_rom.vhd
copy /B 5k + 5m gfx1.bin
make_vhdl_prom gfx1.bin jng_chr_rom.vhd
make_vhdl_prom 82s129.10g jng_dot_rom.vhd
make_vhdl_prom 1b jng_snd_rom.vhd
make_vhdl_prom 18s030.8b jng_pal_rom.vhd
make_vhdl_prom tbp24s10.9d jng_col_rom.vhd

BIN
Arcade_MiST/Namco Rally X Hardware/Jungler_MiST/rtl/roms/make_vhdl_prom.exe Normal file
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