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https://github.com/Gehstock/Mist_FPGA.git
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Vectrex: remove HQ2x, wasn't used anyway
This commit is contained in:
Gyorgy Szombathelyi
@@ -1,454 +0,0 @@
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//
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//
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// Copyright (c) 2012-2013 Ludvig Strigeus
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// Copyright (c) 2017 Sorgelig
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//
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// This program is GPL Licensed. See COPYING for the full license.
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//
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//
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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`define BITS_TO_FIT(N) ( \
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N <= 2 ? 0 : \
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N <= 4 ? 1 : \
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N <= 8 ? 2 : \
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N <= 16 ? 3 : \
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N <= 32 ? 4 : \
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N <= 64 ? 5 : \
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N <= 128 ? 6 : \
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N <= 256 ? 7 : \
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N <= 512 ? 8 : \
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N <=1024 ? 9 : 10 )
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module hq2x_in #(parameter LENGTH, parameter DWIDTH)
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(
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input clk,
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input [AWIDTH:0] rdaddr,
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input rdbuf,
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output[DWIDTH:0] q,
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input [AWIDTH:0] wraddr,
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input wrbuf,
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input [DWIDTH:0] data,
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input wren
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);
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localparam AWIDTH = `BITS_TO_FIT(LENGTH);
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wire [DWIDTH:0] out[2];
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assign q = out[rdbuf];
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
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hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
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endmodule
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module hq2x_out #(parameter LENGTH, parameter DWIDTH)
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(
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input clk,
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input [AWIDTH:0] rdaddr,
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input [1:0] rdbuf,
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output[DWIDTH:0] q,
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input [AWIDTH:0] wraddr,
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input [1:0] wrbuf,
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input [DWIDTH:0] data,
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input wren
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);
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localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
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wire [DWIDTH:0] out[4];
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assign q = out[rdbuf];
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
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hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
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endmodule
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module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
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(
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input clock,
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input [DWIDTH:0] data,
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input [AWIDTH:0] rdaddress,
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input [AWIDTH:0] wraddress,
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input wren,
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output [DWIDTH:0] q
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);
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altsyncram altsyncram_component (
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.address_a (wraddress),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.address_b (rdaddress),
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.q_b(q),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken0 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b ({(DWIDTH+1){1'b1}}),
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.eccstatus (),
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.q_a (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.address_aclr_b = "NONE",
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altsyncram_component.address_reg_b = "CLOCK0",
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altsyncram_component.clock_enable_input_a = "BYPASS",
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altsyncram_component.clock_enable_input_b = "BYPASS",
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altsyncram_component.clock_enable_output_b = "BYPASS",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = NUMWORDS,
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altsyncram_component.numwords_b = NUMWORDS,
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altsyncram_component.operation_mode = "DUAL_PORT",
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altsyncram_component.outdata_aclr_b = "NONE",
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altsyncram_component.outdata_reg_b = "UNREGISTERED",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
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altsyncram_component.widthad_a = AWIDTH+1,
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altsyncram_component.widthad_b = AWIDTH+1,
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altsyncram_component.width_a = DWIDTH+1,
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altsyncram_component.width_b = DWIDTH+1,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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////////////////////////////////////////////////////////////////////////////////////////////////////////
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module DiffCheck
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(
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input [17:0] rgb1,
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input [17:0] rgb2,
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output result
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);
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wire [5:0] r = rgb1[5:1] - rgb2[5:1];
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wire [5:0] g = rgb1[11:7] - rgb2[11:7];
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wire [5:0] b = rgb1[17:13] - rgb2[17:13];
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wire [6:0] t = $signed(r) + $signed(b);
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wire [6:0] gx = {g[5], g};
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wire [7:0] y = $signed(t) + $signed(gx);
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wire [6:0] u = $signed(r) - $signed(b);
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wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
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// if y is inside (-24..24)
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wire y_inside = (y < 8'h18 || y >= 8'he8);
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// if u is inside (-4, 4)
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wire u_inside = (u < 7'h4 || u >= 7'h7c);
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// if v is inside (-6, 6)
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wire v_inside = (v < 8'h6 || v >= 8'hfA);
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assign result = !(y_inside && u_inside && v_inside);
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endmodule
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module InnerBlend
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(
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input [8:0] Op,
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input [5:0] A,
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input [5:0] B,
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input [5:0] C,
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output [5:0] O
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);
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function [8:0] mul6x3;
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input [5:0] op1;
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input [2:0] op2;
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begin
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mul6x3 = 9'd0;
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if(op2[0]) mul6x3 = mul6x3 + op1;
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if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
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if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
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end
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endfunction
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wire OpOnes = Op[4];
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wire [8:0] Amul = mul6x3(A, Op[7:5]);
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wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
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wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
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wire [8:0] At = Amul;
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wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
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wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
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wire [9:0] Res = {At, 1'b0} + Bt + Ct;
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assign O = Op[8] ? A : Res[9:4];
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endmodule
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module Blend
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(
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input [5:0] rule,
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input disable_hq2x,
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input [17:0] E,
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input [17:0] A,
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input [17:0] B,
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input [17:0] D,
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input [17:0] F,
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input [17:0] H,
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output [17:0] Result
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);
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reg [1:0] input_ctrl;
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reg [8:0] op;
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localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
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localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
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localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
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localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
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localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
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localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
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localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
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localparam AB = 2'b00;
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localparam AD = 2'b01;
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localparam DB = 2'b10;
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localparam BD = 2'b11;
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wire is_diff;
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DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
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always @* begin
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case({!is_diff, rule[5:2]})
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1,17: {op, input_ctrl} = {BLEND1, AB};
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2,18: {op, input_ctrl} = {BLEND1, DB};
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3,19: {op, input_ctrl} = {BLEND1, BD};
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4,20: {op, input_ctrl} = {BLEND2, DB};
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5,21: {op, input_ctrl} = {BLEND2, AB};
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6,22: {op, input_ctrl} = {BLEND2, AD};
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8: {op, input_ctrl} = {BLEND0, 2'bxx};
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9: {op, input_ctrl} = {BLEND0, 2'bxx};
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10: {op, input_ctrl} = {BLEND0, 2'bxx};
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11: {op, input_ctrl} = {BLEND1, AB};
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12: {op, input_ctrl} = {BLEND1, AB};
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13: {op, input_ctrl} = {BLEND1, AB};
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14: {op, input_ctrl} = {BLEND1, DB};
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15: {op, input_ctrl} = {BLEND1, BD};
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24: {op, input_ctrl} = {BLEND2, DB};
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25: {op, input_ctrl} = {BLEND5, DB};
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26: {op, input_ctrl} = {BLEND6, DB};
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27: {op, input_ctrl} = {BLEND2, DB};
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28: {op, input_ctrl} = {BLEND4, DB};
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29: {op, input_ctrl} = {BLEND5, DB};
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30: {op, input_ctrl} = {BLEND3, BD};
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31: {op, input_ctrl} = {BLEND3, DB};
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default: {op, input_ctrl} = 11'bx;
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endcase
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// Setting op[8] effectively disables HQ2X because blend will always return E.
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if (disable_hq2x) op[8] = 1;
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end
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// Generate inputs to the inner blender. Valid combinations.
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// 00: E A B
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// 01: E A D
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// 10: E D B
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// 11: E B D
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wire [17:0] Input1 = E;
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wire [17:0] Input2 = !input_ctrl[1] ? A :
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!input_ctrl[0] ? D : B;
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wire [17:0] Input3 = !input_ctrl[0] ? B : D;
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InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
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InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
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InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
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endmodule
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////////////////////////////////////////////////////////////////////////////////////////////////////
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module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
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(
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input clk,
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input ce_x4,
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input [DWIDTH:0] inputpixel,
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input mono,
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input disable_hq2x,
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input reset_frame,
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input reset_line,
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input [1:0] read_y,
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input [AWIDTH+1:0] read_x,
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output [DWIDTH:0] outpixel
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);
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localparam AWIDTH = `BITS_TO_FIT(LENGTH);
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localparam DWIDTH = HALF_DEPTH ? 8 : 17;
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wire [5:0] hqTable[256] = '{
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
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19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
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19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
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19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
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};
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reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
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reg [17:0] A, B, D, F, G, H;
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reg [7:0] pattern, nextpatt;
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reg [1:0] i;
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reg [7:0] y;
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wire curbuf = y[0];
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reg prevbuf = 0;
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wire iobuf = !curbuf;
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wire diff0, diff1;
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DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
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DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
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wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
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wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
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wire [17:0] blend_result;
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Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
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reg Curr2_addr1;
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reg [AWIDTH:0] Curr2_addr2;
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wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
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wire [DWIDTH:0] Curr2tmp;
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reg [AWIDTH:0] wrin_addr2;
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reg [DWIDTH:0] wrpix;
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reg wrin_en;
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function [17:0] h2rgb;
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input [8:0] v;
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begin
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h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
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end
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endfunction
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function [8:0] rgb2h;
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input [17:0] v;
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begin
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rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
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end
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endfunction
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hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
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(
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.clk(clk),
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.rdaddr(Curr2_addr2),
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.rdbuf(Curr2_addr1),
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.q(Curr2tmp),
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.wraddr(wrin_addr2),
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.wrbuf(iobuf),
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.data(wrpix),
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.wren(wrin_en)
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);
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reg [1:0] wrout_addr1;
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reg [AWIDTH+1:0] wrout_addr2;
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reg wrout_en;
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reg [DWIDTH:0] wrdata;
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hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
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(
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.clk(clk),
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.rdaddr(read_x),
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.rdbuf(read_y),
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.q(outpixel),
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.wraddr(wrout_addr2),
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.wrbuf(wrout_addr1),
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.data(wrdata),
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.wren(wrout_en)
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);
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always @(posedge clk) begin
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reg [AWIDTH:0] offs;
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reg old_reset_line;
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reg old_reset_frame;
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wrout_en <= 0;
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wrin_en <= 0;
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if(ce_x4) begin
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pattern <= new_pattern;
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if(~&offs) begin
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if (i == 0) begin
|
||||
Curr2_addr1 <= prevbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 1) begin
|
||||
Prev2 <= Curr2;
|
||||
Curr2_addr1 <= curbuf;
|
||||
Curr2_addr2 <= offs;
|
||||
end
|
||||
if (i == 2) begin
|
||||
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
|
||||
wrpix <= inputpixel;
|
||||
wrin_addr2 <= offs;
|
||||
wrin_en <= 1;
|
||||
end
|
||||
if (i == 3) begin
|
||||
offs <= offs + 1'd1;
|
||||
end
|
||||
|
||||
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
|
||||
else wrdata <= blend_result;
|
||||
|
||||
wrout_addr1 <= {curbuf, i[1]};
|
||||
wrout_addr2 <= {offs, i[1]^i[0]};
|
||||
wrout_en <= 1;
|
||||
end
|
||||
|
||||
if(i==3) begin
|
||||
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
|
||||
{A, G} <= {Prev0, Next0};
|
||||
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
|
||||
{Prev0, Prev1} <= {Prev1, Prev2};
|
||||
{Curr0, Curr1} <= {Curr1, Curr2};
|
||||
{Next0, Next1} <= {Next1, Next2};
|
||||
end else begin
|
||||
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
|
||||
{B, F, H, D} <= {F, H, D, B};
|
||||
end
|
||||
|
||||
i <= i + 1'b1;
|
||||
if(old_reset_line && ~reset_line) begin
|
||||
old_reset_frame <= reset_frame;
|
||||
offs <= 0;
|
||||
i <= 0;
|
||||
y <= y + 1'd1;
|
||||
prevbuf <= curbuf;
|
||||
if(old_reset_frame & ~reset_frame) begin
|
||||
y <= 0;
|
||||
prevbuf <= 0;
|
||||
end
|
||||
end
|
||||
|
||||
old_reset_line <= reset_line;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // Hq2x
|
||||
@@ -199,6 +199,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
|
||||
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/vectrex.vhd
|
||||
@@ -208,7 +209,6 @@ set_global_assignment -name QIP_FILE rtl/card.qip
|
||||
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/pll.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mc6809is.v
|
||||
@@ -218,5 +218,4 @@ set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/osd.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rgb2ypbpr.sv
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/rgb2ypbpr.sv
|
||||
Reference in New Issue
Block a user