mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-17 16:43:22 +00:00
Update jtopl
This commit is contained in:
parent
80b2323ff1
commit
8070eddf08
@ -21,7 +21,7 @@
|
||||
*/
|
||||
|
||||
module jtopl_csr #(
|
||||
parameter LEN=18, W=34
|
||||
parameter LEN=18, W=34, OPL_TYPE=1
|
||||
) ( // Circular Shift Register + input mux
|
||||
input rst,
|
||||
input clk,
|
||||
@ -70,8 +70,9 @@ assign regop_in[31:0] = { // 4 bytes:
|
||||
up_sl_rr_op ? din : shift_out[ 7: 0]
|
||||
};
|
||||
|
||||
`ifdef JTOPL2
|
||||
assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
|
||||
`endif
|
||||
generate if (OPL_TYPE == 2) begin
|
||||
assign regop_in[33:32] = up_wav_I ? din[1:0] : shift_out[33:32];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule // jtopl_reg
|
||||
@ -129,7 +129,7 @@ wire en_sus, rhy_oen;
|
||||
// Sustained is disabled in rhythm mode for channels in group 2 (i.e. 6,7,8)
|
||||
assign en_sus_I = rhy_oen ? 1'b0 : en_sus;
|
||||
|
||||
jtopl_csr #(.LEN(CH*2),.W(OPCFGW)) u_csr(
|
||||
jtopl_csr #(.LEN(CH*2),.W(OPCFGW), .OPL_TYPE(OPL_TYPE)) u_csr(
|
||||
.rst ( rst ),
|
||||
.clk ( clk ),
|
||||
.cen ( cen ),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user