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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-24 19:21:31 +00:00

Update Centiped.qsf

This commit is contained in:
Marcel 2021-06-23 17:31:03 +02:00
parent f6578a7bb9
commit 83a3d0e495

View File

@ -40,7 +40,7 @@
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
@ -147,15 +147,14 @@ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_RO
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/cent.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Centipede_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/centipede.v
set_global_assignment -name VERILOG_FILE rtl/pf_ram.v
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/POKEY.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/matoro.sv
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T65/T65.qip
set_global_assignment -name SIGNALTAP_FILE output_files/cent.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name QIP_FILE ../../../common/Sound/Pokey/Pokey.qip
set_global_assignment -name SIGNALTAP_FILE output_files/cent.stp