Add Checkmate

Arcade_MiST/Midway-Taito 8080 Hardware/Amazing Maze_MiST/rtl/AmazingMaze_mist.sv

@@ -121,7 +121,7 @@ mist_video #(.COLOR_DEPTH(1)) mist_video(
 	.SPI_DI(SPI_DI),
 	.R(Video),
 	.G(Video),
-	.B(1'b0),
+	.B(Video),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -189,11 +189,3 @@ arcade_inputs inputs (
 );
 
 endmodule 
-
-
-//mod_amazingmaze:
-//        begin
-//				WDEnabled 		<= 1'b0;
-
-//				software_flip  <= 0;
-//		 end

Arcade_MiST/Midway-Taito 8080 Hardware/Amazing Maze_MiST/rtl/AmazingMaze_overlay.vhd

@@ -1,127 +0,0 @@
-library ieee;
-  use ieee.std_logic_1164.all;
-  use ieee.std_logic_unsigned.all;
-  use ieee.numeric_std.all;
-
-
-entity AmazingMaze_overlay is
-	port(
-		Video             : in    std_logic;
-		Overlay           : in    std_logic;
-		CLK               : in    std_logic;
-		Rst_n_s           : in    std_logic;
-		HSync             : in    std_logic;
-		VSync             : in    std_logic;
-		O_VIDEO_R         : out   std_logic;
-		O_VIDEO_G         : out   std_logic;
-		O_VIDEO_B         : out   std_logic;
-		O_HSYNC           : out   std_logic;
-		O_VSYNC           : out   std_logic
-		);
-end AmazingMaze_overlay;
-
-architecture rtl of AmazingMaze_overlay is
-
-	signal HCnt            : std_logic_vector(11 downto 0);
-	signal VCnt            : std_logic_vector(11 downto 0);
-	signal HSync_t1        : std_logic;
-	signal Overlay_G1      : boolean;
-	signal Overlay_G2      : boolean;
-	signal Overlay_R1      : boolean;
-	signal Overlay_G1_VCnt : boolean;
-	signal VideoRGB        : std_logic_vector(2 downto 0);
-begin	
-	process (Rst_n_s, Clk)
-		variable cnt : unsigned(3 downto 0);
-	begin
-		if Rst_n_s = '0' then
-			cnt := "0000";
-		elsif Clk'event and Clk = '1' then
-			if cnt = 9 then
-				cnt := "0000";
-			else
-				cnt := cnt + 1;
-			end if;
-		end if;
-	end process;
-	
-  p_overlay : process(Rst_n_s, Clk)
-	variable HStart : boolean;
-  begin
-	if Rst_n_s = '0' then
-	  HCnt <= (others => '0');
-	  VCnt <= (others => '0');
-	  HSync_t1 <= '0';
-	  Overlay_G1_VCnt <= false;
-	  Overlay_G1 <= false;
-	  Overlay_G2 <= false;
-	  Overlay_R1 <= false;
-	elsif Clk'event and Clk = '1' then
-	  HSync_t1 <= HSync;
-	  HStart := (HSync_t1 = '0') and (HSync = '1');
-
-	  if HStart then
-		HCnt <= (others => '0');
-	  else
-		HCnt <= HCnt + "1";
-	  end if;
-
-	  if (VSync = '0') then
-		VCnt <= (others => '0');
-	  elsif HStart then
-		VCnt <= VCnt + "1";
-	  end if;
-
-	  if HStart then
-		if (Vcnt = x"1F") then
-		  Overlay_G1_VCnt <= true;
-		elsif (Vcnt = x"95") then
-		  Overlay_G1_VCnt <= false;
-		end if;
-	  end if;
-
-	  if (HCnt = x"027") and Overlay_G1_VCnt then
-		Overlay_G1 <= true;
-	  elsif (HCnt = x"046") then
-		Overlay_G1 <= false;
-	  end if;
-
-	  if (HCnt = x"046") then
-		Overlay_G2 <= true;
-	  elsif (HCnt = x"0B6") then
-		Overlay_G2 <= false;
-	  end if;
-
-	  if (HCnt = x"1A6") then
-		Overlay_R1 <= true;
-	  elsif (HCnt = x"1E6") then
-		Overlay_R1 <= false;
-	  end if;
-
-	end if;
-  end process;
-
-  p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
-  begin
-	if (Video = '0') then
-	  VideoRGB  <= "000";
-	else
-	  if Overlay_G1 or Overlay_G2 then
-		VideoRGB  <= "010";
-	  elsif Overlay_R1 then
-		VideoRGB  <= "100";
-	  else
-		VideoRGB  <= "111";
-	  end if;
-	end if;
-  end process;
-
-
-  O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
-  O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
-  O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
-  O_HSYNC   <= HSync;
-  O_VSYNC   <= VSync;
-
-
-end;

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/BalloonBomber.qsf

@@ -157,7 +157,6 @@ set_global_assignment -name VHDL_FILE rtl/invaders.vhd
 set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
 set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/BalloonBomber_memory.sv
-set_global_assignment -name VHDL_FILE rtl/BalloonBomber_Overlay.vhd
 set_global_assignment -name VHDL_FILE rtl/spram.vhd
 set_global_assignment -name VHDL_FILE rtl/pll.vhd
 set_global_assignment -name VHDL_FILE rtl/roms/tn07.vhd

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/README.txt

@@ -1,7 +1,7 @@
 ---------------------------------------------------------------------------------
 -- 
--- Arcade: Vortex port to MiST by Gehstock 
--- 08 June 2019
+-- Arcade: Balloon Bomber to MiST by Gehstock 
+-- 24 May 2021
 -- 
 ---------------------------------------------------------------------------------
 -- 

Arcade_MiST/Midway-Taito 8080 Hardware/BalloonBomber_MiST/rtl/BalloonBomber_mist.sv

@@ -22,14 +22,12 @@ localparam CONF_STR = {
 	"BallBomb;;",
 	"O2,Rotate Controls,Off,On;",
 	"O34,Scanlines,Off,25%,50%,75%;",
-	"O5,Overlay,On,Off;",
 	"T0,Reset;",
 	"V,v1.20.",`BUILD_DATE
 };
 
 wire  [1:0] scanlines = status[4:3];
 wire        rotate    = status[2];
-wire        overlay   = status[5];
 
 assign LED = 1;
 assign AUDIO_R = AUDIO_L;
@@ -94,8 +92,8 @@ invaderst invaderst(
 	.Rst_n_s(Rst_n_s),
 	.RWE_n(RWE_n),
 	.Video(Video),
-	.HSync(HSync),
-	.VSync(VSync)
+	.HSync(hs),
+	.VSync(vs)
 	);
 
 BalloonBomber_memory BalloonBomber_memory (
@@ -108,19 +106,6 @@ BalloonBomber_memory BalloonBomber_memory (
 	.Rom_out(IB)
 	);
 
-BalloonBomber_Overlay BalloonBomber_Overlay (
-	.Video(Video),
-	.Overlay(~overlay),
-	.CLK(clk_core),
-	.Rst_n_s(Rst_n_s),
-	.HSync(HSync),
-	.VSync(VSync),
-	.O_VIDEO_R(r),
-	.O_VIDEO_G(g),
-	.O_VIDEO_B(b),
-	.O_HSYNC(hs),
-	.O_VSYNC(vs)
-	);
 
 invaders_audio invaders_audio (
 	.Clk(clk_core),
@@ -134,9 +119,9 @@ mist_video #(.COLOR_DEPTH(1)) mist_video(
 	.SPI_SCK(SPI_SCK),
 	.SPI_SS3(SPI_SS3),
 	.SPI_DI(SPI_DI),
-	.R(r),
-	.G(g),
-	.B(b),
+	.R(Video),
+	.G(Video),
+	.B(Video),
 	.HSync(hs),
 	.VSync(vs),
 	.VGA_R(VGA_R),
@@ -193,7 +178,7 @@ arcade_inputs inputs (
 	.joystick_0  ( joystick_0  ),
 	.joystick_1  ( joystick_1  ),
 	.rotate      ( rotate      ),
-	.orientation ( 2'b01       ),
+	.orientation ( {2'b01}     ),
 	.joyswap     ( 1'b0        ),
 	.oneplayer   ( 1'b1        ),
 	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/Checkmate.qpf

@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 16:15:41  June 05, 2019
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "16:15:41  June 05, 2019"
+
+# Revisions
+
+PROJECT_REVISION = "Checkmate"

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/Checkmate.qsf

@@ -0,0 +1,169 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 02:57:11  June 09, 2019
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		Checkmate_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39  NOVEMBER 20, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name TOP_LEVEL_ENTITY Checkmate_mist
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# ---------------------------
+# start ENTITY(OzmaWars_mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(OzmaWars_mist)
+# -------------------------
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp5.stp
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Checkmate_mist.sv
+set_global_assignment -name VHDL_FILE rtl/invaders.vhd
+set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
+set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Checkmate_memory.sv
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
+set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/Checkmate.sdc

@@ -0,0 +1,126 @@
+## Generated SDC file "vectrex_MiST.out.sdc"
+
+## Copyright (C) 1991-2013 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
+
+## DATE    "Sun Jun 24 12:53:00 2018"
+
+##
+## DEVICE  "EP3C25E144C8"
+##
+
+# Clock constraints
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {CLOCK_27}]  1.000 [get_ports {CLOCK_27}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {CONF_DATA0}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DI}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SCK}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS2}]
+set_input_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_SS3}]
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {SPI_SCK}]  1.000 [get_ports {SPI_DO}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_L}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {AUDIO_R}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}]  1.000 [get_ports {LED}]
+set_output_delay -add_delay  -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}]  1.000 [get_ports {VGA_*}]
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/README.txt

@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: Checkmate to MiST by Gehstock 
+-- 26 May 2021
+-- 
+---------------------------------------------------------------------------------
+-- 
+-- Midway 8080 Hardware
+-- Audio based on work by Paul Walsh.
+-- Audio and scan converter by MikeJ.
+---------------------------------------------------------------------------------
+-- 
+-- 
+-- Keyboard inputs :
+--	ESC	:	Coin
+--   	F1      : 	Start
+--   	Ctrl    : 	Fire
+--   	Joystick: 	Movement
+--
+-- 4 Joystick support.
+-- 
+-- 
+---------------------------------------------------------------------------------
+
+ToDo  	Sound
+

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/clean.bat

@@ -0,0 +1,16 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s build_id.v
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+del PLLJ_PLLSPE_INFO.txt
+del *.qws
+del *.ppf
+del *.qip
+del *.ddb
+pause

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/Checkmate_memory.sv

@@ -0,0 +1,73 @@
+
+module Checkmate_memory(
+input				Clock,
+input				RW_n,
+input		[15:0]Addr,
+input		[15:0]Ram_Addr,
+output	 [7:0]Ram_out,
+input		 [7:0]Ram_in,
+output	 [7:0]Rom_out
+);
+
+wire [7:0]rom_data_0;
+wire [7:0]rom_data_1;
+wire [7:0]rom_data_2;
+wire [7:0]rom_data_3;
+sprom #(
+	.init_file("./roms/checkmat.h.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_h (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_0)
+	);
+
+sprom #(
+	.init_file("./roms/checkmat.g.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_g (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_1)
+	);
+	
+sprom #(
+	.init_file("./roms/checkmat.f.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_f (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_2)
+	);	
+	
+sprom #(
+	.init_file("./roms/checkmat.e.hex"),
+	.widthad_a(10),
+	.width_a(8))
+u_rom_e (
+	.clock(Clock),
+	.Address(Addr[9:0]),
+	.q(rom_data_3)
+	);		
+
+assign Rom_out = Addr[11:10] == 2'b00 ? rom_data_0 ://0000 00	11 1111 1111
+					  Addr[11:10] == 2'b01 ? rom_data_1 ://0000 01	11 1111 1111
+					  Addr[11:10] == 2'b10 ? rom_data_2 ://0000 10	11 1111 1111
+					  Addr[11:10] == 2'b11 ? rom_data_3 ://0000 11  11 1111 1111
+					  8'hz;
+		
+spram #(
+	.addr_width_g(13),
+	.data_width_g(8)) 
+u_ram0(
+	.address(Ram_Addr[12:0]),
+	.clken(1'b1),
+	.clock(Clock),
+	.data(Ram_in),
+	.wren(~RW_n),
+	.q(Ram_out)
+	);
+endmodule 

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/Checkmate_mist.sv

@@ -0,0 +1,191 @@
+module Checkmate_mist(
+	output        LED,						
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,	
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"Checkmate;;",
+	"O34,Scanlines,Off,25%,50%,75%;",
+	"T0,Reset;",
+	"V,v1.20.",`BUILD_DATE
+};
+
+wire  [1:0] scanlines = status[4:3];
+
+assign LED = 1;
+assign AUDIO_R = AUDIO_L;
+
+wire clk_core, clk_vid;
+wire pll_locked;
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.c0(clk_core),
+	.c1(clk_vid)
+);
+
+wire [63:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire [31:0] joystick_0,joystick_1,joystick_2,joystick_3;
+wire        scandoublerD;
+wire        ypbpr;
+wire        no_csync;
+wire        key_pressed;
+wire  [7:0] key_code;
+wire        key_strobe;
+wire  [7:0] audio;
+wire 			hs, vs;
+wire 			r,g,b;
+
+
+wire [15:0]RAB;
+wire [15:0]AD;
+wire [7:0]RDB;
+wire [7:0]RWD;
+wire [7:0]IB;
+wire [5:0]SoundCtrl3;
+wire [5:0]SoundCtrl5;
+wire Rst_n_s;
+wire RWE_n;
+wire Video;
+wire HSync;
+wire VSync;
+
+invaderst invaderst(
+	.Rst_n(~(status[0] | buttons[1])),
+	.Clk(clk_core),
+	.ENA(),
+	.GDB0({m_right2,m_left2,m_down2,m_up2,m_right,m_left,m_down,m_up}),
+	.GDB1({{m_right3,m_left3,m_down3,m_up3,m_right4,m_left4,m_down4,m_up4}}),
+	.GDB2({1'b0,1'b0,1'b0,1'b1,1'b0,1'b0,1'b0,1'b1}),//Service,Language,Language,Unused,Rounds,Rounds,Unused,Coinage
+	.GDB3({m_coin1,3'b000,m_four_players,m_three_players,m_two_players,m_one_player}),
+	.RDB(RDB),
+	.IB(IB),
+	.RWD(RWD),
+	.RAB(RAB),
+	.AD(AD),
+	.SoundCtrl3(SoundCtrl3),
+	.SoundCtrl5(SoundCtrl5),
+	.Rst_n_s(Rst_n_s),
+	.RWE_n(RWE_n),
+	.Video(Video),
+	.HSync(hs),
+	.VSync(vs)
+	);
+
+Checkmate_memory Checkmate_memory (
+	.Clock(clk_core),
+	.RW_n(RWE_n),
+	.Addr(AD),
+	.Ram_Addr(RAB),
+	.Ram_out(RDB),
+	.Ram_in(RWD),
+	.Rom_out(IB)
+	);
+
+
+invaders_audio invaders_audio (
+	.Clk(clk_core),
+	.S1(SoundCtrl3),
+	.S2(SoundCtrl5),
+	.Aud(audio)
+	);
+
+mist_video #(.COLOR_DEPTH(1)) mist_video(
+	.clk_sys(clk_vid),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(Video),
+	.G(Video),
+	.B(Video),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+//	.rotate({1'b0,rotate}),
+	.scandoubler_disable(scandoublerD),
+	.scanlines(scanlines),
+	.ce_divider(1'b0),
+	.ypbpr(ypbpr),
+	.no_csync(no_csync)
+	);
+
+user_io #(
+	.STRLEN(($size(CONF_STR)>>3)))
+user_io(
+	.clk_sys        (clk_core       ),
+	.conf_str       (CONF_STR       ),
+	.SPI_CLK        (SPI_SCK        ),
+	.SPI_SS_IO      (CONF_DATA0     ),
+	.SPI_MISO       (SPI_DO         ),
+	.SPI_MOSI       (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches       (switches       ),
+	.scandoubler_disable (scandoublerD	  ),
+	.ypbpr          (ypbpr          ),
+	.no_csync       (no_csync       ),
+	.key_strobe     (key_strobe     ),
+	.key_pressed    (key_pressed    ),
+	.key_code       (key_code       ),
+	.joystick_0     (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.joystick_2     (joystick_2     ),
+	.joystick_3     (joystick_3     ),
+	.status         (status         )
+	);
+
+dac dac (
+	.clk_i(clk_core),
+	.res_n_i(1),
+	.dac_i(audio),
+	.dac_o(AUDIO_L)
+	);
+
+wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
+wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
+
+wire m_up3, m_down3, m_left3, m_right3, m_fire3A, m_fire3B, m_fire3C, m_fire3D, m_fire3E, m_fire3F;
+wire m_up4, m_down4, m_left4, m_right4, m_fire4A, m_fire4B, m_fire4C, m_fire4D, m_fire4E, m_fire4F;
+wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
+
+arcade_inputs inputs (
+	.clk         ( clk_core    ),
+	.key_strobe  ( key_strobe  ),
+	.key_pressed ( key_pressed ),
+	.key_code    ( key_code    ),
+	.joystick_0  ( joystick_0  ),
+	.joystick_1  ( joystick_1  ),
+	.joystick_2  ( joystick_2  ),
+	.joystick_3  ( joystick_3  ),
+//	.rotate      ( rotate      ),
+//	.orientation ( {2'b01}     ),
+	.joyswap     ( 1'b0        ),
+	.oneplayer   ( 1'b0        ),
+	.controls    ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
+	.player1     ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
+	.player2     ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} ),
+	.player3     ( {m_fire3F, m_fire3E, m_fire3D, m_fire3C, m_fire3B, m_fire3A, m_up3, m_down3, m_left3, m_right3} ),
+	.player4     ( {m_fire4F, m_fire4E, m_fire4D, m_fire4C, m_fire4B, m_fire4A, m_up4, m_down4, m_left4, m_right4} )
+);
+
+endmodule

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/build_id.tcl

@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/invaders.vhd

@@ -0,0 +1,251 @@
+-- Space Invaders core logic
+-- 9.984MHz clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Cleaned up reset logic
+--
+--      0300 : MikeJ tidyup for audio release
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity invaderst is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		
+		GDB0           : in  std_logic_vector(7 downto 0);
+		GDB1            : in  std_logic_vector(7 downto 0);
+		GDB2            : in  std_logic_vector(7 downto 0);
+		GDB3            : in  std_logic_vector(7 downto 0);
+		
+		GDB4           : in  std_logic_vector(7 downto 0);
+		GDB5            : in  std_logic_vector(7 downto 0);
+		GDB6            : in  std_logic_vector(7 downto 0);
+
+		RDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		RWD             : out std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		SoundCtrl3      : out std_logic_vector(5 downto 0);
+		SoundCtrl5      : out std_logic_vector(5 downto 0);
+		Rst_n_s         : out std_logic;
+		RWE_n           : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic
+		);
+end invaderst;
+
+architecture rtl of invaderst is
+
+	component mw8080
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out  std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+	end component;
+
+
+	signal S            : std_logic_vector(7 downto 0);
+	signal GDB          : std_logic_vector(7 downto 0);
+	signal DB           : std_logic_vector(7 downto 0);
+	signal Sounds       : std_logic_vector(7 downto 0);
+	signal AD_i         : std_logic_vector(15 downto 0);
+	signal PortWr       : std_logic_vector(6 downto 2);
+	signal EA           : std_logic_vector(2 downto 0);
+	signal D5           : std_logic_vector(15 downto 0);
+	signal WD_Cnt       : unsigned(7 downto 0);
+	signal Sample       : std_logic;
+	signal Rst_n_s_i    : std_logic;
+	signal GDB_A        : unsigned(1 downto 0);
+begin
+
+	Rst_n_s <= Rst_n_s_i;
+	RWD <= DB;
+	AD <= AD_i;
+
+	process (Rst_n, Clk)
+		variable Rst_n_r : std_logic;
+	begin
+		if Rst_n = '0' then
+			Rst_n_r := '0';
+			Rst_n_s_i <= '0';
+		elsif Clk'event and Clk = '1' then
+			Rst_n_s_i <= Rst_n_r;
+			if WD_Cnt = 255 then
+				Rst_n_s_i <= '0';
+			end if;
+			Rst_n_r := '1';
+		end if;
+	end process;
+
+	process (Rst_n_s_i, Clk)
+		variable Old_S0 : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			WD_Cnt <= (others => '0');
+			Old_S0 := '1';
+		elsif Clk'event and Clk = '1' then
+			if Sounds(0) = '1' and Old_S0 = '0' then
+				WD_Cnt <= WD_Cnt + 1;
+			end if;
+			if PortWr(6) = '1' then
+				WD_Cnt <= (others => '0');
+			end if;
+			Old_S0 := Sounds(0);
+		end if;
+	end process;
+
+	u_mw8080: mw8080
+		port map(
+			Rst_n => '1',--Rst_n_s_i,
+			Clk => Clk,
+			ENA => ENA,
+			RWE_n => RWE_n,
+			RDB => RDB,
+			IB => IB,
+			RAB => RAB,
+			Sounds => Sounds,
+			Ready => open,
+			GDB => GDB,
+			DB => DB,
+			AD => AD_i,
+			Status => open,
+			Systb => open,
+			Int => open,
+			Hold_n => '1',
+			IntE => open,
+			DBin_n => open,
+			Vait => open,
+			HldA => open,
+			Sample => Sample,
+			Wr => open,
+			Video => Video,
+			HSync => HSync,
+			VSync => VSync);
+
+	with AD_i(10 downto 8) select
+		GDB <= GDB0 when "000",
+				GDB1 when "001",
+				GDB2 when "010",
+				GDB3 when "011",
+				GDB4 when "100",
+				GDB5 when "101",
+				GDB6 when "110",
+				S when others;
+
+
+	PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
+	PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
+	PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
+	PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
+	PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
+
+	process (Rst_n_s_i, Clk)
+		variable OldSample : std_logic;
+	begin
+		if Rst_n_s_i = '0' then
+			D5 <= (others => '0');
+			EA <= (others => '0');
+			SoundCtrl3 <= (others => '0');
+			SoundCtrl5 <= (others => '0');
+			OldSample := '0';
+		elsif Clk'event and Clk = '1' then
+			if PortWr(2) = '1' then
+				EA <= DB(2 downto 0);
+			end if;
+			if PortWr(3) = '1' then
+				SoundCtrl3 <= DB(5 downto 0);
+			end if;
+			if PortWr(4) = '1' and OldSample = '0' then
+				D5(15 downto 8) <= DB;
+				D5(7 downto 0) <= D5(15 downto 8);
+			end if;
+			if PortWr(5) = '1' then
+				SoundCtrl5 <= DB(5 downto 0);
+			end if;
+			OldSample := Sample;
+		end if;
+	end process;
+
+	with EA select
+		S <= D5(15 downto 8) when "000",
+			 D5(14 downto 7) when "001",
+			 D5(13 downto 6) when "010",
+			 D5(12 downto 5) when "011",
+			 D5(11 downto 4) when "100",
+			 D5(10 downto 3) when "101",
+			 D5( 9 downto 2) when "110",
+			 D5( 8 downto 1) when others;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/invaders_audio.vhd

@@ -0,0 +1,496 @@
+
+-- Version : 0300
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+-- minor tidy up by MikeJ
+-------------------------------------------------------------------------------
+-- Company:
+-- Engineer:    PaulWalsh
+--
+-- Create Date:    08:45:29 11/04/05
+-- Design Name:
+-- Module Name:    Invaders Audio
+-- Project Name:   Space Invaders
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+--------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+
+entity invaders_audio is
+	Port (
+	  Clk : in  std_logic;
+	  S1  : in  std_logic_vector(5 downto 0);
+	  S2  : in  std_logic_vector(5 downto 0);
+	  Aud : out std_logic_vector(7 downto 0)
+	  );
+end;
+ --* Port 3: (S1)
+ --* bit 0=UFO  (repeats)
+ --* bit 1=Shot
+ --* bit 2=Base hit
+ --* bit 3=Invader hit
+ --* bit 4=Bonus base
+ --*
+ --* Port 5: (S2)
+ --* bit 0=Fleet movement 1
+ --* bit 1=Fleet movement 2
+ --* bit 2=Fleet movement 3
+ --* bit 3=Fleet movement 4
+ --* bit 4=UFO 2
+
+architecture Behavioral of invaders_audio is
+
+  signal ClkDiv       : unsigned(10 downto 0) := (others => '0');
+  signal ClkDiv2      : std_logic_vector(7 downto 0) := (others => '0');
+  signal Clk7680_ena  : std_logic;
+  signal Clk480_ena   : std_logic;
+  signal Clk240_ena   : std_logic;
+  signal Clk60_ena    : std_logic;
+
+  signal s1_t1        : std_logic_vector(5 downto 0);
+  signal s2_t1        : std_logic_vector(5 downto 0);
+  signal tempsum      : std_logic_vector(7 downto 0);
+
+  signal vco_cnt      : std_logic_vector(3 downto 0);
+
+  signal TriDir1      : std_logic;
+  signal Fnum         : std_logic_vector(3 downto 0);
+  signal comp         : std_logic;
+
+  signal SS           : std_logic;
+
+  signal TrigSH       : std_logic;
+  signal SHCnt        : std_logic_vector(8 downto 0);
+  signal SH           : std_logic_vector(7 downto 0);
+  signal SauHit       : std_logic_vector(8 downto 0);
+  signal SHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigIH       : std_logic;
+  signal IHDir        : std_logic;
+  signal IHDir1       : std_logic;
+  signal IHCnt        : std_logic_vector(8 downto 0);
+  signal IH           : std_logic_vector(7 downto 0);
+  signal InHit        : std_logic_vector(8 downto 0);
+  signal IHitTri      : std_logic_vector(5 downto 0);
+
+  signal TrigEx       : std_logic;
+  signal Excnt        : std_logic_vector(9 downto 0);
+  signal ExShift      : std_logic_vector(15 downto 0);
+  signal Ex           : std_logic_vector(2 downto 0);
+  signal Explo        : std_logic;
+
+  signal TrigMis      : std_logic;
+  signal MisShift     : std_logic_vector(15 downto 0);
+  signal MisCnt       : std_logic_vector(8 downto 0);
+  signal miscnt1      : unsigned(7 downto 0);
+  signal Mis          : std_logic_vector(2 downto 0);
+  signal Missile      : std_logic;
+
+  signal EnBG         : std_logic;
+  signal BGFnum       : std_logic_vector(7 downto 0);
+  signal BGCnum       : std_logic_vector(7 downto 0);
+  signal bg_cnt       : unsigned(7 downto 0);
+  signal BG           : std_logic;
+
+begin
+
+  -- do a crude addition of all sound samples
+	p_audio_mix : process
+	  variable IHVol : std_logic_vector(6 downto 0);
+	  variable SHVol : std_logic_vector(6 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+
+	  IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
+	  SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
+
+	  tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
+
+	  Aud(7) <= tempsum (7);
+	  Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor  (Ex(2) and Explo) xor BG;
+	  Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor  (Ex(1) and Explo) xor SS;
+	  Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor  (Ex(0) and Explo);
+	  Aud(3 downto 0) <= tempsum (3 downto 0);
+
+	end process;
+
+	p_clkdiv : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk7680_ena <= '0';
+	  if ClkDiv =  1277 then
+		Clk7680_ena <= '1';
+		ClkDiv <= (others => '0');
+	  else
+		ClkDiv <= ClkDiv + 1;
+	  end if;
+	end process;
+
+	p_clkdiv2 : process
+	begin
+	  wait until rising_edge(Clk);
+	  Clk480_ena <= '0';
+	  Clk240_ena <= '0';
+	  Clk60_ena  <= '0';
+
+	  if (Clk7680_ena = '1') then
+		ClkDiv2 <= ClkDiv2 + 1;
+
+		if (ClkDiv2(3 downto 0) = "0000") then
+		  Clk480_ena <= '1';
+		end if;
+
+		if (ClkDiv2(4 downto 0) = "00000") then
+		  Clk240_ena <= '1';
+		end if;
+
+		if (ClkDiv2(7 downto 0) = "00000000") then
+		  Clk60_ena <= '1';
+		end if;
+
+	  end if;
+	end process;
+
+   p_delay : process
+   begin
+	 wait until rising_edge(Clk);
+	 s1_t1 <= S1;
+	 s2_t1 <= S2;
+   end process;
+--*************************Saucer Sound***************************************
+
+-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
+	p_saucer_vco : process
+	  variable term : std_logic_vector(3 downto 0);
+	begin
+	  wait until rising_edge(Clk);
+	  term := 8 + Fnum;
+	  if (S1(0) = '1') and (Clk7680_ena = '1') then
+		if vco_cnt = term then
+
+		  vco_cnt <= (others => '0');
+		  SS <= not SS;
+		else
+		  vco_cnt <= vco_cnt + 1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
+	-- this is 6Hz ?? 0123454321
+	p_saucer_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk60_ena = '1') then
+		if Fnum = 4 then -- 5 -1
+		  Comp <= '1';
+		elsif Fnum = 1 then -- 0 +1
+		  Comp <= '0';
+		end if;
+
+		if comp = '1' then
+		  Fnum <= Fnum - 1 ;
+		else
+		  Fnum <= Fnum + 1 ;
+		end if;
+	  end if;
+	end process;
+
+--**********************SAUCER HIT Sound**************************
+
+-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
+	p_saucer_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if SHitTri = 48 then
+		  SHitTri <= "000000";
+		else
+		  SHitTri <= SHitTri+1;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Saucer Hit      200Hz to 1kHz approx
+	p_saucer_hit_lfo : process
+	begin
+	 wait until rising_edge(Clk);
+	 if (Clk7680_ena = '1') then
+			if TriDir1 = '1' then
+				if (SauHit +58 - SHitTri) < 190 + 256 then
+					SauHit <= SauHit +58 - SHitTri;
+				else
+					SauHit <= "110111110";
+					TriDir1 <= '0';
+				end if;
+			else
+				if (SauHit -58 + SHitTri) > 256 then
+					SauHit <= SauHit -58 + SHitTri;
+				else
+					SauHit <= "100000000";
+					TriDir1 <= '1';
+				end if;
+			end if;
+	end if;
+  end process;
+
+-- Implement the ADSR for Saucer Hit Sound
+	p_saucer_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigSH = '1') then
+		  SHCnt <= "100000000";
+		  SH <= "11111111";
+		elsif (SHCnt(8) = '1') then
+		  SHCnt <= SHCnt + "1";
+		  if SHCnt(7 downto 0) = x"60" then -- 96
+			SH <= "01111111";
+		  elsif SHCnt(7 downto 0) = x"90" then -- 144
+			SH <= "00111111";
+		  elsif SHCnt(7 downto 0) = x"C0" then -- 192
+			SH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+ -- Implement the trigger for The Saucer Hit Sound
+	p_saucer_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
+		TrigSH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigSH <= '0';
+	  end if;
+	end process;
+
+--***********************Invader Hit Sound*****************************
+-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
+	p_invader_hit_lfo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if IHitTri = 48-2 then
+		  IHDir <= '0';
+		elsif IHitTri =0+2 then
+		  IHDir <= '1';
+		end if;
+
+		if IHDir ='1' then
+		  IHitTri <= IHitTri + 2;
+		else
+		  IHitTri <= IHitTri - 2;
+		end if;
+	  end if;
+	end process;
+
+-- Implement a trianglular wave VCO for Invader Hit     700Hz to 3kHz approx
+	p_invader_hit_vco : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if IHDir1 = '1' then
+		  if (InHit +10 + IHitTri) < 110 + 256 then
+			 InHit <= InHit +10 + IHitTri;
+		   else
+			 InHit <= "101101110";
+			 IHDir1 <= '0';
+		   end if;
+		else
+		  if (InHit -10 - IHitTri) > 256 then
+			 InHit <= InHit -10 - IHitTri;
+		  else
+			 InHit <= "100000000";
+			 IHDir1 <= '1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the ADSR for Invader Hit Sound
+	p_invader_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigIH = '1') then
+		  IHCnt <= "100000000";
+		  IH <= "11111111";
+		elsif (IHCnt(8) = '1') then
+		  IHCnt <= IHCnt + "1";
+		  if IHCnt(7 downto 0) = x"14" then -- 20
+			IH <= "01111111";
+		  elsif IHCnt(7 downto 0) = x"1C" then -- 28
+			IH <= "11111111";
+		  elsif IHCnt(7 downto 0) = x"30" then -- 48
+			IH <= "00000000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+  -- Implement the trigger for The Invader Hit Sound
+	p_invader_hit : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
+		TrigIH <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigIH <= '0';
+	  end if;
+	end process;
+
+--***********************Explosion*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_explosion_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (ExShift = x"0000") then
+		  ExShift <= "0000000010101001";
+		else
+		  ExShift(0) <= Exshift(14) xor ExShift(15);
+		  ExShift(15 downto 1)  <= ExShift (14 downto 0);
+		end if;
+	  end if;
+	end process;
+	Explo <= ExShift(0);
+
+	p_explosion_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigEx = '1') then
+		  ExCnt <= "1000000000";
+		  Ex <= "100";
+		elsif (ExCnt(9) = '1') then
+		  ExCnt <= ExCnt + "1";
+		  if ExCnt(8 downto 0) = '0' & x"64" then -- 100
+			Ex <= "010";
+		  elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
+			Ex <= "001";
+		  elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
+			Ex <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Explosion Sound
+	p_explosion_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
+		TrigEx <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigEx <= '0';
+	  end if;
+	end process;
+
+--***********************Missile*****************************
+-- Implement a Pseudo Random Noise Generator
+	p_missile_pseudo : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if (MisShift = x"0000") then
+		  MisShift <= "0000000010101001";
+		else
+		  MisShift(0) <= MisShift(14) xor MisShift(15);
+		  MisShift(15 downto 1)  <= MisShift (14 downto 0);
+		end if;
+
+		miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
+		if miscnt1 > 60 then
+		  miscnt1 <= "00000000";
+		  Missile <= not Missile;
+		end if;
+
+	  end if;
+	end process;
+
+-- Implement the ADSR for The Missile Sound
+	p_missile_adsr : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk480_ena = '1') then
+		if (TrigMis = '1') then
+		  MisCnt <= "100000000";
+		  Mis <= "100";
+		elsif (MisCnt(8) = '1') then
+		  MisCnt <= MisCnt + "1";
+		  if MisCnt(7 downto 0) = x"4b" then -- 75
+			Mis <= "010";
+		  elsif MisCnt(7 downto 0) = x"70" then -- 112
+			Mis <= "001";
+		  elsif MisCnt(7 downto 0) = x"96" then -- 150
+			Mis <= "000";
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+-- Implement the trigger for The Missile Sound
+	p_missile_trig : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
+		TrigMis <= '1';
+	  elsif (Clk480_ena = '1') then
+		TrigMis <= '0';
+	  end if;
+	end process;
+
+-- ******************************** Background invader moving tones **************************
+	EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
+
+	with S2(3 downto 0) select
+		BGFnum <= x"66" when "0001",
+				  x"74" when "0010",
+				  x"7C" when "0100",
+				  x"87" when "1000",
+				  x"87" when others;
+
+	with S2(3 downto 0) select
+		BGCnum <= x"33" when "0001",
+				  x"3A" when "0010",
+				  x"3E" when "0100",
+				  x"43" when "1000",
+				  x"43" when others;
+
+-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
+
+	p_background : process
+	begin
+	  wait until rising_edge(Clk);
+	  if (Clk7680_ena = '1') then
+		if EnBG = '0' then
+		  bg_cnt <= x"00";
+		  BG <= '0';
+		else
+		  bg_cnt <= bg_cnt + 1;
+
+		  if bg_cnt = unsigned(BGfnum) then
+			bg_cnt <= x"00";
+			BG  <= '0';
+		  elsif bg_cnt=unsigned(BGCnum) then
+			BG <='1';
+		  end if;
+		end if;
+	  end if;
+	end process;
+
+end Behavioral;

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/mw8080.vhd

@@ -0,0 +1,336 @@
+-- Midway 8080 main board
+-- 9.984MHz Clock
+--
+-- Version : 0242
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.fpgaarcade.com
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0241 : First release
+--
+--      0242 : Removed the ROM
+--
+--      0300 : MikeJ tidyup for audio release
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity mw8080 is
+	port(
+		Rst_n           : in  std_logic;
+		Clk             : in  std_logic;
+		ENA             : out std_logic;
+		RWE_n           : out std_logic;
+		RDB             : in  std_logic_vector(7 downto 0);
+		RAB             : out std_logic_vector(12 downto 0);
+		Sounds          : out std_logic_vector(7 downto 0);
+		Ready           : out std_logic;
+		GDB             : in  std_logic_vector(7 downto 0);
+		IB              : in  std_logic_vector(7 downto 0);
+		DB              : out std_logic_vector(7 downto 0);
+		AD              : out std_logic_vector(15 downto 0);
+		Status          : out std_logic_vector(7 downto 0);
+		Systb           : out std_logic;
+		Int             : out std_logic;
+		Hold_n          : in  std_logic;
+		IntE            : out std_logic;
+		DBin_n          : out std_logic;
+		Vait            : out std_logic;
+		HldA            : out std_logic;
+		Sample          : out std_logic;
+		Wr              : out std_logic;
+		Video           : out std_logic;
+		HSync           : out std_logic;
+		VSync           : out std_logic);
+end mw8080;
+
+architecture struct of mw8080 is
+
+	component T8080se
+	generic(
+		Mode : integer := 2;
+		T2Write : integer := 0);
+	port(
+		RESET_n         : in  std_logic;
+		CLK             : in  std_logic;
+		CLKEN           : in  std_logic;
+		READY           : in  std_logic;
+		HOLD            : in  std_logic;
+		INT             : in  std_logic;
+		INTE            : out std_logic;
+		DBIN            : out std_logic;
+		SYNC            : out std_logic;
+		VAIT            : out std_logic;
+		HLDA            : out std_logic;
+		WR_n            : out std_logic;
+		A               : out std_logic_vector(15 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : out std_logic_vector(7 downto 0));
+	end component;
+
+	signal Ready_i      : std_logic;
+	signal Hold         : std_logic;
+	signal IntTrig      : std_logic;
+	signal IntTrigOld   : std_logic;
+	signal Int_i        : std_logic;
+	signal IntE_i       : std_logic;
+	signal DBin         : std_logic;
+	signal Sync         : std_logic;
+	signal Wr_n, Rd_n   : std_logic;
+	signal ClkEnCnt     : unsigned(2 downto 0);
+	signal Status_i     : std_logic_vector(7 downto 0);
+	signal A            : std_logic_vector(15 downto 0);
+	signal ISel         : std_logic_vector(1 downto 0);
+	signal DI           : std_logic_vector(7 downto 0);
+	signal DO           : std_logic_vector(7 downto 0);
+	signal RR           : std_logic_vector(9 downto 0);
+
+	signal VidEn        : std_logic;
+	signal CntD5        : unsigned(3 downto 0); -- Horizontal counter / 320
+	signal CntE5        : unsigned(4 downto 0); -- Horizontal counter 2
+	signal CntE6        : unsigned(3 downto 0); -- Vertical counter / 262
+	signal CntE7        : unsigned(4 downto 0); -- Vertical counter 2
+	signal Shift        : std_logic_vector(7 downto 0);
+
+begin
+	ENA <= ClkEnCnt(2);
+	Status <= Status_i;
+	Ready <= Ready_i;
+	DB <= DO;
+	Systb <= Sync;
+	Int <= Int_i;
+	Hold <= not Hold_n;
+	IntE <= IntE_i;
+	DBin_n <= not DBin;
+	Sample <= not Wr_n and Status_i(4);
+	Wr <= not Wr_n;
+	AD <= A;
+	Sounds(0) <= CntE7(3);
+	Sounds(1) <= CntE7(2);
+	Sounds(2) <= CntE7(1);
+	Sounds(3) <= CntE7(0);
+	Sounds(4) <= CntE6(3);
+	Sounds(5) <= CntE6(2);
+	Sounds(6) <= CntE6(1);
+	Sounds(7) <= CntE6(0);
+
+	IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
+
+	ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
+	ISel(1) <= Status_i(0) nor Status_i(6);
+
+	with ISel select
+		DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
+			GDB when "01",
+			IB when "10",
+			RR(7 downto 0) when others;
+
+	RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
+	RAB <= A(12 downto 0) when CntD5(2) = '1' else
+		std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
+
+	u_8080: T8080se
+		generic map (
+			Mode => 2,
+			T2Write => 1)
+		port map (
+			RESET_n => Rst_n,
+			CLK => Clk,
+			CLKEN => ClkEnCnt(2),
+			READY => Ready_i,
+			HOLD => Hold,
+			INT => Int_i,
+			INTE => IntE_i,
+			DBIN => DBin,
+			SYNC => Sync,
+			VAIT => Vait,
+			HLDA => HLDA,
+			WR_n => Wr_n,
+			A => A,
+			DI => DI,
+			DO => DO);
+
+	-- Clock enables
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			ClkEnCnt <= "000";
+			VidEn <= '0';
+		elsif Clk'event and Clk = '1' then
+			VidEn <= not VidEn;
+			if ClkEnCnt = 4 then
+				ClkEnCnt <= "000";
+			else
+				ClkEnCnt <= ClkEnCnt + 1;
+			end if;
+		end if;
+	end process;
+
+	-- Glue
+	process (Rst_n, Clk)
+		variable OldASEL : std_logic;
+	begin
+		if Rst_n = '0' then
+			Status_i <= (others => '0');
+			IntTrigOld <= '0';
+			Int_i <= '0';
+			OldASEL := '0';
+			Ready_i <= '0';
+			RR <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			-- E3
+			-- Interrupt
+			IntTrigOld <= IntTrig;
+			if Status_i(0) = '1' then
+				Int_i <= '0';
+			elsif IntTrigOld = '0' and IntTrig = '1' then
+				Int_i <= IntE_i;
+			end if;
+
+			-- D7
+			-- Status register
+			if Sync = '1' then
+				Status_i <= DO;
+			end if;
+
+			-- A3, C3, E3
+			-- RAM register/ready logic
+			if Sync = '1' and A(13) = '1' then
+				Ready_i <= '0';
+			elsif Ready_i = '1' then
+				Ready_i <= '1';
+			else
+				Ready_i <= RR(9);
+			end if;
+			if Sync = '1' and A(13) = '1' then
+				RR <= (others => '0');
+			elsif (CntD5(2) = '1' and OldASEL = '0') or                                 -- ASEL pos edge
+				(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
+				RR(7 downto 0) <= RDB;
+				RR(8) <= '1';
+				RR(9) <= RR(8);
+			end if;
+			OldASEL := CntD5(2);
+		end if;
+	end process;
+
+	-- Video counters
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			CntD5 <= (others => '0');
+			CntE5 <= (others => '0');
+			CntE6 <= (others => '0');
+			CntE7 <= (others => '0');
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				CntD5 <= CntD5 + 1;
+				if CntD5 = 15 then
+
+					CntE5 <= CntE5 + 1;
+					if CntE5(3 downto 0) = 15 then
+						if CntE5(4) = '0' then
+							CntE5 <= "11100";
+
+							CntE6 <= CntE6 + 1;
+							if CntE6 = 15 then
+
+								CntE7 <= CntE7 + 1;
+								if CntE7(3 downto 0) = 15 then
+									if CntE7(4) = '0' then
+										CntE6 <= "1010";
+										CntE7 <= "11101";
+									else
+										CntE7 <= "00010";
+									end if;
+								end if;
+							end if;
+						end if;
+					else
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	-- Video shift register
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			Shift <= (others => '0');
+			Video <= '0';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
+					Shift(7 downto 0) <= RDB(7 downto 0);
+				else
+					Shift(6 downto 0) <= Shift(7 downto 1);
+					Shift(7) <= '0';
+				end if;
+				Video <= Shift(0);
+			end if;
+		end if;
+	end process;
+
+	-- Sync
+	process (Rst_n, Clk)
+	begin
+		if Rst_n = '0' then
+			HSync <= '1';
+			VSync <= '1';
+		elsif Clk'event and Clk = '1' then
+			if VidEn = '1' then
+				if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
+					HSync <= '0';
+				else
+					HSync <= '1';
+				end if;
+				if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
+					VSync <= '0';
+				else
+					VSync <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/pll.qip

@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/pll.vhd

@@ -0,0 +1,382 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire2    <= sub_wire0(1);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	c1    <= sub_wire2;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1125,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 416,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 1125,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 832,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire4,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "9.984000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "19.968000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "9.98400000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "19.96800000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "416"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1125"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "832"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/roms/checkmat.e.hex

@@ -0,0 +1,34 @@
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+:2003E0001429143900F00000140405A90519057900320000000000000000000000000000EF
+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/roms/checkmat.f.hex

@@ -0,0 +1,34 @@
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+:2003E0000B0D0DCDE80B0CC93AE921A7C2FD0BE5CD590C7AC2F90BF6800757E1C93DC23585
+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/roms/checkmat.g.hex

@@ -0,0 +1,34 @@
+:020000040000FA
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+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/roms/checkmat.h.hex

@@ -0,0 +1,34 @@
+:020000040000FA
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+:2003E000955551FFFF7EE6F0C2F4033E40CD0004C3FB037E07070707CDFC037EE60FC630D8
+:00000001FF

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/spram.vhd

@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;

Arcade_MiST/Midway-Taito 8080 Hardware/Checkmate_MiST/rtl/sprom.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;

common/CPU/NextZ80/NextZ80.qip

@@ -0,0 +1,3 @@
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80ALU.v      ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80CPU.v     ]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) NextZ80Reg.v    ]