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Marcel
2019-03-15 21:10:24 +01:00
parent 79400be9d0
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Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 02:40:30 January 25, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "02:40:30 January 25, 2017"
# Revisions
PROJECT_REVISION = "Capitol_mist"

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Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 20:38:53 March 15, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Capitol_mist_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Capitol_MiST.sv
set_global_assignment -name VHDL_FILE rtl/phoenix.vhd
set_global_assignment -name VHDL_FILE rtl/phoenix_effect3.vhd
set_global_assignment -name VHDL_FILE rtl/phoenix_effect2.vhd
set_global_assignment -name VHDL_FILE rtl/phoenix_effect1.vhd
set_global_assignment -name VHDL_FILE rtl/phoenix_video.vhd
set_global_assignment -name VHDL_FILE rtl/phoenix_music.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Capitol_MiST
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------
# start ENTITY(Capitol_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Capitol_MiST)
# ------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/phoenix_mist.sdc → Arcade_MiST/Phoenix Hardware/Capitol_MIST/Capitol_mist.sdc
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24
Arcade_MiST/Phoenix Hardware/Capitol_MIST/README.txt Normal file
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---------------------------------------------------------------------------------
--
-- Arcade: Capitol for MiST by Gehstock
-- 15 Mar 2019
--
---------------------------------------------------------------------------------
-- Copyright (c) DAR - Feb 2016
-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/phoenix/
---------------------------------------------------------------------------------
--
-- Only controls and OSD are rotated on VGA output.
--
--
-- Keyboard inputs :
--
-- ESC : Coin
-- F1 : Start 1 player
-- F2 : Start 2 players
-- SPACE : Fire
-- ARROW KEYS : Movement/Shield
--
-- Joystick support.
--
---------------------------------------------------------------------------------

BIN
Arcade_MiST/Phoenix Hardware/Capitol_MIST/Release/Capitol_mist.rbf Normal file
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Binary file not shown.

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/clean.bat → Arcade_MiST/Phoenix Hardware/Capitol_MIST/clean.bat
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184
Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/Capitol_MiST.sv Normal file
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//============================================================================
// Arcade: Capitol
//
//-------------------------------------------------------------------------------
// DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) (April 2016)
// http://darfpga.blogspot.fr
//
//
//-------------------------------------------------------------------------------
module Capitol_MiST
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Capitol;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys, clk_mist;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_mist),//44
.c1(clk_sys)//11
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
reg [11:0] audio;
wire hb1, hb2, vb;
wire blankn = ~(hb1 | hb2 | vb);
wire ce_pix;
wire hs, vs;
wire [1:0] r,g,b;
phoenix phoenix(
.clk(clk_sys),
.reset(status[0] | status[6] | buttons[1]),
.ce_pix(ce_pix),
.dip_switch(8'b00001111),
.btn_coin(btn_coin),
.btn_player_start({btn_two_players,btn_one_player}),
.btn_left(m_left),
.btn_right(m_right),
.btn_barrier(m_bomb),
.btn_fire(m_fire),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hs(hs),
.video_vs(vs),
.video_vblank(vb),
.video_hblank_bg(hb1),
.video_hblank_fg(hb2),
.audio_select("000"),
.audio(audio)
);
video_mixer video_mixer(
.clk_sys(clk_mist),
.ce_pix(ce_pix),
.ce_pix_actual(ce_pix),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? {r,r,r} : "000"),
.G(blankn ? {g,g,g} : "000"),
.B(blankn ? {b,b,b} : "000"),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.rotate({1'b1,status[2]}),
.scandoublerD(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr),
.ypbpr_full(1),
.line_start(0),
.mono(0)
);
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clk_mist ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoublerD (scandoublerD ),
.ypbpr (ypbpr ),
.ps2_key (ps2_key ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(15))
dac(
.clk_i(clk_mist),
.res_n_i(1),
.dac_i({audio, 4'b0000}),
.dac_o(AUDIO_L)
);
// Rotated Normal
//wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
//wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire pressed = ps2_key[9];
wire [7:0] code = ps2_key[7:0];
always @(posedge clk_mist) begin
reg old_state;
old_state <= ps2_key[10];
if(old_state != ps2_key[10]) begin
case(code)
'h75: btn_up <= pressed; // up
'h72: btn_down <= pressed; // down
'h6B: btn_left <= pressed; // left
'h74: btn_right <= pressed; // right
'h76: btn_coin <= pressed; // ESC
'h05: btn_one_player <= pressed; // F1
'h06: btn_two_players <= pressed; // F2
'h14: btn_fire3 <= pressed; // ctrl
'h11: btn_fire2 <= pressed; // alt
'h29: btn_fire1 <= pressed; // Space
endcase
end
end
endmodule

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Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/ROM/prog.hex Normal file
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Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/T80/T80_ALU.vhd → Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/T80/T80_ALU.vhd
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Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/T80/T80_Reg.vhd → Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/T80/T80_Reg.vhd
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---------------------------------------------------------------------------------
-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
entity phoenix is
generic (
C_test_picture: boolean := false;
C_tile_rom: boolean := true; -- false: disable tile ROM to try game logic on small FPGA
-- reduce ROMs: 14 is normal game, 13 will draw initial screen, 12 will repeatedly blink 1 line of garbage
C_autofire: boolean := true;
-- C_audio: boolean := true;
C_prog_rom_addr_bits: integer range 12 to 14 := 14
);
port(
clk : in std_logic; -- 11 MHz for TV, 25 MHz for VGA
reset : in std_logic;
ce_pix : out std_logic;
dip_switch : in std_logic_vector(7 downto 0);
-- game controls, normal logic '1':pressed, '0':released
btn_coin: in std_logic;
btn_player_start: in std_logic_vector(1 downto 0);
btn_fire, btn_left, btn_right, btn_barrier: in std_logic;
video_r : out std_logic_vector(1 downto 0);
video_g : out std_logic_vector(1 downto 0);
video_b : out std_logic_vector(1 downto 0);
video_vblank, video_hblank_bg, video_hblank_fg: out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
sound_fire : out std_logic; -- '1' when missile fires
sound_explode: out std_logic; -- '1' when ship explodes
sound_burn : out std_logic; -- bird burns
sound_fireball: out std_logic; -- bird explodes in 2 fireballs
sound_ab : out std_logic_vector(15 downto 0);
audio_select : in std_logic_vector(2 downto 0) := (others => '0');
audio : out std_logic_vector(11 downto 0)
);
end phoenix;
architecture struct of phoenix is
signal reset_n: std_logic;
signal hcnt : std_logic_vector(9 downto 1);
signal vcnt : std_logic_vector(8 downto 1);
signal sync : std_logic;
signal adrsel : std_logic;
signal rdy : std_logic := '1';
signal vblank : std_logic;
signal hblank_bkgrd : std_logic;
signal hblank_frgrd : std_logic;
signal ce_pix1 : std_logic;
signal cpu_adr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_wr_n : std_logic;
signal prog_do : std_logic_vector( 7 downto 0);
signal S_prog_rom_addr : std_logic_vector(13 downto 0);
signal frgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_horz_cnt : std_logic_vector(7 downto 0) := (others =>'0');
signal vert_cnt : std_logic_vector(7 downto 0) := (others =>'0');
signal frgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
signal bkgnd_ram_adr: std_logic_vector(10 downto 0) := (others =>'0');
signal frgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
signal bkgnd_ram_do : std_logic_vector( 7 downto 0) := (others =>'0');
signal frgnd_ram_we : std_logic := '0';
signal bkgnd_ram_we : std_logic := '0';
signal frgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
signal bkgnd_graph_adr : std_logic_vector(11 downto 0) := (others =>'0');
signal palette_adr : std_logic_vector( 7 downto 0) := (others =>'0');
signal A11 : std_logic;
signal frgnd_clk : std_logic;
signal bkgnd_clk : std_logic;
signal frgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_tile_id : std_logic_vector(7 downto 0) := (others =>'0');
signal frgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
signal frgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_bit0_graph : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_bit1_graph : std_logic_vector(7 downto 0) := (others =>'0');
signal frgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
signal frgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_bit0_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
signal bkgnd_bit1_graph_r : std_logic_vector(7 downto 0) := (others =>'0');
signal fr_bit0 : std_logic;
signal fr_bit1 : std_logic;
signal bk_bit0 : std_logic;
signal bk_bit1 : std_logic;
signal fr_lin : std_logic_vector(2 downto 0);
signal bk_lin : std_logic_vector(2 downto 0);
signal color_set : std_logic;
signal color_set2 : std_logic;
signal color_id : std_logic_vector(5 downto 0);
signal rgb_0 : std_logic_vector(2 downto 0);
signal rgb_1 : std_logic_vector(2 downto 0);
signal player2 : std_logic := '0';
signal pl2_cocktail : std_logic := '0';
signal bkgnd_offset : std_logic_vector(7 downto 0) := (others =>'0');
signal sound_a : std_logic_vector(7 downto 0) := (others =>'0');
signal sound_b : std_logic_vector(7 downto 0) := (others =>'0');
signal clk10 : std_logic;
signal snd1 : std_logic_vector( 7 downto 0) := (others =>'0');
signal snd2 : std_logic_vector( 1 downto 0) := (others =>'0');
signal snd3 : std_logic_vector( 7 downto 0) := (others =>'0');
signal song : std_logic_vector( 7 downto 0) := (others =>'0');
signal mixed : std_logic_vector(11 downto 0) := (others =>'0');
signal sound_string : std_logic_vector(31 downto 0);
signal coin : std_logic;
signal player_start : std_logic_vector(1 downto 0);
signal buttons : std_logic_vector(3 downto 0);
signal R_autofire : std_logic_vector(21 downto 0);
begin
-- game core uses inverted control logic
coin <= not btn_coin; -- insert coin
player_start <= not btn_player_start; -- select 1 or 2 players
buttons(1) <= not btn_right; -- Right
buttons(2) <= not btn_left; -- Left
buttons(3) <= not btn_barrier; -- Protection
G_not_autofire: if not C_autofire generate
buttons(0) <= not btn_fire; -- Fire
end generate;
G_yes_autofire: if C_autofire generate
process(clk)
begin
if rising_edge(clk) then
if btn_fire='1' then
R_autofire <= R_autofire-1;
else
R_autofire <= (others => '0');
end if;
end if;
end process;
buttons(0) <= not R_autofire(R_autofire'high);
end generate;
video: entity work.phoenix_video
port map
(
clk11 => clk,
ce_pix => ce_pix1,
hcnt => hcnt,
vcnt => vcnt,
sync_hs => video_hs,
sync_vs => video_vs,
adrsel => adrsel, -- RAM address selector ('0')cpu / ('1')video_generator
rdy => rdy, -- Ready ('1')cpu can access RAMs read/write
vblank => vblank,
hblank_frgrd => hblank_frgrd,
hblank_bkgrd => hblank_bkgrd,
reset => reset
);
reset_n <= not reset;
ce_pix <= ce_pix1;
-- microprocessor 8085
cpu8085 : entity work.T8080se
generic map
(
Mode => 2,
T2Write => 0
)
port map(
RESET_n => reset_n,
CLK => clk,
CLKEN => '1', -- fixme: use it to make 5.5 MHz clock average
READY => rdy,
HOLD => '1',
INT => '1',
INTE => open,
DBIN => open,
SYNC => open,
VAIT => open,
HLDA => open,
WR_n => cpu_wr_n,
A => cpu_adr,
DI => cpu_di,
DO => cpu_do
);
-- mux prog, ram, vblank, switch... to processor data bus in
cpu_di <= prog_do when cpu_adr(14) = '0' else
frgnd_ram_do when cpu_adr(13 downto 10) = 2#00_00# else
bkgnd_ram_do when cpu_adr(13 downto 10) = 2#00_10# else
buttons & '0' & player_start & coin when cpu_adr(13 downto 10) = 2#11_00# else--buttons & '1'
not vblank & dip_switch(6 downto 0) when cpu_adr(13 downto 10) = 2#11_10# else
prog_do;
-- write enable to RAMs from cpu
frgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10000" and adrsel = '0' else '0';
bkgnd_ram_we <= '1' when cpu_wr_n = '0' and cpu_adr(14 downto 10) = "10010" and adrsel = '0' else '0';
-- RAMs address mux cpu/video_generator, bank0 for player1, bank1 for player2
frgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & frgnd_horz_cnt(7 downto 3);
bkgnd_ram_adr <= player2 & cpu_adr(9 downto 0) when adrsel ='0' else player2 & vert_cnt(7 downto 3) & bkgnd_horz_cnt(7 downto 3);
-- demux cpu data to registers : background scrolling, sound control,
-- player id (1/2), palette color set.
process (clk)
begin
if rising_edge(clk) then
if cpu_wr_n = '0' then
case cpu_adr(14 downto 10) is
when "10110" => bkgnd_offset <= cpu_do;
when "11000" => sound_b <= cpu_do;
when "11010" => sound_a <= cpu_do;
when "10100" => player2 <= cpu_do(0);
color_set <= cpu_do(1);
color_set2 <= cpu_do(2);
A11 <= cpu_do(3);
when others => null;
end case;
end if;
end if;
end process;
-- player2 and cocktail mode (flip horizontal/vertical)
pl2_cocktail <= player2 and dip_switch(7);
-- horizontal scan video RAMs address background and foreground
-- with flip and scroll offset
frgnd_horz_cnt <= hcnt(8 downto 1) when pl2_cocktail = '0' else not hcnt(8 downto 1);
bkgnd_horz_cnt <= frgnd_horz_cnt + bkgnd_offset;
-- vertical scan video RAMs address
vert_cnt <= vcnt(8 downto 1) when pl2_cocktail = '0' else not (vcnt(8 downto 1) + X"30");
-- get tile_ids from RAMs
frgnd_tile_id <= frgnd_ram_do;
bkgnd_tile_id <= bkgnd_ram_do;
-- address graphix ROMs with tile_ids and line counter
frgnd_graph_adr <= A11 & frgnd_tile_id & vert_cnt(2 downto 0);
bkgnd_graph_adr <= A11 & bkgnd_tile_id & vert_cnt(2 downto 0);
-- latch foreground/background next graphix byte, high bit and low bit
-- and palette_ids (fr_lin, bklin)
process (clk)
begin
if rising_edge(clk) then
if (pl2_cocktail = '0' and (frgnd_horz_cnt(2 downto 0) = "111")) or
(pl2_cocktail = '1' and (frgnd_horz_cnt(2 downto 0) = "000")) then
frgnd_bit0_graph_r <= frgnd_bit0_graph;
frgnd_bit1_graph_r <= frgnd_bit1_graph;
fr_lin <= frgnd_tile_id(7 downto 5);
end if;
if (pl2_cocktail = '0' and (bkgnd_horz_cnt(2 downto 0) = "111")) or
(pl2_cocktail = '1' and (bkgnd_horz_cnt(2 downto 0) = "000")) then
bkgnd_bit0_graph_r <= bkgnd_bit0_graph;
bkgnd_bit1_graph_r <= bkgnd_bit1_graph;
bk_lin <= bkgnd_tile_id(7 downto 5);
end if;
end if;
end process;
-- demux background and foreground pixel bits (0/1) from graphix byte with horizontal counter
-- and apply horizontal and vertical blanking
fr_bit0 <= frgnd_bit0_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0';
fr_bit1 <= frgnd_bit1_graph_r(to_integer(unsigned(frgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_frgrd)= '0' else '0';
bk_bit0 <= bkgnd_bit0_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0';
bk_bit1 <= bkgnd_bit1_graph_r(to_integer(unsigned(bkgnd_horz_cnt(2 downto 0)))) when (vblank or hblank_bkgrd)= '0' else '0';
-- select pixel bits and palette_id with foreground priority
color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 or fr_bit1) = '1' else
(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
-- address palette with pixel bits color and color set
palette_adr <= color_set2 & color_set & color_id;
-- output video to top level
video_vblank <= vblank;
video_hblank_fg <= hblank_frgrd;
video_hblank_bg <= hblank_bkgrd;
video_r <= rgb_1(0) & rgb_0(0) when (hcnt>=192) else "00";
video_g <= rgb_1(2) & rgb_0(2) when (hcnt>=192) else "00";
video_b <= rgb_1(1) & rgb_0(1) when (hcnt>=192) else "00";
frgnd_bit0 : entity work.sprom
generic map (
init_file => "./ROM/39.hex",
widthad_a => 11,
width_a => 8)
port map (
address => frgnd_graph_adr(10 downto 0),
clock => clk,
q => frgnd_bit0_graph
);
frgnd_bit1 : entity work.sprom
generic map (
init_file => "./ROM/40.hex",
widthad_a => 11,
width_a => 8)
port map (
address => frgnd_graph_adr(10 downto 0),
clock => clk,
q => frgnd_bit1_graph
);
bkgnd_bit0 : entity work.sprom
generic map (
init_file => "./ROM/23.hex",
widthad_a => 11,
width_a => 8)
port map (
address => bkgnd_graph_adr(10 downto 0),
clock => clk,
q => bkgnd_bit0_graph
);
bkgnd_bit1 : entity work.sprom
generic map (
init_file => "./ROM/24.hex",
widthad_a => 11,
width_a => 8)
port map (
address => bkgnd_graph_adr(10 downto 0),
clock => clk,
q => bkgnd_bit1_graph
);
palette_0 : entity work.sprom
generic map (
init_file => "./ROM/ic40.hex",
widthad_a => 7,
width_a => 3)
port map (
address => palette_adr(6 downto 0),
clock => clk,
q => rgb_0
);
palette_1 : entity work.sprom
generic map (
init_file => "./ROM/ic41.hex",
widthad_a => 7,
width_a => 3)
port map (
address => palette_adr(6 downto 0),
clock => clk,
q => rgb_1
);
-- Program PROM
S_prog_rom_addr(C_prog_rom_addr_bits-1 downto 0) <= cpu_adr(C_prog_rom_addr_bits-1 downto 0);
prog : entity work.sprom
generic map (
init_file => "./ROM/prog.hex",
widthad_a => 14,
width_a => 8)
port map (
address => S_prog_rom_addr,
clock => clk,
q => prog_do
);
-- foreground RAM 0x4000-0x433F
-- cpu working area 0x4340-0x43FF
frgnd_ram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clk,
we => frgnd_ram_we,
addr => frgnd_ram_adr,
d => cpu_do,
q => frgnd_ram_do
);
-- background RAM 0x4800-0x4B3F
-- cpu working area 0x4B40-0x4BFF
-- stack pointer downward from 0x4BFF
bkgnd_ram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clk,
we => bkgnd_ram_we,
addr => bkgnd_ram_adr,
d => cpu_do,
q => bkgnd_ram_do
);
effect1: entity work.phoenix_effect1
port map
(
clk => clk,
reset => '0',
trigger => sound_a(4),
filter => sound_a(5),
divider => sound_a(3 downto 0),
snd => snd1
);
effect2 : entity work.phoenix_effect2
port map
(
clk => clk,
reset => '0',
trigger1 => sound_b(4),
trigger2 => sound_b(5),
divider => sound_b(3 downto 0),
snd => snd2
);
effect3 : entity work.phoenix_effect3
port map
(
clk => clk,
reset => '0',
trigger1 => sound_b(6),
trigger2 => sound_b(7),
snd => snd3
);
sound_burn <= sound_b(4);
sound_fire <= sound_b(6); -- '1' when fire sound
sound_explode <= sound_b(7); -- '1' when explode sound
sound_fireball <= sound_a(1) and not sound_a(0); -- ambiguity: mothership descend also triggers this
sound_ab <= sound_b & sound_a;
music: entity work.phoenix_music
port map
(
clk => clk,
reset => '0',
trigger => sound_a(7),
sel_song => sound_a(6),
snd => song
);
-- mix effects and music
mixed <= std_logic_vector
(
unsigned("00" & snd1 & "00") +
unsigned("0" & snd2 & "000000000") +
unsigned("00" & snd3 & "00") +
unsigned("00" & song & "00" )
);
-- select sound or/and effect
with audio_select select
audio <= "00" & snd1 & "00" when "100",
"0" & snd2 & "000000000" when "101",
"00" & snd3 & "00" when "110",
"00" & song & "00" when "111",
mixed when others;
end struct;

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@@ -0,0 +1,387 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c0 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 44,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_duty_cycle => 50,
clk1_multiply_by => 11,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "44.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "11.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "44.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "11.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/scandoubler.v → Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/scandoubler.v
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55
Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/spram.vhd Normal file
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@@ -0,0 +1,55 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

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Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/sprom.vhd Normal file
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/video_mixer.sv → Arcade_MiST/Phoenix Hardware/Capitol_MIST/rtl/video_mixer.sv
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0
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0
Arcade_MiST/Custom Hardware/Phoenix_MIST/README.txt → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/README.txt
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0
Arcade_MiST/Custom Hardware/Phoenix_MIST/Release/phoenix_mist.rbf → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/Release/phoenix_mist.rbf
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Arcade_MiST/Phoenix Hardware/Phoenix_MIST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/phoenix_mist.qpf → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qpf
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0
Arcade_MiST/Custom Hardware/Phoenix_MIST/phoenix_mist.qsf → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.qsf
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Arcade_MiST/Phoenix Hardware/Phoenix_MIST/phoenix_mist.sdc Normal file
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#************************************************************
# THIS IS A WIZARD-GENERATED FILE.
#
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
#
#************************************************************
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
# Clock constraints
create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/Phoenix_MiST.sv
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0
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Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_ic39.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/ROM/prom_ic39.vhd
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0
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0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic40.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic40.vhd
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0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic41.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/ROM/prom_palette_ic41.vhd
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--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

35
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/build_id.tcl Normal file
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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/build_id.v Normal file
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`define BUILD_DATE "190312"
`define BUILD_TIME "215035"

48
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/dac.vhd Normal file
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-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 12
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
qReg <= ram(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/greybox_tmp/cbx_args.txt → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/greybox_tmp/cbx_args.txt
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454
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/hq2x.sv Normal file
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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
`define BITS_TO_FIT(N) ( \
N <= 2 ? 0 : \
N <= 4 ? 1 : \
N <= 8 ? 2 : \
N <= 16 ? 3 : \
N <= 32 ? 4 : \
N <= 64 ? 5 : \
N <= 128 ? 6 : \
N <= 256 ? 7 : \
N <= 512 ? 8 : \
N <=1024 ? 9 : 10 )
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
wire [DWIDTH:0] out[2];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_out #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input [1:0] rdbuf,
output[DWIDTH:0] q,
input [AWIDTH:0] wraddr,
input [1:0] wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
wire [DWIDTH:0] out[4];
assign q = out[rdbuf];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output [DWIDTH:0] q
);
altsyncram altsyncram_component (
.address_a (wraddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.address_b (rdaddress),
.q_b(q),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({(DWIDTH+1){1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone III",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = NUMWORDS,
altsyncram_component.numwords_b = NUMWORDS,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = AWIDTH+1,
altsyncram_component.widthad_b = AWIDTH+1,
altsyncram_component.width_a = DWIDTH+1,
altsyncram_component.width_b = DWIDTH+1,
altsyncram_component.width_byteena_a = 1;
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [17:0] rgb1,
input [17:0] rgb2,
output result
);
wire [5:0] r = rgb1[5:1] - rgb2[5:1];
wire [5:0] g = rgb1[11:7] - rgb2[11:7];
wire [5:0] b = rgb1[17:13] - rgb2[17:13];
wire [6:0] t = $signed(r) + $signed(b);
wire [6:0] gx = {g[5], g};
wire [7:0] y = $signed(t) + $signed(gx);
wire [6:0] u = $signed(r) - $signed(b);
wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-24..24)
wire y_inside = (y < 8'h18 || y >= 8'he8);
// if u is inside (-4, 4)
wire u_inside = (u < 7'h4 || u >= 7'h7c);
// if v is inside (-6, 6)
wire v_inside = (v < 8'h6 || v >= 8'hfA);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [5:0] A,
input [5:0] B,
input [5:0] C,
output [5:0] O
);
function [8:0] mul6x3;
input [5:0] op1;
input [2:0] op2;
begin
mul6x3 = 9'd0;
if(op2[0]) mul6x3 = mul6x3 + op1;
if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [8:0] Amul = mul6x3(A, Op[7:5]);
wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
wire [8:0] At = Amul;
wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [9:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[9:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [17:0] E,
input [17:0] A,
input [17:0] B,
input [17:0] D,
input [17:0] F,
input [17:0] H,
output [17:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = 11'bx;
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [17:0] Input1 = E;
wire [17:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [17:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]);
InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]);
InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input [AWIDTH+1:0] read_x,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
localparam DWIDTH = HALF_DEPTH ? 8 : 17;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
reg [17:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] i;
reg [7:0] y;
wire curbuf = y[0];
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
wire [17:0] blend_result;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
reg Curr2_addr1;
reg [AWIDTH:0] Curr2_addr2;
wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
wire [DWIDTH:0] Curr2tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [17:0] h2rgb;
input [8:0] v;
begin
h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
end
endfunction
function [8:0] rgb2h;
input [17:0] v;
begin
rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(Curr2_addr2),
.rdbuf(Curr2_addr1),
.q(Curr2tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [1:0] wrout_addr1;
reg [AWIDTH+1:0] wrout_addr2;
reg wrout_en;
reg [DWIDTH:0] wrdata;
hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
(
.clk(clk),
.rdaddr(read_x),
.rdbuf(read_y),
.q(outpixel),
.wraddr(wrout_addr2),
.wrbuf(wrout_addr1),
.data(wrdata),
.wren(wrout_en)
);
always @(posedge clk) begin
reg [AWIDTH:0] offs;
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(~&offs) begin
if (i == 0) begin
Curr2_addr1 <= prevbuf;
Curr2_addr2 <= offs;
end
if (i == 1) begin
Prev2 <= Curr2;
Curr2_addr1 <= curbuf;
Curr2_addr2 <= offs;
end
if (i == 2) begin
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
if (i == 3) begin
offs <= offs + 1'd1;
end
if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
else wrdata <= blend_result;
wrout_addr1 <= {curbuf, i[1]};
wrout_addr2 <= {offs, i[1]^i[0]};
wrout_en <= 1;
end
if(i==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
i <= i + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
i <= 0;
y <= y + 1'd1;
prevbuf <= curbuf;
if(old_reset_frame & ~reset_frame) begin
y <= 0;
prevbuf <= 0;
end
end
old_reset_line <= reset_line;
end
end
endmodule // Hq2x

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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2015-2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
// output reg [31:0] joystick_2,
// output reg [31:0] joystick_3,
// output reg [31:0] joystick_4,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoublerD,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output [1:0] img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input [1:0] sd_rd,
input [1:0] sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ps2 alternative interface.
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
// ARM -> FPGA download
input ioctl_ce,
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg [1:0] mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoublerD = but_sw[4];
assign ypbpr = but_sw[5];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire drive_sel = sd_rd[1] | sd_wr[1];
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
reg [7:0] spi_data_out;
// SPI transmitter
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
reg [7:0] spi_data_in;
reg spi_data_ready = 0;
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
reg [6:0] sbuf;
reg [31:0] sd_lba_r;
reg drive_sel_r;
if(CONF_DATA0) begin
bit_cnt <= 0;
byte_cnt <= 0;
spi_data_out <= core_type;
end
else
begin
bit_cnt <= bit_cnt + 1'd1;
sbuf <= {sbuf[5:0], SPI_DI};
// finished reading command byte
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
spi_data_in <= {sbuf, SPI_DI};
spi_data_ready <= ~spi_data_ready;
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
spi_data_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_data_out <= sd_cmd;
sd_lba_r <= sd_lba;
drive_sel_r <= drive_sel;
end else if (byte_cnt == 1) begin
spi_data_out <= drive_sel_r;
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
// reading sd card write data
8'h18: spi_data_out <= sd_buff_din;
endcase
end
end
end
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
// transfer to clk_sys domain
always@(posedge clk_sys) begin
reg old_ss1, old_ss2;
reg old_ready1, old_ready2;
reg [2:0] b_wr;
reg got_ps2 = 0;
old_ss1 <= CONF_DATA0;
old_ss2 <= old_ss1;
old_ready1 <= spi_data_ready;
old_ready2 <= old_ready1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
if(old_ss2) begin
got_ps2 <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_buff_addr <= 0;
if(got_ps2) begin
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
end
end
else
if(old_ready2 ^ old_ready1) begin
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(byte_cnt < 2) begin
if (cmd == 8'h19) sd_ack_conf <= 1;
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
mount_strobe <= 0;
if(cmd == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_data_in;
8'h02: joystick_0 <= spi_data_in;
8'h03: joystick_1 <= spi_data_in;
// 8'h60: if (byte_cnt < 5) joystick_0[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h61: if (byte_cnt < 5) joystick_1[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h62: if (byte_cnt < 5) joystick_2[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h63: if (byte_cnt < 5) joystick_3[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// 8'h64: if (byte_cnt < 5) joystick_4[(byte_cnt-1)<<3 +:8] <= spi_data_in;
// store incoming ps2 mouse bytes
8'h04: begin
got_ps2 <= 1;
case(byte_cnt)
2: ps2_mouse[7:0] <= spi_data_in;
3: ps2_mouse[15:8] <= spi_data_in;
4: ps2_mouse[23:16] <= spi_data_in;
endcase
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
got_ps2 <= 1;
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_data_in;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_data_in;
b_wr <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
else if(byte_cnt == 3) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
end else if(byte_cnt == 4) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
end
end
// notify image selection
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
// send image info
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
// status, 32bit version
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
default: ;
endcase
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
reg rdownload = 0;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
case(ioctl_index[4:0])
1: addr <= 25'h200000; // TRD buffer at 2MB
2: addr <= 25'h400000; // tape buffer at 4MB
default: addr <= 25'h150000; // boot rom
endcase
rdownload <= 1;
end else begin
addr_w <= addr;
rdownload <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
addr <= addr + 1'd1;
rclk <= ~rclk;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
// transfer to ioctl_clk domain.
// ioctl_index is set before ioctl_download, so it's stable already
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
if(ioctl_ce) begin
ioctl_download <= rdownload;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD != rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
end
end
endmodule

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// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
input [1:0] rotate, //[0] - rotate [1] - left or right
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [10:0] osd_buffer_addr;
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
reg osd_pixel;
always @(posedge clk_sys) begin
if(ce_pix) begin
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
end
end
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

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Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/phoenix.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix.vhd
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---------------------------------------------------------------------------------
-- Phoenix sound effect1 by Dar (darfpga@aol.fr) (April 2016)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- this module generates sound how the birds fly
-- how they burn and the ship's barrier activation sound
-- it is most often heard module througut all levels of the game
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity phoenix_effect1 is
generic(
-- Command
Cmd_Fs: real := 11.0; -- MHz
Cmd_V: real := 12.0; -- V
Cmd_Vd: real := 0.46; -- V
Cmd_Vce: real := 0.2; -- V
Cmd_R1: real := 100.0; -- k
Cmd_R2: real := 33.0; -- k
Cmd_R3: real := 0.47; -- k
Cmd_C: real := 6.8; -- uF
Cmd_Div2n: integer := 8; -- bits divisor
Cmd_bits: integer := 16; -- bits counter
-- Oscillator
Osc_Fs: real := 11.0; -- MHz
Osc_Vb: real := 5.0; -- V
Osc_Vce: real := 0.2; -- V
Osc_R1: real := 47.0; -- k
Osc_R2: real := 47.0; -- k
Osc_C: real := 0.001; -- uF
Osc_Div2n: integer := 7; -- bits divisor
Osc_bits: integer := 6; -- bits counter
-- Filter
Filt_Fs: real := 11.0; -- MHz
Filt_V1: real := 5.0; -- V
Filt_V2: real := 0.0; -- V
Filt_R1: real := 100.0; -- k
Filt_R2: real := 10.0; -- k
Filt_C: real := 0.047; -- uF
Filt_Div2n: integer := 7; -- bits divisor
Filt_bits: integer := 8; -- bits counter
Vmax: real := 5.0; -- V
Vmax_bits: integer := 16 -- number of bits to represent vmax
);
port(
clk : in std_logic;
reset : in std_logic;
trigger : in std_logic;
filter : in std_logic;
divider : in std_logic_vector(3 downto 0);
snd : out std_logic_vector(7 downto 0)
);
end phoenix_effect1;
architecture struct of phoenix_effect1 is
-- integer representation of voltage, full range
constant IVmax: integer := integer(2**Vmax_bits)-1;
-- command --
constant Cmd_div: integer := integer(2**Cmd_Div2n);
-- command charge
constant Cmd_VFc: real := (Cmd_V*Cmd_R2 + Cmd_Vd*Cmd_R1)/(Cmd_R1 + Cmd_R2); -- V
constant Cmd_RCc: real := Cmd_R1*Cmd_R2/(Cmd_R1 + Cmd_R2)*Cmd_C/1000.0; -- s
constant Cmd_ikc: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCc / 2.0**Cmd_Div2n);
constant Cmd_iVFc: integer := integer(Cmd_VFc * real(IVmax)/Vmax);
-- command discharge
constant Cmd_VFd: real := (Cmd_V/Cmd_R1+Cmd_Vd/Cmd_R2+(Cmd_Vd+Cmd_Vce)/Cmd_R3)/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3); -- V
constant Cmd_RCd: real := 1.0/(1.0/Cmd_R1+1.0/Cmd_R2+1.0/Cmd_R3)*Cmd_C/1000.0; -- s
constant Cmd_ikd: integer := integer(Cmd_Fs * 1.0E6 * Cmd_RCd / 2.0**Cmd_Div2n);
constant Cmd_iVFd: integer := integer(Cmd_VFd * real(IVmax)/Vmax);
-- oscillator
constant Osc_div: integer := integer(2**Osc_Div2n);
-- oscillator charge
constant Osc_VFc: real := Osc_Vb; -- V
constant Osc_RCc: real := (Osc_R1+Osc_R2)*Osc_C/1000.0; -- s
constant Osc_ikc: integer := integer(Osc_Fs * 1.0E6 * Osc_RCc / 2.0**Osc_Div2n);
constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax);
-- oscillator discharge
constant Osc_VFd: real := Osc_Vce; -- V
constant Osc_RCd: real := Osc_R2*Osc_C/1000.0; -- s
constant Osc_ikd: integer := integer(Osc_Fs * 1.0E6 * Osc_RCd / 2.0**Osc_Div2n);
constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax);
-- filter
constant Filt_div: integer := integer(2**Filt_Div2n);
-- filter charge
constant Filt_VFc: real := Filt_V1; -- V
constant Filt_RCc: real := 1.0/(1.0/Filt_R1+1.0/Filt_R2)*Filt_C/1000.0; -- s
constant Filt_ikc: integer := integer(Filt_Fs * 1.0E6 * Filt_RCc / 2.0**Filt_Div2n);
constant Filt_iVFc: integer := integer(Filt_VFc * real(IVmax)/Vmax);
-- filter discharge
constant Filt_VFd: real := Filt_V2; -- V
constant Filt_RCd: real := Filt_RCc; -- s
constant Filt_ikd: integer := integer(Filt_Fs * 1.0E6 * Filt_RCd / 2.0**Filt_Div2n);
constant Filt_iVFd: integer := integer(Filt_VFd * real(IVmax)/Vmax);
function imax(x,y: integer) return integer is begin
if x > y then
return x;
else
return y;
end if;
end imax;
signal u_c1 : unsigned(15 downto 0) := (others => '0');
signal u_c2 : unsigned(15 downto 0) := (others => '0');
signal flip : std_logic := '0';
signal u_cf : unsigned(15 downto 0) := (others => '0');
signal sound : std_logic := '0';
begin
-- Commande
-- R1 = 100k, R2 = 33k, R3 = 0.47k C=6.8e-6 SR=10MHz
-- Charge : VF1 = 43559, k1 = 6591 (R1//R2)
-- Decharge : VF2 = 9300, k2 = 123 (R1//R2//R3)
-- Div = 2^8
process (clk)
variable cnt: integer range 0 to imax(Cmd_ikc,Cmd_ikd) := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c1 <= (others => '0');
else
cnt := cnt + 1;
if trigger = '1' then
if cnt = Cmd_ikc then
cnt := 0;
u_c1 <= u_c1 + (Cmd_iVFc - u_c1)/Cmd_div;
end if;
else
if cnt = Cmd_ikd then
cnt := 0;
u_c1 <= u_c1 - (u_c1 - Cmd_iVFd)/Cmd_div;
end if;
end if;
end if;
end if;
end process;
-- Oscillateur
-- R1 = 47k, R2 = 47k, C=0.001e-6 SR=50MHz
-- Charge : VF1 = 65535, k1 = 37 (R1+R2)
-- Decharge : VF2 = 2621, k2 = 18 (R2)
-- Div = 2^7
-- Diviseur
-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF)
-- LS74 : Divide by 2
process (clk)
variable cnt: integer range 0 to imax(Osc_ikc,Osc_ikd) := 0;
variable cnt2: unsigned(3 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c2 <= (others => '0');
flip <= '0';
else
if u_c2 > u_c1 then flip <= '0'; end if;
if u_c2 < u_c1/2 then
flip <= '1';
if flip = '0' then
cnt2 := cnt2 + 1;
if cnt2 = "0000" then
cnt2 := unsigned(divider);
if divider /= "1111" then sound <= not sound; end if;
end if;
end if;
end if;
cnt := cnt + 1;
if flip = '1' then
if cnt = Osc_ikc then
cnt := 0;
u_c2 <= u_c2 + (Osc_iVFc - u_c2)/Osc_div;
end if;
else
if cnt = Osc_ikd then
cnt := 0;
u_c2 <= u_c2 - (u_c2 - Osc_iVFd)/Osc_div;
end if;
end if;
end if;
end if;
end process;
-- filter
-- R1 = 10k, R2 = 100k, C=0.047e-6, SR=10MHz
-- Charge : VF1= 65535, k1 = 33 (R1//R2)
-- Decharge : VF2= 0 , k2 = 33 (R1//R2)
-- Div = 2^7
process (clk)
variable cnt: integer range 0 to imax(Filt_ikc,Filt_ikd) := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_cf <= (others => '0');
else
cnt := cnt + 1;
if sound = '1' then
if cnt = Filt_ikc then
cnt := 0;
u_cf <= u_cf + (Filt_iVFc - u_cf)/Filt_div;
end if;
else
if cnt = Filt_ikd then
cnt := 0;
u_cf <= u_cf - (u_cf - Filt_iVFd)/Filt_div;
end if;
end if;
end if;
end if;
end process;
with filter select snd <= std_logic_vector(u_cf(15 downto 8)) when '1', sound&"0000000" when others;
end struct;

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---------------------------------------------------------------------------------
-- Phoenix sound effect2 by Dar (darfpga@aol.fr) (April 2016)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- this module outputs sound of mothership's descend
-- it could be heard at beginning of level 5
-- the prrrrr...vioooouuuuu sound
-- fixme:
-- the VCO control levels are too coarse (quantized)
-- frequency transitions are heard in large steps
-- instead of continous sweep
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity phoenix_effect2 is
generic(
-- Oscillator 1
Osc1_Fs: real := 11.0; -- MHz
Osc1_Vb: real := 5.0; -- V
Osc1_Vce: real := 0.2; -- V
Osc1_R1: real := 47.0; -- k
Osc1_R2: real := 100.0; -- k
Osc1_C1: real := 0.01; -- uF
Osc1_C2: real := 0.47; -- uF
Osc1_C3: real := 1.0; -- uF
Osc1_Div2n: integer := 8; -- bits divisor
Osc1_bits: integer := 16; -- bits counter
-- Oscillator 2
Osc2_Fs: real := 11.0; -- MHz
Osc2_Vb: real := 5.0; -- V
Osc2_Vce: real := 0.2; -- V
Osc2_R1: real := 510.0; -- k
Osc2_R2: real := 510.0; -- k
Osc2_C: real := 1.0; -- uF
Osc2_Div2n: integer := 8; -- bits divisor
Osc2_bits: integer := 17; -- bits counter
-- Filter 2
Filt2_Fs: real := 11.0; -- MHz
Filt2_V: real := 5.0; -- V
Filt2_R1: real := 10.0; -- k
Filt2_R2: real := 5.1; -- k
Filt2_R3: real := 5.1; -- k
Filt2_R4: real := 5.0; -- k
Filt2_R5: real := 10.0; -- k
Filt2_C: real := 100.0; -- uF
Filt2_Div2n: integer := 8; -- bits divisor
Filt2_bits: integer := 16; -- bits counter
-- Oscillator 3
Osc3_Fs: real := 11.0; -- MHz
Osc3_Vb: real := 5.0; -- V
Osc3_Vce: real := 0.2; -- V
Osc3_R1: real := 20.0; -- k
Osc3_R2: real := 20.0; -- k
Osc3_C: real := 0.001; -- uF
Osc3_Div2n: integer := 6; -- bits divisor
Osc3_bits: integer := 6; -- bits counter
C_flip1_0: integer := 22020;
C_flip1_1: integer := 33063;
C_flip1_scale: integer := 84; -- ??
Vmax: real := 5.0; -- V
Vmax_bits: integer := 16 -- number of bits to represent Vmax
);
port(
clk : in std_logic;
reset : in std_logic;
trigger1 : in std_logic;
trigger2 : in std_logic;
divider : in std_logic_vector(3 downto 0);
snd : out std_logic_vector(1 downto 0)
);
end phoenix_effect2;
architecture struct of phoenix_effect2 is
function imax(x,y: integer) return integer is begin
if x > y then
return x;
else
return y;
end if;
end imax;
-- integer representation of voltage, full range
constant IVmax: integer := integer(2**Vmax_bits)-1;
-- Oscillator1 --
constant Osc1_div: integer := integer(2**Osc1_Div2n);
-- Oscillator1 charge/discharge voltages
constant Osc1_VFc: real := Osc1_Vb; -- V
constant Osc1_iVFc: integer := integer(Osc1_VFc * real(IVmax)/Vmax);
constant Osc1_VFd: real := Osc1_Vce; -- V
constant Osc1_iVFd: integer := integer(Osc1_VFd * real(IVmax)/Vmax);
-- Oscillator1 charge/discharge time constants
constant Osc1_T0_RCc: real := (Osc1_R1+Osc1_R2)*Osc1_C1/1000.0; -- s
constant Osc1_T0_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCc / 2.0**Osc1_Div2n);
constant Osc1_T0_RCd: real := Osc1_R2*Osc1_C1/1000.0; -- s
constant Osc1_T0_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T0_RCd / 2.0**Osc1_Div2n);
constant Osc1_T1_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2)/1000.0; -- s
constant Osc1_T1_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCc / 2.0**Osc1_Div2n);
constant Osc1_T1_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2)/1000.0; -- s
constant Osc1_T1_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T1_RCd / 2.0**Osc1_Div2n);
constant Osc1_T2_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C3)/1000.0; -- s
constant Osc1_T2_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCc / 2.0**Osc1_Div2n);
constant Osc1_T2_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C3)/1000.0; -- s
constant Osc1_T2_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T2_RCd / 2.0**Osc1_Div2n);
constant Osc1_T3_RCc: real := (Osc1_R1+Osc1_R2)*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s
constant Osc1_T3_ikc: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCc / 2.0**Osc1_Div2n);
constant Osc1_T3_RCd: real := Osc1_R2*(Osc1_C1+Osc1_C2+Osc1_C3)/1000.0; -- s
constant Osc1_T3_ikd: integer := integer(Osc1_Fs * 1.0E6 * Osc1_T3_RCd / 2.0**Osc1_Div2n);
constant Osc1_ik_max: integer := imax( imax(Osc1_T1_ikc,Osc1_T1_ikd), imax(Osc1_T3_ikc,Osc1_T3_ikd));
-- Oscillator2 --
constant Osc2_div: integer := integer(2**Osc2_Div2n);
-- Oscillator2 charge/discharge voltages
constant Osc2_VFc: real := Osc2_Vb; -- V
constant Osc2_iVFc: integer := integer(Osc2_VFc * real(IVmax)/Vmax);
constant Osc2_VFd: real := Osc2_Vce; -- V
constant Osc2_iVFd: integer := integer(Osc2_VFd * real(IVmax)/Vmax);
-- Oscillator2 charge/discharge time constants
constant Osc2_RCc: real := (Osc2_R1+Osc2_R2)*Osc2_C/1000.0; -- s
constant Osc2_ikc: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCc / 2.0**Osc2_Div2n);
constant Osc2_RCd: real := Osc2_R2*Osc2_C/1000.0; -- s
constant Osc2_ikd: integer := integer(Osc2_Fs * 1.0E6 * Osc2_RCd / 2.0**Osc2_Div2n);
-- Filter2 --
constant Filt2_div: integer := integer(2**Filt2_Div2n);
constant Filt2_R4p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R4); -- k
constant Filt2_R5p: real := 1.0/(1.0/Filt2_R1+1.0/Filt2_R5); -- k
constant Filt2_Rp: real := 1.0/(1.0/Filt2_R3+1.0/Filt2_R4+1.0/Filt2_R5p); -- k
constant Filt2_Rs: real := 1.0/(1.0/Filt2_R2+1.0/Filt2_R3-Filt2_Rp/(Filt2_R3**2)); -- k
constant Filt2_RC: real := Filt2_Rs*Filt2_C/1000.0; -- s
constant Filt2_ik: integer := integer(Filt2_Fs*1.0E6*Filt2_RC / 2.0**Filt2_Div2n);
-- Filter2 voltages
constant Filt2_V0: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4); -- V
constant Filt2_iV0: integer := integer(Filt2_V0 * real(IVmax)/Vmax);
constant Filt2_V1: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R4p*Filt2_R3); -- V
constant Filt2_iV1: integer := integer(Filt2_V1 * real(IVmax)/Vmax);
constant Filt2_V2: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4)+Filt2_V*Filt2_Rs/Filt2_R2; -- V
constant Filt2_iV2: integer := integer(Filt2_V2 * real(IVmax)/Vmax);
constant Filt2_V3: real := Filt2_V*Filt2_Rp*Filt2_Rs/(Filt2_R3*Filt2_R4p)+Filt2_V*Filt2_Rs/Filt2_R2; -- V
constant Filt2_iV3: integer := integer(Filt2_V3 * real(IVmax)/Vmax);
-- Oscillator3 --
constant Osc3_div: integer := integer(2**Osc3_Div2n);
-- Oscillator3 charge/discharge voltages
constant Osc3_VFc: real := Osc3_Vb; -- V
constant Osc3_iVFc: integer := integer(Osc3_VFc * real(IVmax)/Vmax);
constant Osc3_VFd: real := Osc3_Vce; -- V
constant Osc3_iVFd: integer := integer(Osc3_VFd * real(IVmax)/Vmax);
-- Oscillator3 charge/discharge time constants
constant Osc3_RCc: real := (Osc3_R1+Osc3_R2)*Osc3_C/1000.0; -- s
constant Osc3_ikc: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCc / 2.0**Osc3_Div2n);
constant Osc3_RCd: real := Osc3_R2*Osc3_C/1000.0; -- s
constant Osc3_ikd: integer := integer(Osc3_Fs * 1.0E6 * Osc3_RCd / 2.0**Osc3_Div2n);
signal u_c1 : unsigned(15 downto 0) := (others => '0');
signal u_c2 : unsigned(15 downto 0) := (others => '0');
signal u_c3 : unsigned(16 downto 0) := (others => '0');
signal flip1 : std_logic := '0';
signal flip2 : std_logic := '0';
signal flip3 : std_logic := '0';
signal triggers : std_logic_vector(1 downto 0) := "00";
--signal kc : unsigned(15 downto 0) := (others =>'0');
--signal kd : unsigned(15 downto 0) := (others =>'0');
signal kc : integer range 0 to Osc1_ik_max;
signal kd : integer range 0 to Osc1_ik_max;
signal u_cf : unsigned(15 downto 0) := (others => '0');
signal flips : std_logic_vector(1 downto 0) := "00";
signal vf : unsigned(15 downto 0) := (others =>'0');
signal u_cf_scaled : unsigned(23 downto 0) := (others => '0');
signal u_ctrl : unsigned(15 downto 0) := (others => '0');
signal sound: std_logic := '0';
begin
-- Oscillateur1
-- R1 = 47k, R2 = 100k, C1=0.01e-6, C2=0.047e-6, C3=1.000e-6 SR=10MHz
-- Div = 2^8
-- trigger = 00
-- Charge : VF1 = 65535, k1 = 57 (R1+R2, C1)
-- Decharge : VF2 = 2621, k2 = 39 (R2, C1)
-- trigger = 01
-- Charge : VF1 = 65535, k1 = 2756 (R1+R2, C1+C2)
-- Decharge : VF2 = 2621, k2 = 1875 (R2, C1+C2)
-- trigger = 10
-- Charge : VF1 = 65535, k1 = 5800 (R1+R2, C1+C3)
-- Decharge : VF2 = 2621, k2 = 3945 (R2, C1+C3)
-- trigger = 11
-- Charge : VF1 = 65535, k1 = 8498 (R1+R2, C1+C2+C3)
-- Decharge : VF2 = 2621, k2 = 5781 (R2, C1+C2+C3)
triggers <= trigger2 & trigger1;
with triggers select
kc <= Osc1_T0_ikc when "00",
Osc1_T1_ikc when "01",
Osc1_T2_ikc when "10",
Osc1_T3_ikc when others;
with triggers select
kd <= Osc1_T0_ikd when "00",
Osc1_T1_ikd when "01",
Osc1_T2_ikd when "10",
Osc1_T3_ikd when others;
process (clk)
variable cnt: integer range 0 to Osc1_ik_max := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c1 <= (others => '0');
else
if u_c1 > X"AAAA" then flip1 <= '0'; end if;
if u_c1 < X"5555" then flip1 <= '1'; end if;
cnt := cnt + 1;
if flip1 = '1' then
if cnt = kc then
cnt := 0;
u_c1 <= u_c1 + (Osc1_iVFc - u_c1)/Osc1_div;
end if;
else
if cnt = kd then
cnt := 0;
u_c1 <= u_c1 - (u_c1 - Osc1_iVFd)/Osc1_div;
end if;
end if;
end if;
end if;
end process;
-- Oscillateur2
-- R1 = 510k, R2 = 510k, C=1.000e-6, SR=10MHz
-- Charge : VF1 = 65535, k1 = 39844 (R1+R2, C)
-- Decharge : VF2 = 2621, k2 = 19922 (R2, C)
-- Div = 2^8
process (clk)
variable cnt: integer range 0 to imax(Osc2_ikc,Osc2_ikd) := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c2 <= (others => '0');
else
if u_c2 > X"AAAA" then flip2 <= '0'; end if;
if u_c2 < X"5555" then flip2 <= '1'; end if;
cnt := cnt + 1;
if flip2 = '1' then
if cnt = Osc2_ikc then
cnt := 0;
u_c2 <= u_c2 + (Osc2_iVFc - u_c2)/Osc2_div;
end if;
else
if cnt = Osc2_ikd then
cnt := 0;
u_c2 <= u_c2 - (u_c2 - Osc2_iVFd)/Osc2_div;
end if;
end if;
end if;
end if;
end process;
-- Filtre
-- V1 = 5V
-- R1 = 10k, R2 = 5.1k, R3 = 5.1k, R4 = 5k, R5 = 10k, C=100.0e-6, SR=10MHz
-- Rp = R3//R4//R4//R1 = 1.68k
-- Rs = 1/(1/R2 + 1/R3 - Rp/(R3*R3)) = 3.05k
-- k = 11922 (Rs*C)
-- Div = 2^8
-- VF00 = 13159 (V*Rp*Rs)/(R4*R3)
-- VF01 = 19738 (V*Rp*Rs)/(R4p*R3)
-- VF10 = 52377 (V*Rp*Rs)/(R4*R3) + V*Rs/R2
-- VF11 = 58957 (V*Rp*Rs)/(R4p*R3) + V*Rs/R2
flips <= flip2 & flip1;
with flips select
vf <= to_unsigned(Filt2_iV0,16) when "00",
to_unsigned(Filt2_iV1,16) when "01",
to_unsigned(Filt2_iV2,16) when "10",
to_unsigned(Filt2_iV3,16) when others;
process (clk)
variable cnt: integer range 0 to Filt2_ik := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_cf <= (others => '0');
else
cnt := cnt + 1;
if vf > u_cf then
if cnt = Filt2_ik then
cnt := 0;
u_cf <= u_cf + (vf - u_cf)/Filt2_div;
end if;
else
if cnt = Filt2_ik then
cnt := 0;
u_cf <= u_cf - (u_cf - vf)/Filt2_div;
end if;
end if;
end if;
end if;
end process;
-- U_CTRL
-- flip1 = 0 u_ctrl = 5V*Rp/R4 + u_cf*Rp/R3 # 22020 + u_cf*84/256
-- flip1 = 1 u_ctrl = 5V*Rp/R4p + u_cf*Rp/R3 # 33063 + u_cf*84/256
u_cf_scaled <= u_cf*to_unsigned(C_flip1_scale,8);
with flip1 select
u_ctrl <= to_unsigned(C_flip1_0,16)+u_cf_scaled(23 downto 8) when '0',
to_unsigned(C_flip1_1,16)+u_cf_scaled(23 downto 8) when others;
-- Oscillateur3
-- R1 = 20k, R2 = 20k, C=0.001e-6 SR=50MHz
-- Charge : VF1 = 65535, k1 = 31 (R1+R2)
-- Decharge : VF2 = 2621, k2 = 16 (R2)
-- Div = 2^6
-- Diviseur
-- LS163 : Count up, Sync load when 0xF (no toggle sound if divider = 0xF)
-- LS74 : Divide by 2
process (clk)
variable cnt: integer range 0 to imax(Osc3_ikc,Osc3_ikd) := 0;
variable cnt2: unsigned(3 downto 0) := (others => '0');
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c3 <= (others => '0');
flip3 <= '0';
else
if u_c3 > u_ctrl then flip3 <= '0'; end if;
if u_c3 < u_ctrl/2 then
flip3 <= '1';
if flip3 = '0' then
cnt2 := cnt2 + 1;
if cnt2 = "0000" then
cnt2 := unsigned(divider);
if divider /= "1111" then sound <= not sound; end if;
end if;
end if;
end if;
cnt := cnt + 1;
if flip3 = '1' then
if cnt = Osc3_ikc then
cnt := 0;
u_c3 <= u_c3 + (Osc3_iVFc - u_c3)/Osc3_div;
end if;
else
if cnt = Osc3_ikd then
cnt := 0;
u_c3 <= u_c3 - (u_c3 - Osc3_iVFd)/Osc3_div;
end if;
end if;
end if;
end if;
end process;
with trigger2 select snd <= '0'&sound when '1', sound&'0' when others;
end struct;

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---------------------------------------------------------------------------------
-- Phoenix sound effect3 (noise) by Dar (darfpga@aol.fr) (April 2016)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- this module generates noisy sound of ship missile shooting
-- ship explosions and enemy mothership explosion
-- it is often head throught all the levels of the game
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
entity phoenix_effect3 is
generic(
-- Command 1
Cmd1_Fs: real := 11.0; -- MHz
Cmd1_V: real := 5.0; -- V
Cmd1_Vd: real := 0.46; -- V
Cmd1_Vce: real := 0.2; -- V
Cmd1_R1: real := 1.0; -- k
Cmd1_R2: real := 0.33; -- k
Cmd1_R3: real := 20.0; -- k
Cmd1_C: real := 6.8; -- uF
Cmd1_Div2n: integer := 8; -- bits divisor
--Cmd1_bits: integer := 16; -- bits counter
-- Command 2
Cmd2_Fs: real := 11.0; -- MHz
Cmd2_V: real := 5.0; -- V
Cmd2_Vd: real := 0.46; -- V
Cmd2_Vce: real := 0.2; -- V
Cmd2_R1: real := 1.0; -- k
Cmd2_R2: real := 0.33; -- k
Cmd2_R3: real := 47.0; -- k
Cmd2_C: real := 6.8; -- uF
Cmd2_Div2n: integer := 8; -- bits divisor
--Cmd2_bits: integer := 16; -- bits counter
-- Oscillator
Osc_Fs: real := 11.0; -- MHz
Osc_Vb: real := 5.0; -- V
Osc_Vce: real := 0.2; -- V
Oscmin_R1a: real := 47.0; -- k
Oscmin_R2: real := 0.33; -- k
Oscmin_C: real := 0.05; -- uF
Oscmin_bits: integer := 16; -- bits counter
Oscmax_R1a: real := 2.553; -- k
Oscmax_R2: real := 1.0; -- k
Oscmax_C: real := 0.05; -- uF
Osc_Div2n: integer := 7; -- bits divisor
--Osc_bits: integer := 16; -- bits counter
C_commande2_chop_k: integer := 62500;
Vmax: real := 5.0; -- V
Vmax_bits: integer := 16 -- number of bits to represent Vmax
);
port(
clk : in std_logic;
reset : in std_logic;
trigger1 : in std_logic;
trigger2 : in std_logic;
snd : out std_logic_vector(7 downto 0)
);
end phoenix_effect3;
architecture struct of phoenix_effect3 is
-- integer representation of voltage, full range
constant IVmax: integer := integer(2**Vmax_bits)-1;
-- Command1 --
constant Cmd1_div: integer := integer(2**Cmd1_Div2n);
-- Command1 charge/discharge voltages
constant Cmd1_VFc: real := Cmd1_V-Cmd1_Vd; -- V
constant Cmd1_iVFc: integer := integer(Cmd1_VFc * real(IVmax)/Vmax);
constant Cmd1_VFd: real := Cmd1_Vce+Cmd1_Vd; -- V
constant Cmd1_iVFd: integer := integer(Cmd1_VFd * real(IVmax)/Vmax);
-- Command1 charge/discharge time constants
constant Cmd1_RCc: real := (Cmd1_R1+Cmd1_R2+Cmd1_R3)*Cmd1_C/1000.0; -- s
constant Cmd1_ikc: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCc / 2.0**Cmd1_Div2n);
constant Cmd1_RCd: real := Cmd1_R2*Cmd1_C/1000.0; -- s
constant Cmd1_ikd: integer := integer(Cmd1_Fs * 1.0E6 * Cmd1_RCd / 2.0**Cmd1_Div2n);
-- Command2 --
constant Cmd2_div: integer := integer(2**Cmd2_Div2n);
-- Command2 charge/discharge voltages
constant Cmd2_VFc: real := (Cmd2_V-Cmd2_Vd)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3); -- V
constant Cmd2_iVFc: integer := integer(Cmd2_VFc * real(IVmax)/Vmax);
constant Cmd2_VFd: real := 0.0; -- V
constant Cmd2_iVFd: integer := integer(Cmd2_VFd * real(IVmax)/Vmax);
-- Command2 charge/discharge time constants
constant Cmd2_RCc: real := (Cmd2_R1+Cmd2_R2)*Cmd2_R3/(Cmd2_R1+Cmd2_R2+Cmd2_R3)*Cmd2_C/1000.0; -- s
constant Cmd2_ikc: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCc / 2.0**Cmd2_Div2n);
constant Cmd2_RCd: real := Cmd2_R3*Cmd2_C/1000.0; -- s
constant Cmd2_ikd: integer := integer(Cmd2_Fs * 1.0E6 * Cmd2_RCd / 2.0**Cmd2_Div2n);
-- Oscillator --
constant Osc_div: integer := integer(2**Osc_Div2n);
-- Oscillator charge/discharge voltages
constant Osc_VFc: real := Osc_Vb; -- V
constant Osc_iVFc: integer := integer(Osc_VFc * real(IVmax)/Vmax);
constant Osc_VFd: real := Osc_Vce; -- V
constant Osc_iVFd: integer := integer(Osc_VFd * real(IVmax)/Vmax);
-- Oscillator min charge/discharge time constants
constant Oscmin_RCc: real := (Oscmin_R1a+Oscmin_R2)*Oscmin_C/1000.0; -- s
constant Oscmin_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCc / 2.0**Osc_Div2n);
constant Oscmin_RCd: real := Oscmin_R2*Oscmin_C/1000.0; -- s
constant Oscmin_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmin_RCd / 2.0**Osc_Div2n);
-- Oscillator max charge/discharge time constants
constant Oscmax_RCc: real := (Oscmax_R1a+Oscmax_R2)*Oscmax_C/1000.0; -- s
constant Oscmax_ikc: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCc / 2.0**Osc_Div2n);
constant Oscmax_RCd: real := Oscmax_R2*Oscmax_C/1000.0; -- s
constant Oscmax_ikd: integer := integer(Osc_Fs * 1.0E6 * Oscmax_RCd / 2.0**Osc_Div2n);
function imax(x,y: integer) return integer is begin
if x > y then
return x;
else
return y;
end if;
end imax;
signal u_c1 : unsigned(15 downto 0) := (others => '0');
signal u_c2 : unsigned(15 downto 0) := (others => '0');
signal u_c3 : unsigned(15 downto 0) := (others => '0');
signal flip3 : std_logic := '0';
signal k_ch : unsigned(25 downto 0) := (others =>'0');
signal u_ctrl1 : unsigned(15 downto 0) := (others => '0');
signal u_ctrl2 : unsigned(15 downto 0) := (others => '0');
signal u_ctrl1_f : unsigned( 7 downto 0) := (others => '0');
signal u_ctrl2_f : unsigned( 7 downto 0) := (others => '0');
signal sound : unsigned( 7 downto 0) := (others => '0');
signal shift_reg : std_logic_vector(17 downto 0) := (others => '0');
begin
-- Commande1
-- R1 = 1k, R2 = 0.33k, R3 = 20k C=6.8e-6 SR=10MHz
-- Charge : VF1 = 59507, k1 = 5666 (R1+R2+R3)
-- Decharge : VF2 = 8651, k2 = 88 (R2)
-- Div = 2^8
process (clk)
-- variable cnt : unsigned(15 downto 0) := (others => '0');
variable cnt: integer range 0 to imax(Cmd1_ikc,Cmd1_ikd)*2 := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c1 <= (others => '0');
else
cnt := cnt + 1;
if trigger1 = '1' then
-- if cnt > C_commande1_k1 then
if cnt > Cmd1_ikc then
cnt := 0;
-- u_c1 <= u_c1 + (C_commande1_VF1 - u_c1)/256;
u_c1 <= u_c1 + (Cmd1_iVFc - u_c1)/Cmd1_div;
end if;
else
-- if cnt > C_commande1_k2 then
if cnt > Cmd1_ikd then
cnt := 0;
-- u_c1 <= u_c1 - (u_c1 - C_commande1_VF2)/256;
u_c1 <= u_c1 - (u_c1 - Cmd1_iVFd)/Cmd1_div;
end if;
end if;
end if;
end if;
end process;
-- Commande2
-- R1 = 1k, R2 = 0.33k, R3 = 47k C=6.8e-6 SR=10MHz
-- Charge : VF1 = 57869, k1 = 344 (R1+R2)//R3
-- Decharge : VF2 = 0, k2 = 12484 (R3)
-- Div = 2^8
process (clk)
-- variable cnt : unsigned(15 downto 0) := (others => '0');
variable cnt: integer range 0 to imax(Cmd2_ikc,Cmd2_ikd)*2 := 0;
begin
if rising_edge(clk) then
if reset = '1' then
-- cnt := (others => '0');
cnt := 0;
u_c2 <= (others => '0');
else
cnt := cnt + 1;
if trigger2 = '1' then
-- if cnt > C_commande2_k1 then
if cnt > Cmd2_ikc then
-- cnt := (others => '0');
cnt := 0;
-- u_c2 <= u_c2 + (C_commande2_VF1 - u_c2)/256;
u_c2 <= u_c2 + (Cmd2_iVFc - u_c2)/Cmd2_div;
end if;
else
-- if cnt > C_commande2_k2 then
if cnt > Cmd2_ikd then
-- cnt := (others => '0');
cnt := 0;
-- u_c2 <= u_c2 - (u_c2 - C_commande2_VF2)/256;
u_c2 <= u_c2 - (u_c2 - Cmd2_iVFd)/Cmd2_div;
end if;
end if;
end if;
end if;
end process;
-- control voltage from command1 is R3 voltage (not u_c1 voltage)
with trigger1 select
-- u_ctrl1 <= (to_unsigned(C_commande1_VF1,16) - u_c1) when '1', (others=>'0') when others;
u_ctrl1 <= (to_unsigned(Cmd1_iVFc,16) - u_c1) when '1', (others=>'0') when others;
-- control voltage from command2 is u_c2 voltage
u_ctrl2 <= u_c2;
-- sum up and scaled both control voltages to vary R1 resistor of oscillator
-- k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(C_oscillateur_min_k1-C_oscillateur_max_k1,10)),15) + C_oscillateur_max_k1;
k_ch <= shift_right(((u_ctrl1/2 + u_ctrl2/2) * to_unsigned(Oscmin_ikc-Oscmax_ikc,10)),15) + Oscmax_ikc;
-- Oscillateur
-- R1 = 47k..2.533k, R2 = 1k, C=0.05e-6, SR=50MHz
-- Charge : VF1 = 65536, k_ch = 938..69 (R1+R2, C)
-- Decharge : VF2 = 2621, k2 = 20 (R2, C)
-- Div = 2^7
-- noise generator triggered by oscillator output
process (clk)
variable cnt: integer range 0 to imax(imax(Oscmin_ikc,Oscmin_ikd), imax(Oscmax_ikc,Oscmax_ikd))+256 := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
u_c3 <= (others => '0');
else
if u_c3 > X"AAAA" then flip3 <= '0'; end if;
if u_c3 < X"5555" then
flip3 <= '1';
if flip3 = '0' then
shift_reg <= shift_reg(16 downto 0) & not(shift_reg(17) xor shift_reg(16));
end if;
end if;
cnt := cnt + 1;
if flip3 = '1' then
if cnt > k_ch then
cnt := 0;
u_c3 <= u_c3 + (Osc_iVFc - u_c3)/Osc_div;
end if;
else
if cnt > Oscmax_ikd then
cnt := 0;
u_c3 <= u_c3 - (u_c3 - Osc_iVFd)/Osc_div;
end if;
end if;
end if;
end if;
end process;
-- modulated (chop) command1 voltage with noise generator output
with shift_reg(17) xor shift_reg(16) select
u_ctrl1_f <= u_ctrl1(15 downto 8)/2 when '0', (others => '0') when others;
-- modulated (chop) command2 voltage with noise generator output
-- and add 400Hz filter (raw sub-sampling)
-- f=10 MHz, k = 25000
process (clk)
variable cnt : unsigned(15 downto 0) := (others => '0');
begin
if rising_edge(clk) then
cnt := cnt + 1;
if cnt > C_commande2_chop_k then
cnt := (others => '0');
if (shift_reg(17) xor shift_reg(16)) = '0' then
u_ctrl2_f <= u_ctrl2(15 downto 8)/2;
else
u_ctrl2_f <= (others => '0');
end if;
end if;
end if;
end process;
-- mix modulated noises 1 and 2
sound <= u_ctrl1_f + u_ctrl2_f;
snd <= std_logic_vector(sound);
end struct;

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---------------------------------------------------------------------------------
-- DE2-35 Top level for Phoenix by Dar (darfpga@aol.fr) (April 2016)
-- http://darfpga.blogspot.fr
--
-- Main features
-- PS2 keyboard input
-- wm8731 sound output
-- NO board SRAM used
--
-- sw 0: on/off hdmi-audio
--
-- Board switch : ---- todo fixme switches note
-- 1 - 4 : dip switch
-- 0-1 : lives 3-6
-- 3-2 : bonus life 30K-60K
-- 4 : coin 1-2
-- 6-5 : unkonwn
-- 7 : upright-cocktail
-- 8 -10 : sound_select
-- 0XX : all mixed (normal)
-- 100 : sound1 only
-- 101 : sound2 only
-- 110 : sound3 only
-- 111 : melody only
-- Board key :
-- 0 : reset
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
entity phoenix_mist is
port
(
CLOCK_27 : in std_logic;
LED : out std_logic;
VGA_R : out std_logic_vector(5 downto 0);
VGA_G : out std_logic_vector(5 downto 0);
VGA_B : out std_logic_vector(5 downto 0);
VGA_HS : out std_logic;
VGA_VS : out std_logic;
SPI_SCK : in std_logic;
SPI_DI : in std_logic;
SPI_DO : out std_logic;
SPI_SS2 : in std_logic;
SPI_SS3 : in std_logic;
CONF_DATA0 : in std_logic;
AUDIO_L : out std_logic;
AUDIO_R : out std_logic
);
end;
architecture struct of phoenix_mist is
signal clk : std_logic;
signal clk_88m : std_logic;
signal reset : std_logic;
signal clock_stable : std_logic;
signal audio : std_logic_vector(11 downto 0);
signal video_r, video_g, video_b: std_logic_vector(1 downto 0);
signal vsync, hsync : std_logic;
signal dip_switch : std_logic_vector(7 downto 0);-- := (others => '0');
signal status : std_logic_vector(31 downto 0);
signal buttons : std_logic_vector(1 downto 0);
signal scandoubler_disable : std_logic;
signal ypbpr : std_logic;
signal ce_pix : std_logic;
signal scanlines : std_logic_vector(1 downto 0);
signal hq2x : std_logic;
signal coin : std_logic;
signal player_start : std_logic_vector(1 downto 0);
signal button_left, button_right, button_protect, button_fire: std_logic;
signal joy0 : std_logic_vector(7 downto 0);
signal joy1 : std_logic_vector(7 downto 0);
signal ps2Clk : std_logic;
signal ps2Data : std_logic;
signal kbd_joy : std_logic_vector(7 downto 0);
signal upjoyL : std_logic;
signal upjoyR : std_logic;
signal upjoyB : std_logic;
-- config string used by the io controller to fill the OSD
constant CONF_STR : string := "PHOENIX;;O4,Screen Direction,Upright,Normal;O67,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.1;";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
variable rval: std_logic_vector(1 to 8 * s'length);
variable p: integer;
variable c: integer;
begin
for i in ss'range loop
p := 8 * i;
c := character'pos(ss(i));
rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8));
end loop;
return rval;
end function;
component mist_io
generic ( STRLEN : integer := 0 );
port (
clk_sys :in std_logic;
SPI_SCK, CONF_DATA0, SPI_DI :in std_logic;
SPI_DO : out std_logic;
conf_str : in std_logic_vector(8*STRLEN-1 downto 0);
buttons : out std_logic_vector(1 downto 0);
joystick_0 : out std_logic_vector(7 downto 0);
joystick_1 : out std_logic_vector(7 downto 0);
status : out std_logic_vector(31 downto 0);
scandoubler_disable, ypbpr : out std_logic;
ps2_kbd_clk : out std_logic;
ps2_kbd_data : out std_logic
);
end component mist_io;
component video_mixer
generic ( LINE_LENGTH : integer := 352; HALF_DEPTH : integer := 1 );
port (
clk_sys, ce_pix, ce_pix_actual : in std_logic;
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
rotate : in std_logic_vector(1 downto 0);
R, G, B : in std_logic_vector(2 downto 0);
HSync, VSync, line_start, mono : in std_logic;
VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0);
VGA_VS, VGA_HS : out std_logic
);
end component video_mixer;
component keyboard
PORT(
clk : in std_logic;
reset : in std_logic;
ps2_kbd_clk : in std_logic;
ps2_kbd_data : in std_logic;
joystick : out std_logic_vector (7 downto 0)
);
end component;
begin
-- SWITCH 1: SWITCH 2: NUMBER OF SPACESHIPS:
-- --------- --------- ---------------------
-- OFF OFF 6
-- ON OFF 5
-- OFF ON 4
-- ON ON 3
-- FIRST FREE SECOND FREE
-- SWITCH 3: SWITCH 4: SHIP SCORE: SHIP SCORE:
-- --------- --------- ----------- -----------
-- OFF OFF 6,000 60,000
-- ON OFF 5,000 50,000
-- OFF ON 4,000 40,000
-- ON ON 3,000 30,000
--Cocktail,Factory,Factory,Factory,Bonus2,Bonus1,Ships2,Ships1
dip_switch <= "00001111";
mist_io_inst : mist_io
generic map (STRLEN => CONF_STR'length)
port map (
clk_sys => clk,
SPI_SCK => SPI_SCK,
CONF_DATA0 => CONF_DATA0,
SPI_DI => SPI_DI,
SPI_DO => SPI_DO,
conf_str => to_slv(CONF_STR),
buttons => buttons,
scandoubler_disable => scandoubler_disable,
ypbpr => ypbpr,
joystick_1 => joy1,
joystick_0 => joy0,
status => status,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data
);
--
-- Audio
--
u_dac1 : entity work.dac
port map(
clk_i => clk_88m,
res_n_i => not reset,
dac_i => audio,
dac_o => AUDIO_L
);
u_dac2 : entity work.dac
port map(
clk_i => clk_88m,
res_n_i => not reset,
dac_i => audio,
dac_o => AUDIO_R
);
pll: entity work.pll27
port map(
inclk0 => CLOCK_27,
c0 => clk_88m,
c1 => clk,
locked => clock_stable
);
reset <= status(0) or status(5) or buttons(1) or not clock_stable;
u_keyboard : keyboard
port map(
clk => clk,
reset => reset,
ps2_kbd_clk => ps2Clk,
ps2_kbd_data => ps2Data,
joystick => kbd_joy
);
process(clk_88m)
variable cnt: integer range 0 to 6000000 := 0;
begin
if rising_edge(clk_88m) then
if status(3 downto 1) /= "000" then
cnt := 0;
coin <= status(1);
player_start <= status(3 downto 2);
else
if cnt < 6000000 then
cnt := cnt + 1;
else
coin <= '0';
player_start <= "00";
end if;
end if;
end if;
end process;
upjoyB <= joy0(2) or joy1(2) when status(4) = '0' else joy0(0) or joy1(0);
upjoyL <= joy0(1) or joy1(1) or kbd_joy(6) when status(4) = '0' else joy0(2) or joy1(2) or kbd_joy(5);
upjoyR <= joy0(0) or joy1(0) or kbd_joy(7) when status(4) = '0' else joy0(3) or joy1(3) or kbd_joy(4);
phoenix : entity work.phoenix
port map
(
clk => clk,
reset => reset,
ce_pix => ce_pix,
dip_switch => dip_switch,
btn_coin => kbd_joy(3) or coin,--ESC
btn_player_start(0) => kbd_joy(1) or player_start(0),--1
btn_player_start(1) => kbd_joy(2) or player_start(1),--2
btn_left => upjoyL,
btn_right => upjoyR,
btn_barrier => upjoyB or kbd_joy(2),--TAB
btn_fire => joy0(4) or joy1(4) or kbd_joy(0),--space
video_r => video_r,
video_g => video_g,
video_b => video_b,
video_hs => hsync,
video_vs => vsync,
audio_select => "000",
audio => audio
);
scanlines(0) <= '1' when status(7 downto 6) = "10" else '0';
scanlines(1) <= '1' when status(7 downto 6) = "11" else '0';
hq2x <= '1' when status(7 downto 6) = "01" else '0';
vmixer : video_mixer
port map (
clk_sys => clk_88m,
ce_pix => ce_pix,
ce_pix_actual => ce_pix,
SPI_SCK => SPI_SCK,
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
rotate => '1' & not status(4),
scanlines => scanlines,
scandoubler_disable => scandoubler_disable,
hq2x => hq2x,
ypbpr => ypbpr,
ypbpr_full => '1',
R => video_r & video_r(1),
G => video_g & video_g(1),
B => video_b & video_b(1),
HSync => hsync,
VSync => vsync,
line_start => '0',
mono => '0',
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_VS => VGA_VS,
VGA_HS => VGA_HS
);
LED <= '1';
end struct;

241
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---------------------------------------------------------------------------------
-- Phoenix music by Dar (darfpga@aol.fr) (April 2016)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity phoenix_music is
generic(
C_clk_freq: real := 11.0 -- MHz
);
port(
clk : in std_logic;
reset : in std_logic;
trigger : in std_logic;
sel_song : in std_logic;
snd : out std_logic_vector(7 downto 0)
);
end phoenix_music;
architecture struct of phoenix_music is
constant C_voice_attack: integer := integer(230.0 * C_clk_freq); -- larger value is faster
constant C_song0_tempo: integer := integer(2200.0 * C_clk_freq); -- larger value is faster
constant C_song1_tempo: integer := integer(1700.0 * C_clk_freq); -- larger value is faster
constant C_voice_down_rate: integer := integer(4000.0 / C_clk_freq); -- larger value is slower
type voice_array is array (0 to 94) of integer range 0 to 127;
-- main voice1 (Jeux Interdits)
constant voice1 : voice_array := (
32,96,32,96,32,96,32,96,26,90,24,88,24,88,23,87,21,85,21,85,24,88,32,96,37,101,101,101,101,101,37,101,35,99,33,97,33,97,32,96,26,90,26,90,32,96,33,97,32,96,33,97,32,96,36,100,33,97,32,96,32,96,26,90,24,88,24,88,23,87,21,85,23,87,23,87,23,87,23,87,24,88,23,87,21,85,24,88,32,96,37,101,101,101,101);
-- accompagnement voice1
constant voice2 : voice_array := (
5,69,69,69,69,69,16,80,80,80,80,80,8,72,8,72,8,72,16,80,80,80,80,80,5,69,5,8,16,21,5,69,69,69,69,69,17,81,81,81,81,81,10,74,74,74,74,74,16,80,80,80,80,80,16,80,80,80,80,80,8,72,72,72,72,72,5,69,69,69,69,69,7,71,71,71,71,71,17,81,81,81,8,72,5,69,16,80,8,72,5,69,69,69,69);
-- voice1, voice2 and voice3 value description
-- bit3-bit0 : tone from 0(La/A) to 11(Sol/G#)
-- bit5-bit4 : octave from 0(220Hz)to 2(880Hz)
-- bit6 : 0 = strike (restart) the tone, 1 = don't strike (hold) the tone
type voice_array2 is array (0 to 45) of integer range 0 to 127;
-- main voice3 (La lettre a Elise)
constant voice3 : voice_array2 := (
37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,25,32,33,5,10,17,37,36,37,36,37,32,35,33,26,5,10,17,21,26,32,5,16,21,33,32,26,90);
type period_array is array (0 to 11) of integer range 0 to 65535;
-- Octave 220Hz @ 10MHz
constant tone_period : period_array := (
45455, -- ton 0 La (A )
42903, -- ton 1 La# (A#)
40495, -- ton 2 Si (B )
38223, -- ton 3 Do (C )
36077, -- ton 4 Do# (C#)
34052, -- ton 5 Re (D )
32141, -- ton 6 Re# (D#)
30337, -- ton 7 Mi (E )
28635, -- ton 8 Fa (F )
27027, -- ton 9 Fa# (F#)
25511, -- ton 10 Sol (G )
24079 -- ton 11 Sol# (G#)
);
signal tempo_period : integer range 0 to C_song0_tempo := C_song1_tempo; --0.19s @ 100kHz
signal voice1_tone : integer range 0 to 65535 := 0;
signal voice1_tone_div : integer range 0 to 65535 := 0;
signal voice1_code : unsigned(6 downto 0) := "0000000";
signal voice1_vol : unsigned(7 downto 0) := "00000000";
signal voice1_snd : std_logic := '0';
signal voice2_tone : integer range 0 to 65535 := 0;
signal voice2_tone_div : integer range 0 to 65535 := 0;
signal voice2_code : unsigned(6 downto 0) := "0000000";
signal voice2_vol : unsigned(7 downto 0) := "00000000";
signal voice2_snd : std_logic := '0';
signal snd1 : unsigned(7 downto 0) := "00000000";
signal snd2 : unsigned(7 downto 0) := "00000000";
signal trigger_r : std_logic := '0';
signal max_step : integer range 0 to 94 := 94;
signal sel_song_r: std_logic := '1';
begin
process (clk)
variable cnt : integer range 0 to 127 := 0;
variable step : integer range 0 to 94 := 94;
variable tempo : integer range 0 to C_song0_tempo := 0;
variable voice1_code_v : unsigned(6 downto 0) := "0000000";
variable voice2_code_v : unsigned(6 downto 0) := "0000000";
variable voice1_down_rate : integer range 0 to C_voice_down_rate := 0;
variable voice2_down_rate : integer range 0 to C_voice_down_rate := 0;
begin
if rising_edge(clk) then
trigger_r <= trigger;
if reset = '1' then
cnt := 0;
step := 94;
voice1_vol <= X"00";
voice2_vol <= X"00";
elsif trigger ='1' and trigger_r ='0' and step = 94 then -- restart music on edge trigger if not already playing
cnt := 0;
step := 0;
voice1_vol <= X"00";
voice2_vol <= X"00";
sel_song_r <= sel_song;
if sel_song = '1' then
max_step <= 94;
tempo_period <= C_song1_tempo;
else
max_step <= 46;
tempo_period <= C_song0_tempo;
end if;
else
cnt := cnt +1;
if cnt >= 100 then
cnt := 0;
tempo := tempo +1;
if tempo >= tempo_period then -- next beat
tempo := 0;
if step < max_step then -- if not end of music get next note
if sel_song_r = '1' then
voice1_code_v := to_unsigned(voice1(step),7);
voice2_code_v := to_unsigned(voice2(step),7);
else
voice1_code_v := to_unsigned(voice3(step),7);
voice2_code_v := to_unsigned(voice3(step),7);
end if;
voice1_code <= voice1_code_v;
voice2_code <= voice2_code_v;
step := step + 1;
else -- if end cut-off volume
voice1_vol <= X"00";
voice2_vol <= X"00";
step := 94;
end if;
end if;
if (step < 94) then -- if not end of music
-- manage voice1 volume
-- ramp up fast to xF0 at begining of beat when new strike
if (tempo < C_voice_attack) and (voice1_code_v(6)='0') then
if voice1_vol < X"F0" then voice1_vol <= voice1_vol + X"01"; end if;
voice1_down_rate := 0;
-- ramp down slowly after a while, down to x80
else
if voice1_vol > X"80" then
voice1_down_rate := voice1_down_rate+1;
if voice1_down_rate >= C_voice_down_rate then
voice1_down_rate := 0;
voice1_vol <= voice1_vol - X"01";
end if;
end if;
end if;
-- manage voice2 volume
if (tempo < C_voice_attack) and (voice2_code_v(6)='0') then
if voice2_vol < X"F0" then voice2_vol <= voice2_vol + X"01"; end if;
voice2_down_rate := 0;
else
if voice2_vol > X"80" then
voice2_down_rate := voice2_down_rate+1;
if voice2_down_rate >= C_voice_down_rate then
voice2_down_rate := 0;
voice2_vol <= voice2_vol - X"01";
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
-- get voice1 raw tone
voice1_tone <= tone_period(to_integer(voice1_code(3 downto 0)));
-- get voice1 tone w.r.t octave
with voice1_code(5 downto 4) select
voice1_tone_div <= voice1_tone when "00",
voice1_tone/2 when "01",
voice1_tone/4 when others;
-- generate voice1 frequency
voice1_frequency: process (clk)
variable cnt : integer range 0 to 65535 := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
else
cnt := cnt+1;
if cnt >= voice1_tone_div then
cnt := 0;
voice1_snd <= not voice1_snd;
end if;
end if;
end if;
end process;
-- get voice2 raw tone
voice2_tone <= tone_period(to_integer(voice2_code(3 downto 0)));
-- get voice2 tone w.r.t octave
with voice2_code(5 downto 4) select
voice2_tone_div <= voice2_tone when "00",
voice2_tone/2 when "01",
voice2_tone/4 when others;
-- generate voice2 frequency
voice2_frequency: process (clk)
variable cnt : integer range 0 to 65535 := 0;
begin
if rising_edge(clk) then
if reset = '1' then
cnt := 0;
else
cnt := cnt+1;
if cnt >= voice2_tone_div then
cnt := 0;
voice2_snd <= not voice2_snd;
end if;
end if;
end if;
end process;
-- modulate voice1 volume with voice1 frequency
with voice1_snd select snd1 <= voice1_vol when '1', X"00" when others;
-- modulate voice2 volume with voice2 frequency
with voice2_snd select snd2 <= voice2_vol when '1', X"00" when others;
-- mix voice1 and voice 2
snd <= std_logic_vector(('0'&snd1(7 downto 1)) + ('0'&snd2(7 downto 1)));
end struct;

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/phoenix_prog.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix_prog.vhd
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Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/phoenix_video.vhd Normal file
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---------------------------------------------------------------------------------
-- Phoenix video generator by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.all;
entity phoenix_video is
port(
clk11 : in std_logic;
reset : in std_logic;
ce_pix : out std_logic;
hcnt : out std_logic_vector(9 downto 1);
vcnt : out std_logic_vector(8 downto 1);
sync_hs : out std_logic;
sync_vs : out std_logic;
adrsel : out std_logic;
rdy : out std_logic;
vblank : out std_logic;
hblank_frgrd : out std_logic;
hblank_bkgrd : out std_logic
);
end phoenix_video;
architecture struct of phoenix_video is
signal hclk_i : std_logic := '0';
signal hstb_i : std_logic := '0';
signal hcnt_i : unsigned(9 downto 1) := (others=>'0');
signal vcnt_i : unsigned(9 downto 1) := (others=>'0');
signal vcnt2 : std_logic_vector(8 downto 1) := (others=>'0');
signal vblank_n : std_logic := '0';
signal rdy1_i : std_logic;
signal rdy2_i : std_logic;
signal j1 : std_logic;
signal k1 : std_logic;
signal q1 : std_logic;
signal j2 : std_logic;
signal k2 : std_logic;
signal q2 : std_logic;
begin
-- horizontal counter clock (pixel clock)
process(clk11) begin
if falling_edge(clk11) then
hclk_i <= not hclk_i;
end if;
end process;
-- horizontal counter from 0x0A0 to 0x1FF : 352 pixels
process(clk11) begin
if rising_edge(clk11) then
if hclk_i = '1' then
if reset = '1' then
hcnt_i <= (others=>'0');
vcnt_i <= (others=>'0');
else
hcnt_i <= hcnt_i +1;
if hcnt_i = 511 then
hcnt_i <= to_unsigned(160,9);
vcnt_i <= vcnt_i +1;
if vcnt_i = 261 then
vcnt_i <= to_unsigned(0,9);
end if;
end if;
end if;
end if;
end if;
end process;
-- vertical counter clock (line clock) = hblank
process(clk11) begin
if rising_edge(clk11) then
if hclk_i = '1' then
if (hcnt_i(3) and hcnt_i(2) and hcnt_i(1)) = '1' then hstb_i <= not hcnt_i(9); end if;
end if;
end if;
end process;
-- vertical blanking
vblank_n <=
not(vcnt2(8) and vcnt2(7))
or
( not
( not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and not vcnt2(4))
and
not (vcnt2(8) and vcnt2(7) and not vcnt2(6) and not vcnt2(5) and vcnt2(4))
)
);
-- ready signal for microprocessor
rdy1_i <= not( not(hcnt_i(9)) and not hcnt_i(7) and hcnt_i(6) and not hcnt_i(5));
rdy2_i <= not( not(hcnt_i(9)) and hcnt_i(7) and hcnt_i(6) and hcnt_i(5));
-- background horizontal blanking
j1 <= hcnt_i(6) and hcnt_i(4);
k1 <= hstb_i;
process(clk11) begin
if rising_edge(clk11) then
if hclk_i = '1' then
if (j1 xor k1) = '1' then
q1 <= j1;
elsif j1 = '1' then
q1 <= not q1;
else
q1 <= q1;
end if;
end if;
end if;
end process;
j2 <= not hcnt_i(6) and hcnt_i(5);
k2 <= hcnt_i(8) and hcnt_i(7) and hcnt_i(6) and hcnt_i(4);
process(clk11) begin
if rising_edge(clk11) then
if hclk_i = '1' then
if (j2 xor k2) = '1' then
q2 <= j2;
elsif j2 = '1' then
q2 <= not q2;
else
q2 <= q2;
end if;
end if;
end if;
end process;
-- output
ce_pix <= hclk_i;
hcnt <= std_logic_vector(hcnt_i);
vcnt2 <= std_logic_vector(vcnt_i(8 downto 1)) when vcnt_i < 255 else "11111111";
vcnt <= vcnt2;
--sync <= not(sync1_i xor sync2_i) ; original syncs
rdy <= not(vblank_n and (not (rdy1_i and rdy2_i and not hcnt_i(9))));
adrsel <= vblank_n and hcnt_i(9);
vblank <= not vblank_n;
hblank_frgrd <= hstb_i;
hblank_bkgrd <= not(hcnt_i(9) and q1) and not(hcnt_i(9) and (q2));
process(clk11) begin
if rising_edge(clk11) then
if hclk_i = '1' then
if hcnt_i = 191 then
sync_hs <= '1';
if vcnt_i = 230 then sync_vs <= '1'; end if;
if vcnt_i = 237 then sync_vs <= '0'; end if;
end if;
if hcnt_i = 217 then sync_hs <= '0'; end if;
end if;
end if;
end process;
end struct;

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Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.ppf Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="areset" direction="input" scope="external" />
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
</global>
</pinplan>

4
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

0
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/pll.vhd → Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/pll.vhd
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183
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/scandoubler.v Normal file
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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
input ce_pix_actual,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input line_start,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
assign vs_out = vs_in;
reg [2:0] phase;
reg [2:0] ce_div;
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4;
reg req_line_reset;
wire ls_in = hs_in | line_start;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x1 <= 0;
// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
phase <= phase + 1'd1;
ce_x4 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x4 <= 1;
pix_len <= 0;
phase <= phase + 1'd1;
ce_cnt <= ce_cnt + 1'd1;
if(ce_pix_actual) begin
phase <= 0;
ce_div <= ce_cnt + 1'd1;
ce_cnt <= 0;
req_line_reset <= 0;
end
if(ls_in) req_line_reset <= 1;
end
end
reg ce_sd;
always @(*) begin
case(ce_div)
2: ce_sd = !phase[0];
4: ce_sd = !phase[1:0];
default: ce_sd <= 1;
endcase
end
localparam AWIDTH = `BITS_TO_FIT(LENGTH);
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4 & ce_sd),
.inputpixel({b_in,g_in,r_in}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.read_x(sd_h_actual),
.outpixel({b_out,g_out,r_out})
);
reg [10:0] sd_h_actual;
always @(*) begin
case(ce_div)
2: sd_h_actual = sd_h[10:1];
4: sd_h_actual = sd_h[10:2];
default: sd_h_actual = sd_h;
endcase
end
reg [10:0] sd_h;
reg [1:0] sd_line;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise,hs_ls;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg hs, hs2, vs, ls;
if(ce_x1) begin
hs <= hs_in;
ls <= ls_in;
if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
hs_max <= {hcnt,1'b1};
hcnt <= 0;
if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
sd_h <= sd_h + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
if(sd_hcnt == hs_ls) sd_h <= 0;
if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1;
end
end
endmodule

243
Arcade_MiST/Phoenix Hardware/Phoenix_MIST/rtl/video_mixer.sv Normal file
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@@ -0,0 +1,243 @@
//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 3 bits per component
// For half depth 6 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 480,
parameter HALF_DEPTH = 1,
parameter OSD_COLOR = 3'd4,
parameter OSD_X_OFFSET = 10'd0,
parameter OSD_Y_OFFSET = 10'd0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
// Some systems have multiple resolutions.
// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
input ce_pix_actual,
// OSD SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoublerD,
// High quality 2x scaling
input hq2x,
// YPbPr always uses composite sync
input ypbpr,
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
input [1:0] rotate, //[0] - rotate [1] - left or right
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
// interlace sync. Positive pulses.
input HSync,
input VSync,
// Falling of this signal means start of informative part of line.
// It can be horizontal blank signal.
// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel
// before first informative pixel.
input line_start,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_VS,
output VGA_HS
);
localparam DWIDTH = HALF_DEPTH ? 2 : 5;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.r_in(R),
.g_in(G),
.b_in(B),
.hs_out(hs_sd),
.vs_out(vs_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoublerD ? R : R_sd);
wire [DWIDTH:0] gt = (scandoublerD ? G : G_sd);
wire [DWIDTH:0] bt = (scandoublerD ? B : B_sd);
generate
if(HALF_DEPTH) begin
wire [5:0] r = mono ? {gt,rt} : {rt,rt};
wire [5:0] g = mono ? {gt,rt} : {gt,gt};
wire [5:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [5:0] r = rt;
wire [5:0] g = gt;
wire [5:0] b = bt;
end
endgenerate
wire hs = (scandoublerD ? HSync : hs_sd);
wire vs = (scandoublerD ? VSync : vs_sd);
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire [5:0] r_out, g_out, b_out;
always @(*) begin
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
end
2: begin // reduce 50% = 1/2
r_out = {1'b0, r[5:1]};
g_out = {1'b0, g[5:1]};
b_out = {1'b0, b[5:1]};
end
3: begin // reduce 75% = 1/4
r_out = {2'b00, r[5:2]};
g_out = {2'b00, g[5:2]};
b_out = {2'b00, b[5:2]};
end
default: begin
r_out = r;
g_out = g;
b_out = b;
end
endcase
end
wire [5:0] red, green, blue;
osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
(
.*,
.R_in(r_out),
.G_in(g_out),
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.rotate(rotate),
.R_out(red),
.G_out(green),
.B_out(blue)
);
wire [5:0] yuv_full[225] = '{
6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
6'd63
};
// http://marsee101.blog19.fc2.com/blog-entry-2311.html
// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B)
// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B)
wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red;
assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green;
assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue;
assign VGA_VS = (scandoublerD | ypbpr) ? 1'b1 : ~vs_sd;
assign VGA_HS = scandoublerD ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
endmodule

8
Arcade_MiST/README.txt
View File

@@ -20,7 +20,6 @@ Aviable Arcade Cores
Crazy Climber
Crazy Kong
Galaga
Phoenix
#Data East Burger Time Hardware
#Setup 1
@@ -36,12 +35,15 @@ Aviable Arcade Cores
Black Hole
Catacomb
Galaxian
King & Balloon
Moon Cresta
Mr. Do´s Nightmare
Omega
Orbitron
Pisces
Triple Draw Poker
War of Bugs
Zig Zag
#Irem M52 Hardware
Moon Patrol
@@ -91,6 +93,10 @@ Aviable Arcade Cores
Van Van Car
Woodpecker
#Phoenix Hardware
Capitol
Phoenix
#Scramble Hardware
Amidar
Frogger