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Z80-CTC: update with fixes needed for Playcity addon on Amstrad CPC

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This commit is contained in:
Gyorgy Szombathelyi
2020-07-11 23:50:56 +02:00
parent c4cf5c58fb
commit 8af64d7390
3 changed files with 24 additions and 11 deletions
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19
common/IO/Z80CTC/ctc_counter.vhd
View File

@@ -41,6 +41,7 @@ architecture struct of ctc_counter is
signal clk_trg_in : std_logic;
signal clk_trg_r : std_logic;
signal trigger : std_logic;
signal trigger_clk : std_logic;
signal count_ena : std_logic;
signal load_data_r : std_logic; -- make sure load_data toggles to get one new data
@@ -52,7 +53,6 @@ prescale_max <=
X"FF"; -- timer mode prescale 256
clk_trg_in <= clk_trg xor control_word(4);
trigger <= '1' when clk_trg_in = '0' and clk_trg_r = '1' else '0';
d_out <= count_in(7 downto 0);
@@ -74,8 +74,11 @@ begin
else
if rising_edge(clock) then
if clock_ena = '1' then
clk_trg_r <= clk_trg_in;
trigger <= '0';
trigger_clk <= '0';
if trigger_clk = '0' and trigger = '1' then
trigger_clk <= '1';
end if;
load_data_r <= load_data;
if (restart_on_next_trigger = '1' and trigger = '1') or (restart_on_next_clock = '1') then
@@ -128,7 +131,7 @@ begin
-- counter
zc_to_in <= '0';
if ((control_word(6) = '1' and trigger = '1' ) or
if ((control_word(6) = '1' and trigger_clk = '0' and trigger = '1') or -- rising edge of trigger_clk
(control_word(6) = '0' and count_ena = '1') ) and time_constant_loaded = '1' then
if prescale_in = 0 then
prescale_in <= prescale_max;
@@ -144,6 +147,14 @@ begin
end if;
end if;
-- detecting of trg input is asynchronous,
-- but eventually it's synchronized to the timer clock (clock_ena) via trigger_clk
clk_trg_r <= clk_trg_in;
if clk_trg_in = '0' and clk_trg_r = '1' then
trigger <= '1';
end if;
end if;
end if;
end process;

1
common/IO/Z80CTC/z80ctc.qip
View File

@@ -1,4 +1,3 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) z80ctc_top.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ctc_controler.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) ctc_counter.vhd ]
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) z80ctc_top.vhd ]

15
common/IO/Z80CTC/z80ctc_top.vhd
View File

@@ -37,6 +37,7 @@ end z80ctc_top;
architecture struct of z80ctc_top is
signal cpu_int_ack_n : std_logic;
signal ctc_int_n : std_logic;
signal ctc_controler_we : std_logic;
signal ctc_controler_do : std_logic_vector(7 downto 0);
@@ -87,13 +88,15 @@ ctc_counter_1_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n
ctc_counter_2_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "10" else '0';
ctc_counter_3_we <= '1' when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '1' and cs = "11" else '0';
dout <= ctc_controler_do when cpu_int_ack_n = '0' else
ctc_counter_0_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "00" else
ctc_counter_1_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "01" else
ctc_counter_2_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "10" else
ctc_counter_3_do when iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "11" else
dout <= ctc_controler_do when cpu_int_ack_n = '0' and ctc_int_n = '0' else
ctc_counter_0_do when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "00" else
ctc_counter_1_do when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "01" else
ctc_counter_2_do when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "10" else
ctc_counter_3_do when ce_n = '0' and iorq_n = '0' and m1_n = '1' and rd_n = '0' and cs = "11" else
x"FF";
int_n <= ctc_int_n;
-- CTC interrupt controler Z80-CTC (MK3882)
ctc_controler : entity work.ctc_controler
port map(
@@ -112,7 +115,7 @@ port map(
int_pulse_3 => ctc_counter_3_int,
d_out => ctc_controler_do,
int_n => int_n
int_n => ctc_int_n
);
ctc_counter_0 : entity work.ctc_counter