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Nichibutsu Galivan: new port

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...more like a rewrite than a port
This commit is contained in:
Gyorgy Szombathelyi 2022-10-09 18:15:18 +02:00
parent de3d5e339d
commit 8f6cf4a669
18 changed files with 3556 additions and 0 deletions
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31
Arcade_MiST/Nichibutsu Galivan Hardware/Galivan.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 00:21:03 December 03, 2019
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "00:21:03 December 03, 2019"
# Revisions
PROJECT_REVISION = "Galivan"

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Arcade_MiST/Nichibutsu Galivan Hardware/Galivan.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 19:54:12 November 22, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Galivan_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY Galivan_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/cpu.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ------------------------------
# start ENTITY(Galivan_MiST)
# Pin & Location Assignments
# ==========================
# Fitter Assignments
# ==================
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(Galivan_MiST)
# ----------------------------
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VERILOG_MACRO "EXT_ROM=<None>"
set_global_assignment -name FORCE_SYNCH_CLEAR ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galivan_MiST.sv
set_global_assignment -name QIP_FILE rtl/pll_mist.qip
set_global_assignment -name VERILOG_FILE rtl/video.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/spram.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/gfx.v
set_global_assignment -name VERILOG_FILE rtl/dpram.v
set_global_assignment -name VERILOG_FILE rtl/core.v
set_global_assignment -name VERILOG_FILE rtl/clk_en.v
set_global_assignment -name VERILOG_FILE rtl/build_id.v
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../common/Sound/jtopl/jt26.qip
set_global_assignment -name QIP_FILE ../../common/CPU/T80/T80.qip
set_global_assignment -name SIGNALTAP_FILE output_files/cpu.stp
set_global_assignment -name SIGNALTAP_FILE output_files/spri.stp
set_global_assignment -name SIGNALTAP_FILE output_files/tx.stp
set_global_assignment -name SIGNALTAP_FILE output_files/sh.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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Arcade_MiST/Nichibutsu Galivan Hardware/LICENSE Normal file
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GNU GENERAL PUBLIC LICENSE
Version 2, June 1991
Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Everyone is permitted to copy and distribute verbatim copies
of this license document, but changing it is not allowed.
Preamble
The licenses for most software are designed to take away your
freedom to share and change it. By contrast, the GNU General Public
License is intended to guarantee your freedom to share and change free
software--to make sure the software is free for all its users. This
General Public License applies to most of the Free Software
Foundation's software and to any other program whose authors commit to
using it. (Some other Free Software Foundation software is covered by
the GNU Lesser General Public License instead.) You can apply it to
your programs, too.
When we speak of free software, we are referring to freedom, not
price. Our General Public Licenses are designed to make sure that you
have the freedom to distribute copies of free software (and charge for
this service if you wish), that you receive source code or can get it
if you want it, that you can change the software or use pieces of it
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How to Apply These Terms to Your New Programs
If you develop a new program, and you want it to be of the greatest
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<one line to give the program's name and a brief idea of what it does.>
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with this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
Also add information on how to contact you by electronic and paper mail.
If the program is interactive, make it output a short notice like this
when it starts in an interactive mode:
Gnomovision version 69, Copyright (C) year name of author
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
This is free software, and you are welcome to redistribute it
under certain conditions; type `show c' for details.
The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, the commands you use may
be called something other than `show w' and `show c'; they could even be
mouse-clicks or menu items--whatever suits your program.
You should also get your employer (if you work as a programmer) or your
school, if any, to sign a "copyright disclaimer" for the program, if
necessary. Here is a sample; alter the names:
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
`Gnomovision' (which makes passes at compilers) written by James Hacker.
<signature of Ty Coon>, 1 April 1989
Ty Coon, President of Vice
This General Public License does not permit incorporating your program into
proprietary programs. If your program is a subroutine library, you may
consider it more useful to permit linking proprietary applications with the
library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License.

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# Cosmo Police Galivan & UFO Robo Dangar
This core is an emulation of the GV-1412 PCB from Nichibutsu originally by [Pierco](https://github.com/pcornier). Two games are supported: Cosmo Police Galivan & UFO Robo Dangar. Use a vertically oriented CRT for the best gaming experience!
SDRAM controller/gfx layers rewrite by Gyorgy Szombathelyi

98
Arcade_MiST/Nichibutsu Galivan Hardware/meta/Cosmo Police Galivan (12-26-1985).mra Normal file
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<misterromdescription>
<name>Cosmo Police Galivan (12/26/1985)</name>
<region></region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series></series>
<year>1985</year>
<manufacturer>Nichibutsu</manufacturer>
<category>Platform</category>
<setname>galivan</setname>
<mameversion>0246</mameversion>
<rbf>galivan</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>8-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<buttons names="Start 1P, Start 2P, A, B, Y, Coin A, Coin B" default="Start,Select,A,B,Y,R2,L2"></buttons>
<switches default="30,0e" base="16" page_id="1" page_name="Switches">
<dip bits="0,1" name="Lives" ids="2,3,4,5"/>
<dip bits="2,3" name="Bonus Life" ids="20k/60k,50k/60k,20k/90k,50k/90k"/>
<dip bits="4" name="Demo Sounds" ids="On,Off"/>
<dip bits="5" name="Cabinet" ids="Upright,Cocktail"/>
<dip bits="6" name="Power Invulnerability" ids="No,Yes"/>
<dip bits="7" name="Life Invulnerability" ids="No,Yes"/>
<dip bits="8,9" name="CoinA" ids="2C/1C,1C/1C,1C/2C,Free Play"/>
<dip bits="10,11" name="CoinB" ids="3C/1C,2C/3C,1C/3C,1C/6C"/>
<dip bits="12" name="Difficulty" ids="Easy,Hard"/>
<dip bits="13" name="Flip Screen" ids="Off,On"/>
</switches>
<rom index="0" zip="galivan.zip" md5="none">
<!-- main cpu -->
<part name="1.1b" crc="1e66b3f8"/>
<part name="2.3b" crc="a45964f1"/>
<part name="gv3.4b" crc="82f0c5e6"/>
<!-- audio cpu -->
<part name="gv11.14b" crc="05f1a0e3"/>
<part name="gv12.15b" crc="5b7a0d6d"/>
<!-- gfx1 - chars -->
<part name="gv4.13d" crc="162490b4"/>
<!-- gfx2 - tiles -->
<part name="gv7.14f" crc="eaa1a0db"/>
<part name="gv8.15f" crc="f174a41e"/>
<part name="gv9.17f" crc="edc60f5d"/>
<part name="gv10.19f" crc="41f27fca"/>
<!-- gfx3 - sprites -->
<part name="gv14.4f" crc="03e2229f"/>
<part name="gv13.1f" crc="bca9e66b"/>
<!-- gfx4 - bg tilemaps -->
<part name="gv6.19d" crc="da38168b"/>
<part name="gv5.17d" crc="22492d2a"/>
<!-- proms -->
<part name="mb7114e.9f" crc="de782b3e"/>
<part name="mb7114e.10f" crc="0ae2a857"/>
<part name="mb7114e.11f" crc="7ba8b9d1"/>
<part name="mb7114e.2d" crc="75466109"/>
<!-- user1 - sprite palette bank -->
<part name="mb7114e.7f" crc="06538736"/>
</rom>
<rom index="1">
</rom>
<rom index="2">
</rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<mratimestamp>202108231828</mratimestamp>
</misterromdescription>

99
Arcade_MiST/Nichibutsu Galivan Hardware/meta/Ufo Robo Dangar (4-07-1987).mra Normal file
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<misterromdescription>
<name>Ufo Robo Dangar (4/07/1987)</name>
<region></region>
<homebrew>no</homebrew>
<bootleg>no</bootleg>
<version></version>
<alternative></alternative>
<platform></platform>
<series></series>
<year>1985</year>
<manufacturer>Nichibutsu</manufacturer>
<category>Platform</category>
<setname>dangar</setname>
<mameversion>0246</mameversion>
<rbf>galivan</rbf>
<about></about>
<resolution>15kHz</resolution>
<rotation>vertical</rotation>
<flip></flip>
<players>2</players>
<joystick>8-way</joystick>
<special_controls></special_controls>
<num_buttons>3</num_buttons>
<buttons names="Start 1P, Start 2P, A, B, Y, Coin A, Coin B" default="Start,Select,A,B,Y,R2,L2"></buttons>
<switches default="30,0e" base="16" page_id="1" page_name="Switches">
<dip bits="0,1" name="Lives" ids="2,3,4,5"/>
<dip bits="2,3" name="Bonus Life" ids="20k/60k,50k/60k,20k/90k,50k/90k"/>
<dip bits="4" name="Demo Sounds" ids="On,Off"/>
<dip bits="5" name="Cabinet" ids="Cocktail,Upright"/>
<dip bits="6" name="Power Invulnerability" ids="No,Yes"/>
<dip bits="7" name="Alternate Enemies" ids="Off,On"/>
<dip bits="8,9" name="CoinA" ids="2C/1C,1C/1C,1C/2C,Free Play"/>
<dip bits="10,11" name="CoinB" ids="2C/1C,1C/1C,2C/3C,1C/2C"/>
<dip bits="12" name="Difficulty" ids="Hard,Easy"/>
<dip bits="13" name="Flip Screen" ids="Off,On"/>
<dip bits="14,15" name="Allow Continue" ids="No,3 Times,5 Times,99 Times"/>
</switches>
<rom index="0" zip="dangar.zip" md5="none">
<!-- main cpu -->
<part name="8.1b" crc="fe4a3fd6"/>
<part name="9.3b" crc="809d280f"/>
<part name="10.4b" crc="99a3591b"/>
<!-- audio cpu -->
<part name="13.b14" crc="3e041873"/>
<part name="14.b15" crc="488e3463"/>
<!-- gfx1 - chars -->
<part name="5.13d" crc="40cb378a"/>
<!-- gfx2 - tiles -->
<part name="1.14f" crc="d59ed1f1"/>
<part name="2.15f" crc="dfdb931c"/>
<part name="3.17f" crc="6954e8c3"/>
<part name="4.19f" crc="4af6a8bf"/>
<!-- gfx3 - sprites -->
<part name="12.4f" crc="55711884"/>
<part name="11.1f" crc="8cf11419"/>
<!-- gfx4 - bg tilemaps -->
<part name="7.19d" crc="6dba32cf"/>
<part name="6.17d" crc="6c899071"/>
<!-- proms -->
<part name="82s129.9f" crc="b29f6a07"/>
<part name="82s129.10f" crc="c6de5ecb"/>
<part name="82s129.11f" crc="a5bbd6dc"/>
<part name="82s129.2d" crc="a4ac95a5"/>
<!-- user1 - sprite palette bank -->
<part name="82s129.7f" crc="29bc6216"/>
</rom>
<rom index="1">
</rom>
<rom index="2">
</rom>
<rom_3></rom_3>
<rom_4></rom_4>
<nvram></nvram>
<remark></remark>
<mratimestamp>202108231828</mratimestamp>
</misterromdescription>

348
Arcade_MiST/Nichibutsu Galivan Hardware/rtl/Galivan_MiST.sv Normal file
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module Galivan_MiST (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"GALIVAN;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"O6,Joystick Swap,Off,On;",
"O8,Test mode,Off,On;",
"O1,Pause,Off,On;",
"DIP;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire pause = status[1];
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire service = status[8];
wire flip;
wire [1:0] orientation = {flip, 1'b1};
wire [7:0] j1 = ~{ m_fire1[2], 1'b0, m_fire1[1], m_fire1[0], m_right1, m_left1, m_down1, m_up1 };
wire [7:0] j2 = ~{ m_fire2[2], 1'b0, m_fire2[1], m_fire2[0], m_right2, m_left2, m_down2, m_up2 };
wire [7:0] p1 = ~status[23:16]; // dsw1
wire [7:0] p2 = ~status[31:24]; // dsw2
wire [7:0] system = ~{ 3'b000, service, m_coin2, m_coin1, m_two_players, m_one_player };
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_ram;
assign SDRAM_CKE = 1;
wire clk_sys, clk_ram, pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.c0(clk_ram),
.c1(clk_sys),
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [19:0] joystick_0;
wire [19:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire [6:0] core_mod;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.core_mod (core_mod ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire [15:0] cpu1_rom_addr;
wire [15:0] cpu1_rom_do;
wire cpu1_rom_cs;
wire cpu1_rom_valid;
wire [15:0] cpu2_rom_addr;
wire [15:0] cpu2_rom_do;
wire cpu2_rom_cs;
wire cpu2_rom_valid;
wire [13:0] gfx1_rom_addr;
wire [15:0] gfx1_rom_do;
wire [16:0] gfx2_rom_addr;
wire [15:0] gfx2_rom_do;
wire [15:0] gfx3_rom_addr;
wire [15:0] gfx3_rom_do;
wire gfx3_rom_ready;
wire ioctl_downl;
wire ioctl_upl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_din;
wire [7:0] ioctl_dout;
data_io data_io(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.SPI_DO ( SPI_DO ),
.ioctl_download( ioctl_downl ),
.ioctl_upload ( ioctl_upl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_din ( ioctl_din ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
sdram #(96) sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_ram ),
// port1 for main and sound CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( rom_init ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_cs ( cpu1_rom_cs ),
.cpu1_addr ( {1'b0, cpu1_rom_addr[15:1]} ),
.cpu1_q ( cpu1_rom_do ),
.cpu1_valid ( cpu1_rom_valid ),
.cpu2_cs ( cpu2_rom_cs ),
.cpu2_addr ( {1'b1, cpu2_rom_addr[15:1]} ),
.cpu2_q ( cpu2_rom_do ),
.cpu2_valid ( cpu2_rom_valid ),
// port2 for graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ioctl_addr[23:1] ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( rom_init ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.gfx1_addr ( 27'he000 + gfx1_rom_addr[13:1] ),
.gfx1_q ( gfx1_rom_do ),
.gfx2_addr ( 27'h10000 + gfx2_rom_addr[16:1] ),
.gfx2_q ( gfx2_rom_do ),
.gfx3_addr ( 27'h20000 + gfx3_rom_addr[15:1] ),
.gfx3_q ( gfx3_rom_do ),
.gfx3_ready ( gfx3_rom_ready )
);
// ROM download controller
always @(posedge clk_sys) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (rom_init) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ~rom_loaded;
end
wire [15:0] sound;
wire HBlank;
wire HSync;
wire VBlank;
wire VSync;
wire [8:0] hcount, vcount;
reg [2:0] vred, vgreen;
reg [1:0] vblue;
wire ce_pix;
video video(
.clk ( clk_sys ),
.ce_pix ( ce_pix ),
.hs ( HSync ),
.vs ( VSync ),
.hb ( HBlank ),
.vb ( VBlank ),
.hcount ( hcount ),
.vcount ( vcount ),
.hoffs (),
.voffs ()
);
wire rom_init = ioctl_downl && (ioctl_index==0);
//wire nvram_init = ioctl_downl && (ioctl_index==8'hFF);
core u_core(
.reset ( reset ),
.clk_sys ( clk_sys ),
.ce_pix ( ce_pix ),
.pause ( pause ),
.j1 ( j1 ),
.j2 ( j2 ),
.p1 ( p1 ),
.p2 ( p2 ),
.system ( system ),
.ioctl_index ( ioctl_index ),
.ioctl_download ( rom_init ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout ),
.ioctl_wr ( ioctl_wr ),
.hh ( hcount ),
.vv ( vcount ),
.red ( vred ),
.green ( vgreen ),
.blue ( vblue ),
.vs ( VSync ),
.hb ( HBlank ),
.sound ( sound ),
.hflip ( flip ),
.bg_on ( 1'b1 ),
.tx_on ( 1'b1 ),
.sp_on ( 1'b1 ),
.fdiv ( 2'b0 ),
.cpu1_rom_cs ( cpu1_rom_cs ),
.cpu1_rom_addr ( cpu1_rom_addr ),
.cpu1_rom_q ( cpu1_rom_addr[0] ? cpu1_rom_do[15:8] : cpu1_rom_do[7:0] ),
.cpu1_rom_valid ( cpu1_rom_valid ),
.cpu2_rom_cs ( cpu2_rom_cs ),
.cpu2_rom_addr ( cpu2_rom_addr ),
.cpu2_rom_q ( cpu2_rom_addr[0] ? cpu2_rom_do[15:8] : cpu2_rom_do[7:0] ),
.cpu2_rom_valid ( cpu2_rom_valid ),
.gfx1_rom_addr ( gfx1_rom_addr ),
.gfx1_rom_q ( gfx1_rom_addr[0] ? gfx1_rom_do[15:8] : gfx1_rom_do[7:0] ),
.gfx2_rom_addr ( gfx2_rom_addr ),
.gfx2_rom_q ( gfx2_rom_addr[0] ? gfx2_rom_do[15:8] : gfx2_rom_do[7:0] ),
.gfx3_rom_addr ( gfx3_rom_addr ),
.gfx3_rom_q ( gfx3_rom_addr[0] ? gfx3_rom_do[15:8] : gfx3_rom_do[7:0] ),
.gfx3_rom_ready ( gfx3_rom_ready )
);
wire blankn = !(HBlank | VBlank);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? vred : 0 ),
.G ( blankn ? vgreen : 0 ),
.B ( blankn ? {vblue, vblue[1]} : 0 ),
.HSync ( HSync ),
.VSync ( VSync ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.ce_divider ( 1'b0 ),
.rotate ( { orientation[1], rotate } ),
.blend ( blend ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.ypbpr ( ypbpr ),
.no_csync ( no_csync )
);
wire audio_out;
assign AUDIO_L = audio_out;
assign AUDIO_R = audio_out;
dac #(.C_bits(16))dac(
.clk_i(clk_sys),
.res_n_i(1'b1),
.dac_i({~sound[15], sound[14:0]}),
.dac_o(audio_out)
);
wire m_up1, m_down1, m_left1, m_right1, m_up1B, m_down1B, m_left1B, m_right1B;
wire m_up2, m_down2, m_left2, m_right2, m_up2B, m_down2B, m_left2B, m_right2B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire [11:0] m_fire1, m_fire2;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b0 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_up1B, m_down1B, m_left1B, m_right1B, m_fire1, m_up1, m_down1, m_left1, m_right1} ),
.player2 ( {m_up2B, m_down2B, m_left2B, m_right2B, m_fire2, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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module clk_en #(
parameter DIV=12,
parameter OFFSET=0
)
(
input ref_clk,
output reg cen,
input [15:0] div,
input [1:0] fdiv
);
reg [15:0] cnt = OFFSET;
wire [15:0] cmax = div << { fdiv, 1'b0 };
always @(posedge ref_clk) begin
if (fdiv != 2'b11) begin
if (cnt == cmax) begin
cnt <= 16'd0;
cen <= 1'b1;
end
else begin
cen <= 1'b0;
cnt <= cnt + 16'd1;
end
end
end
endmodule

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//============================================================================
//
// Nichibutsu Galivan Hardware
//
// Original by (C) 2022 Pierre Cornier
// Enhanced/optimized by (C) Gyorgy Szombathelyi
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module core(
input reset,
input clk_sys,
output ce_pix,
input pause,
input [7:0] j1,
input [7:0] j2,
input [7:0] p1,
input [7:0] p2,
input [7:0] system,
input [7:0] ioctl_index,
input ioctl_download,
input [26:0] ioctl_addr,
input [15:0] ioctl_dout,
input ioctl_wr,
output [2:0] red,
output [2:0] green,
output [1:0] blue,
output [15:0] sound,
input [8:0] hh,
input [8:0] vv,
input vs,
input hb,
output hflip,
input bg_on,
input tx_on,
input sp_on,
input [1:0] fdiv,
output cpu1_rom_cs,
output [15:0] cpu1_rom_addr,
input [7:0] cpu1_rom_q,
input cpu1_rom_valid,
output cpu2_rom_cs,
output [15:0] cpu2_rom_addr,
input [7:0] cpu2_rom_q,
input cpu2_rom_valid,
output [13:0] gfx1_rom_addr,
input [7:0] gfx1_rom_q,
output [16:0] gfx2_rom_addr,
input [7:0] gfx2_rom_q,
output [15:0] gfx3_rom_addr,
input [7:0] gfx3_rom_q,
input gfx3_rom_ready
);
/******** CLOCKS ********/
wire clk_en_4, clk_en_6, acpu_irq_en;
clk_en mcpu_clk_en(clk_sys, clk_en_6, 16'd7, fdiv);
clk_en acpu_clk_en(clk_sys, clk_en_4, 16'd11);
clk_en acpu_irq_cen(clk_sys, acpu_irq_en, 16'd6400);
assign ce_pix = clk_en_6;
/******** MCPU ********/
wire [7:0] mcpu_din;
wire [15:0] mcpu_addr;
wire [7:0] mcpu_dout;
wire mcpu_rd_n;
wire mcpu_wr_n;
wire mcpu_m1_n;
wire mcpu_mreq_n;
wire mcpu_iorq_n;
wire mcpu_rfsh_n;
reg mcpu_int_n;
reg oldvs;
always @(posedge clk_sys) begin
oldvs <= vs;
if (oldvs & ~vs) mcpu_int_n <= 1'b0;
if (~mcpu_iorq_n & ~mcpu_m1_n) mcpu_int_n <= 1'b1;
end
reg real_pause = 0;
always @(posedge clk_sys)
if (~clk_en_6 & mcpu_mreq_n & mcpu_iorq_n) real_pause <= pause;
t80s mcpu(
.reset_n ( ~reset ),
.clk ( clk_sys ),
.cen ( clk_en_6 & (!cpu1_rom_cs | cpu1_rom_valid) & !real_pause ),
.wait_n ( 1'b1 ),
.int_n ( mcpu_int_n ),
.nmi_n ( 1'b1 ),
.busrq_n ( 1'b1 ),
.m1_n ( mcpu_m1_n ),
.mreq_n ( mcpu_mreq_n ),
.iorq_n ( mcpu_iorq_n ),
.rd_n ( mcpu_rd_n ),
.wr_n ( mcpu_wr_n ),
.rfsh_n ( mcpu_rfsh_n ),
.halt_n ( ),
.busak_n ( ),
.A ( mcpu_addr ),
.di ( mcpu_din ),
.do ( mcpu_dout )
);
/******** MCPU MEMORY CS ********/
wire mcpu_rom1_en = mcpu_iorq_n & ~mcpu_addr[15]; // (mcpu_addr < 16'h8000);
wire mcpu_rom2_en = mcpu_iorq_n & mcpu_addr[15:14] == 2'b10; // ~mcpu_rom1_en & (mcpu_addr < 16'hc000);
wire mcpu_rom_en = mcpu_iorq_n & (mcpu_rom1_en | mcpu_rom2_en);
wire mcpu_bank_en = mcpu_iorq_n & /*mcpu_addr[15:13] == 3'b110; */ ~mcpu_rom_en & (mcpu_addr < 16'he000);
wire mcpu_vram1_en = mcpu_iorq_n & /*mcpu_addr[15:10] == 5'b1101_10; */ ~mcpu_rom_en & mcpu_bank_en & (mcpu_addr >= 16'hd800 && mcpu_addr < 16'hdc00);
wire mcpu_vram2_en = mcpu_iorq_n & /*mcpu_addr[15:10] == 5'b1101_11; */ ~mcpu_rom_en & mcpu_bank_en & (mcpu_addr >= 16'hdc00);
wire mcpu_spr_en = mcpu_iorq_n & ~mcpu_rom_en & ~mcpu_bank_en & (mcpu_addr < 16'he100);
wire mcpu_ram_en = mcpu_iorq_n & ~mcpu_rom_en & ~mcpu_bank_en & ~mcpu_spr_en;
/******** MCPU MEMORIES ********/
wire [9:0] gfx_vram_addr;
wire [5:0] gfx_spr_addr;
wire [7:0] mcpu_rom1_q;
wire [7:0] mcpu_rom2_q;
wire [7:0] mcpu_bank1_q;
wire [7:0] mcpu_bank2_q;
wire [7:0] mcpu_vram1_q;
wire [7:0] mcpu_vram2_q;
wire [7:0] mcpu_spr_q;
wire [31:0] mcpu_spr_qb;
wire [7:0] mcpu_ram_q;
`ifndef EXT_ROM
wire [7:0] mcpu_rom1_data = ioctl_dout[7:0];
wire [14:0] mcpu_rom1_addr = ioctl_download ? ioctl_addr : mcpu_addr[14:0];
wire mcpu_rom1_wren_a = ioctl_download && ioctl_addr < 27'h8000 ? ioctl_wr : 1'b0;
wire [7:0] mcpu_rom2_data = ioctl_dout[7:0];
wire [14:0] mcpu_rom2_addr = ioctl_download ? ioctl_addr - 27'h8000 : mcpu_addr[14:0];
wire mcpu_rom2_wren_a = ioctl_download && ioctl_addr >= 27'h8000 && ioctl_addr < 27'hc000 ? ioctl_wr : 1'b0;
wire [7:0] mcpu_bank1_data = ioctl_dout[7:0];
wire [13:0] mcpu_bank1_addr = ioctl_download ? ioctl_addr - 27'hc000 : mcpu_addr[13:0];
wire mcpu_bank1_wren_a = ioctl_download && ioctl_addr >= 27'hc000 && ioctl_addr < 27'he000 ? ioctl_wr : 1'b0;
wire [7:0] mcpu_bank2_data = ioctl_dout[7:0];
wire [13:0] mcpu_bank2_addr = ioctl_download ? ioctl_addr - 27'he000 : mcpu_addr[13:0];
wire mcpu_bank2_wren_a = ioctl_download && ioctl_addr >= 27'he000 && ioctl_addr < 27'h10000 ? ioctl_wr : 1'b0;
dpram #(15,8) mcpu_rom1(
.clock ( clk_sys ),
.address_a ( mcpu_rom1_addr ),
.data_a ( mcpu_rom1_data ),
.q_a ( mcpu_rom1_q ),
.rden_a ( 1'b1 ),
.wren_a ( mcpu_rom1_wren_a )
);
dpram #(14,8) mcpu_rom2(
.clock ( clk_sys ),
.address_a ( mcpu_rom2_addr ),
.data_a ( mcpu_rom2_data ),
.q_a ( mcpu_rom2_q ),
.rden_a ( 1'b1 ),
.wren_a ( mcpu_rom2_wren_a )
);
// 0xc000-0xdfff
dpram #(14,8) mcpu_bank1(
.clock ( clk_sys ),
.address_a ( mcpu_bank1_addr ),
.data_a ( mcpu_bank1_data ),
.q_a ( mcpu_bank1_q ),
.rden_a ( 1'b1 ),
.wren_a ( mcpu_bank1_wren_a )
);
// 0xc000-0xdfff
dpram #(14,8) mcpu_bank2(
.clock ( clk_sys ),
.address_a ( mcpu_bank2_addr ),
.data_a ( mcpu_bank2_data ),
.q_a ( mcpu_bank2_q ),
.rden_a ( 1'b1 ),
.wren_a ( mcpu_bank2_wren_a )
);
`else
assign mcpu_rom1_q = cpu1_rom_q;
assign mcpu_rom2_q = cpu1_rom_q;
assign mcpu_bank1_q = cpu1_rom_q;
assign mcpu_bank2_q = cpu1_rom_q;
assign cpu1_rom_addr = mcpu_bank_en ? {bank ? 3'b111 : 3'b110, mcpu_addr[12:0]} : mcpu_addr;
assign cpu1_rom_cs = (mcpu_rom_en | mcpu_bank_en) & mcpu_rfsh_n & ~mcpu_mreq_n;
`endif
// 0xd800-0xdbff (mcpu write only)
dpram #(10,8) mcpu_vram1(
.clock ( clk_sys ),
.address_a ( mcpu_addr[9:0] ),
.address_b ( gfx_vram_addr ),
.data_a ( mcpu_dout ),
.q_b ( mcpu_vram1_q ),
.rden_b ( 1'b1 ),
.wren_a ( ~mcpu_wr_n & mcpu_vram1_en )
);
// 0xdc00-0xdfff (mcpu write only)
dpram #(10,8) mcpu_vram2(
.clock ( clk_sys ),
.address_a ( mcpu_addr[9:0] ),
.address_b ( gfx_vram_addr ),
.data_a ( mcpu_dout ),
.q_b ( mcpu_vram2_q ),
.rden_b ( 1'b1 ),
.wren_a ( ~mcpu_wr_n & mcpu_vram2_en )
);
// 0xe000-0xe0ff
// SPRAM is managed by the GFX module
// 0xe100-0xffff
dpram #(13,8) mcpu_ram(
.clock ( clk_sys ),
.address_a ( mcpu_addr[12:0] ),
.data_a ( mcpu_dout ),
.q_a ( mcpu_ram_q ),
.rden_a ( 1'b1 ),
.wren_a ( ~mcpu_wr_n & mcpu_ram_en )
);
/******** MCPU I/O ********/
reg [7:0] mcpu_io_data;
reg [10:0] scrollx;
reg [10:0] scrolly;
reg [2:0] layers;
reg [7:0] snd_latch;
reg clear_latch;
reg bank;
reg flip;
assign hflip = flip;
always @(posedge clk_sys) begin
reg [7:0] old_j1;
old_j1 <= j1;
if (clear_latch) snd_latch <= 8'd0;
if (~mcpu_iorq_n & mcpu_m1_n) begin
case (mcpu_addr[7:0])
8'h00: mcpu_io_data <= j1;
8'h01: mcpu_io_data <= j2;
8'h02: mcpu_io_data <= system;
8'h03: mcpu_io_data <= p1;
8'h04: mcpu_io_data <= p2;
8'h40: { bank, flip } <= { mcpu_dout[7], mcpu_dout[2] };
8'h41: scrollx[7:0] <= mcpu_dout;
8'h42: { layers, scrollx[10:8] } <= { mcpu_dout[7:5], mcpu_dout[2:0] };
8'h43: scrolly[7:0] <= mcpu_dout;
8'h44: scrolly[10:8] <= mcpu_dout[2:0];
8'h45: snd_latch <= { mcpu_dout[6:0], 1'b1 };
8'hc0: mcpu_io_data <= 8'h58;
endcase
end
// for scroll layer debug
if (real_pause) begin
if (~j1[0] & old_j1[0]) scrollx <= scrollx - 5'd16;
if (~j1[1] & old_j1[1]) scrollx <= scrollx + 5'd16;
if (~j1[2] & old_j1[2]) scrollx <= scrollx - 1'd1;
if (~j1[3] & old_j1[3]) scrollx <= scrollx + 1'd1;
end
end
/******** MCPU DATA BUS ********/
assign mcpu_din =
~mcpu_iorq_n ? mcpu_io_data :
mcpu_rom1_en ? mcpu_rom1_q :
mcpu_rom2_en ? mcpu_rom2_q :
mcpu_bank_en & ~bank ? mcpu_bank1_q :
mcpu_bank_en & bank ? mcpu_bank2_q :
mcpu_spr_en ? mcpu_spr_q :
mcpu_ram_en ? mcpu_ram_q : 8'd0;
/******** ACPU ********/
wire [7:0] acpu_din;
wire [15:0] acpu_addr;
wire [7:0] acpu_dout;
wire acpu_rd_n;
wire acpu_wr_n;
wire acpu_m1_n;
wire acpu_mreq_n;
wire acpu_iorq_n;
wire acpu_rfsh_n;
reg acpu_int_n;
reg old_acpu_irq_en;
always @(posedge clk_sys) begin
old_acpu_irq_en <= acpu_irq_en;
if (~old_acpu_irq_en & acpu_irq_en) acpu_int_n <= 1'b0;
if (~acpu_iorq_n & ~acpu_m1_n) acpu_int_n <= 1'b1;
end
t80s acpu(
.reset_n ( ~reset ),
.clk ( clk_sys ),
.cen ( clk_en_4 & (!cpu2_rom_cs | cpu2_rom_valid) ),
.wait_n ( 1'b1 ),
.int_n ( acpu_int_n ),
.nmi_n ( 1'b1 ),
.busrq_n ( 1'b1 ),
.m1_n ( acpu_m1_n ),
.mreq_n ( acpu_mreq_n ),
.iorq_n ( acpu_iorq_n ),
.rd_n ( acpu_rd_n ),
.wr_n ( acpu_wr_n ),
.rfsh_n ( acpu_rfsh_n ),
.halt_n ( ),
.busak_n ( ),
.A ( acpu_addr ),
.di ( acpu_din ),
.do ( acpu_dout )
);
/******** ACPU MEMORY CS ********/
wire acpu_rom1_en = acpu_iorq_n & ~acpu_addr[15]; // acpu_addr < 16'h8000;
wire acpu_rom2_en = acpu_iorq_n & acpu_addr[15:14] == 2'b10; //~acpu_rom1_en & acpu_addr < 16'hc000;
wire acpu_ram_en = acpu_iorq_n & acpu_addr[15:14] == 2'b11; //~acpu_rom1_en & ~acpu_rom2_en;
/******** ACPU MEMORIES ********/
wire [7:0] acpu_ram_q;
wire [7:0] acpu_rom1_q;
wire [7:0] acpu_rom2_q;
`ifndef EXT_ROM
wire [7:0] acpu_rom_data = ioctl_dout;
wire [15:0] acpu_rom1_addr = ioctl_download ? ioctl_addr - 27'h10000 : acpu_addr;
wire acpu_rom1_wren_a = ioctl_download && ioctl_addr >= 27'h10000 && ioctl_addr < 27'h18000 ? ioctl_wr : 1'b0;
wire [15:0] acpu_rom2_addr = ioctl_download ? ioctl_addr - 27'h18000 : acpu_addr;
wire acpu_rom2_wren_a = ioctl_download && ioctl_addr >= 27'h18000 && ioctl_addr < 27'h1c000 ? ioctl_wr : 1'b0;
dpram #(15,8) acpu_rom1(
.clock ( clk_sys ),
.address_a ( acpu_rom1_addr ),
.data_a ( acpu_rom_data ),
.q_a ( acpu_rom1_q ),
.rden_a ( 1'b1 ),
.wren_a ( acpu_rom1_wren_a )
);
dpram #(14,8) acpu_rom2(
.clock ( clk_sys ),
.address_a ( acpu_rom2_addr ),
.data_a ( acpu_rom_data ),
.q_a ( acpu_rom2_q ),
.rden_a ( 1'b1 ),
.wren_a ( acpu_rom2_wren_a )
);
`else
assign cpu2_rom_addr = acpu_addr;
assign cpu2_rom_cs = (acpu_rom1_en | acpu_rom2_en) & acpu_rfsh_n & ~acpu_mreq_n;
assign acpu_rom1_q = cpu2_rom_q;
assign acpu_rom2_q = cpu2_rom_q;
`endif
dpram #(11,8) acpu_ram(
.clock ( clk_sys ),
.address_a ( acpu_addr[10:0] ),
.data_a ( acpu_dout ),
.q_a ( acpu_ram_q ),
.rden_a ( 1'b1 ),
.wren_a ( ~acpu_wr_n & acpu_ram_en )
);
/******** ACPU I/O ********/
reg [7:0] dac1, dac2;
always @(posedge clk_sys) begin
clear_latch <= 1'b0;
if (~acpu_iorq_n & acpu_m1_n & ~acpu_wr_n) begin
case (acpu_addr[7:0])
8'h02: dac1 <= acpu_dout;
8'h03: dac2 <= acpu_dout;
8'h04: clear_latch <= 1'b1;
default: ;
endcase
end
end
wire snd_latch_cs = ~acpu_iorq_n & acpu_m1_n & acpu_addr[7:0] == 8'h06;
/******** YM3526 ********/
wire ym3526_addr = acpu_addr[0];
wire ym3526_cs = ~acpu_iorq_n & acpu_m1_n & acpu_addr[7:1] == 0;
jtopl ym3526(
.rst ( reset ),
.clk ( clk_sys ),
.cen ( clk_en_4 ),
.din ( acpu_dout ),
.addr ( ym3526_addr ),
.cs_n ( ~ym3526_cs ),
.wr_n ( acpu_wr_n ),
.dout ( ),
.irq_n ( ),
.snd ( ym_sound ),
.sample ( )
);
wire [15:0] ym_sound;
assign sound = ym_sound + {dac1, 5'd0} + {dac2, 5'd0};
/******** ACPU DATA BUS ********/
assign acpu_din =
snd_latch_cs ? snd_latch :
acpu_ram_en ? acpu_ram_q :
acpu_rom1_en ? acpu_rom1_q :
acpu_rom2_en ? acpu_rom2_q :
8'hFF; // RST38h - important, as the code mistakenly enables interrupts in IM0 mode
/********* GFX ********/
wire [13:0] gfx1_addr;
wire [16:0] gfx2_addr;
wire [15:0] gfx3_addr;
wire [13:0] gfx4_addr;
wire [7:0] gfx_rom1_q;
wire [7:0] gfx_rom2_q;
wire [7:0] gfx_rom3_q;
wire [7:0] gfx_rom41_q;
wire [7:0] gfx_rom42_q;
wire [7:0] gfx_prom_addr;
wire [7:0] gfx_prom4_addr;
wire [7:0] gfx_sprom_addr;
wire [3:0] prom1_q;
wire [3:0] prom2_q;
wire [3:0] prom3_q;
wire [3:0] prom4_q;
wire [3:0] sprom_q;
wire [2:0] r;
wire [2:0] g;
wire [1:0] b;
gfx gfx(
.clk ( clk_sys ),
.ce_pix ( ce_pix ),
.hh ( hh ),
.vv ( vv ),
.scrollx ( scrollx ),
.scrolly ( scrolly ),
.layers ( layers ),
.spram_addr ( mcpu_addr[7:0] ),
.spram_din ( mcpu_dout ),
.spram_dout ( mcpu_spr_q ),
.spram_wr ( ~mcpu_wr_n & mcpu_spr_en ),
.bg_map_addr ( gfx4_addr ),
.bg_map_data ( gfx_rom41_q ),
.bg_attr_data ( gfx_rom42_q ),
.bg_tile_addr ( gfx2_addr ),
.bg_tile_data ( gfx_rom2_q ),
.vram_addr ( gfx_vram_addr ),
.vram1_data ( mcpu_vram1_q ),
.vram2_data ( mcpu_vram2_q ),
.tx_tile_addr ( gfx1_addr ),
.tx_tile_data ( gfx_rom1_q ),
.spr_gfx_addr ( gfx3_addr ),
.spr_gfx_data ( gfx_rom3_q ),
.spr_gfx_rdy ( gfx3_rom_ready ),
.spr_bnk_addr ( gfx_sprom_addr ),
.spr_bnk_data ( sprom_q ),
.spr_lut_addr ( gfx_prom4_addr ),
.spr_lut_data ( prom4_q ),
.prom_addr ( gfx_prom_addr ),
.prom1_data ( prom1_q ),
.prom2_data ( prom2_q ),
.prom3_data ( prom3_q ),
.r ( red ),
.g ( green ),
.b ( blue ),
.h_flip ( flip ),
.v_flip ( flip ),
.hb ( hb ),
.bg_on ( bg_on ),
.tx_on ( tx_on ),
.sp_on ( sp_on )
);
/******** GFX ROMs ********/
wire [7:0] gfx_rom_data = ioctl_dout;
`ifndef EXT_ROM
wire [13:0] gfx_rom1_addr = ioctl_download ? ioctl_addr - 27'h1c000 : gfx1_addr;
wire gfx_rom1_wren_a = ioctl_download && ioctl_addr >= 27'h1c000 && ioctl_addr < 27'h20000 ? ioctl_wr : 1'b0;
wire [16:0] gfx_rom2_addr = ioctl_download ? ioctl_addr - 27'h20000 : gfx2_addr;
wire gfx_rom2_wren_a = ioctl_download && ioctl_addr >= 27'h20000 && ioctl_addr < 27'h40000 ? ioctl_wr : 1'b0;
wire [15:0] gfx_rom3_addr = ioctl_download ? ioctl_addr - 27'h40000 : gfx3_addr;
wire gfx_rom3_wren_a = ioctl_download && ioctl_addr >= 27'h40000 && ioctl_addr < 27'h50000 ? ioctl_wr : 1'b0;
dpram #(14,8) gfx_rom1(
.clock ( clk_sys ),
.address_a ( gfx_rom1_addr ),
.data_a ( gfx_rom_data ),
.q_a ( gfx_rom1_q ),
.rden_a ( 1'b1 ),
.wren_a ( gfx_rom1_wren_a )
);
dpram #(17,8) gfx_rom2(
.clock ( clk_sys ),
.address_a ( gfx_rom2_addr ),
.data_a ( gfx_rom_data ),
.q_a ( gfx_rom2_q ),
.rden_a ( 1'b1 ),
.wren_a ( gfx_rom2_wren_a )
);
dpram #(16,8) gfx_rom3(
.clock ( clk_sys ),
.address_a ( gfx_rom3_addr ),
.data_a ( gfx_rom_data ),
.q_a ( gfx_rom3_q ),
.rden_a ( 1'b1 ),
.wren_a ( gfx_rom3_wren_a )
);
`else
assign gfx1_rom_addr = gfx1_addr;
assign gfx_rom1_q = gfx1_rom_q;
assign gfx2_rom_addr = gfx2_addr;
assign gfx_rom2_q = gfx2_rom_q;
assign gfx3_rom_addr = gfx3_addr;
assign gfx_rom3_q = gfx3_rom_q;
`endif
wire [13:0] gfx_rom41_addr = ioctl_download ? ioctl_addr - 27'h50000 : gfx4_addr;
wire gfx_rom41_wren_a = ioctl_download && ioctl_addr >= 27'h50000 && ioctl_addr < 27'h54000 ? ioctl_wr : 1'b0;
wire [13:0] gfx_rom42_addr = ioctl_download ? ioctl_addr - 27'h54000 : gfx4_addr;
wire gfx_rom42_wren_a = ioctl_download && ioctl_addr >= 27'h54000 && ioctl_addr < 27'h58000 ? ioctl_wr : 1'b0;
dpram #(14,8) gfx_rom41(
.clock ( clk_sys ),
.address_a ( gfx_rom41_addr ),
.data_a ( gfx_rom_data ),
.q_a ( gfx_rom41_q ),
.rden_a ( 1'b1 ),
.wren_a ( gfx_rom41_wren_a )
);
dpram #(14,8) gfx_rom42(
.clock ( clk_sys ),
.address_a ( gfx_rom42_addr ),
.data_a ( gfx_rom_data ),
.q_a ( gfx_rom42_q ),
.rden_a ( 1'b1 ),
.wren_a ( gfx_rom42_wren_a )
);
/******** COLOR ROMs ********/
wire [7:0] prom1_addr = ioctl_download ? ioctl_addr - 27'h58000 : gfx_prom_addr;
wire prom1_wren_a = ioctl_download && ioctl_addr >= 27'h58000 && ioctl_addr < 27'h58100 ? ioctl_wr : 1'b0;
wire [7:0] prom2_addr = ioctl_download ? ioctl_addr - 27'h58100 : gfx_prom_addr;
wire prom2_wren_a = ioctl_download && ioctl_addr >= 27'h58100 && ioctl_addr < 27'h58200 ? ioctl_wr : 1'b0;
wire [7:0] prom3_addr = ioctl_download ? ioctl_addr - 27'h58200 : gfx_prom_addr;
wire prom3_wren_a = ioctl_download && ioctl_addr >= 27'h58200 && ioctl_addr < 27'h58300 ? ioctl_wr : 1'b0;
wire [7:0] prom4_addr = ioctl_download ? ioctl_addr - 27'h58300 : gfx_prom4_addr;
wire prom4_wren_a = ioctl_download && ioctl_addr >= 27'h58300 && ioctl_addr < 27'h58400 ? ioctl_wr : 1'b0;
wire [7:0] sprom_addr = ioctl_download ? ioctl_addr - 27'h58400 : gfx_sprom_addr;
wire sprom_wren_a = ioctl_download && ioctl_addr >= 27'h58400 && ioctl_addr < 27'h58500 ? ioctl_wr : 1'b0;
dpram #(8,4) prom1(
.clock ( clk_sys ),
.address_a ( prom1_addr ),
.data_a ( gfx_rom_data ),
.q_a ( prom1_q ),
.rden_a ( 1'b1 ),
.wren_a ( prom1_wren_a )
);
dpram #(8,4) prom2(
.clock ( clk_sys ),
.address_a ( prom2_addr ),
.data_a ( gfx_rom_data ),
.q_a ( prom2_q ),
.rden_a ( 1'b1 ),
.wren_a ( prom2_wren_a )
);
dpram #(8,4) prom3(
.clock ( clk_sys ),
.address_a ( prom3_addr ),
.data_a ( gfx_rom_data ),
.q_a ( prom3_q ),
.rden_a ( 1'b1 ),
.wren_a ( prom3_wren_a )
);
// sprite color lut
dpram #(8,4) slookup(
.clock ( clk_sys ),
.address_a ( prom4_addr ),
.data_a ( gfx_rom_data ),
.q_a ( prom4_q ),
.rden_a ( 1'b1 ),
.wren_a ( prom4_wren_a )
);
// sprite color bank info
dpram #(8,4) sprom(
.clock ( clk_sys ),
.address_a ( sprom_addr ),
.data_a ( gfx_rom_data ),
.q_a ( sprom_q ),
.rden_a ( 1'b1 ),
.wren_a ( sprom_wren_a )
);
endmodule

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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dpram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram
#(
parameter ADDRWIDTH=12,
parameter DATAWIDTH=8
)
(
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
rden_a,
rden_b,
q_a,
q_b);
input [ADDRWIDTH-1:0] address_a;
input [ADDRWIDTH-1:0] address_b;
input clock;
input [DATAWIDTH-1:0] data_a;
input [DATAWIDTH-1:0] data_b;
input wren_a;
input wren_b;
input rden_a;
input rden_b;
output [DATAWIDTH-1:0] q_a;
output [DATAWIDTH-1:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [DATAWIDTH-1:0] sub_wire0;
wire [DATAWIDTH-1:0] sub_wire1;
wire [DATAWIDTH-1:0] q_a = rden_a ? sub_wire0[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}};
wire [DATAWIDTH-1:0] q_b = rden_b ? sub_wire1[DATAWIDTH-1:0] : {DATAWIDTH{1'b0}};
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2**ADDRWIDTH,
altsyncram_component.numwords_b = 2**ADDRWIDTH,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = ADDRWIDTH,
altsyncram_component.widthad_b = ADDRWIDTH,
altsyncram_component.width_a = DATAWIDTH,
altsyncram_component.width_b = DATAWIDTH,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule

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//============================================================================
//
// Nichibutsu Galivan Hardware
//
// Original by (C) 2022 Pierre Cornier
// Enhanced/optimized by (C) Gyorgy Szombathelyi
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//
//============================================================================
module gfx(
input clk,
input ce_pix,
input [8:0] hh,
input [8:0] vv,
input [10:0] scrollx,
input [10:0] scrolly,
input [2:0] layers,
// mcpu sprite ram interface
input [7:0] spram_addr,
input [7:0] spram_din,
output reg [7:0] spram_dout,
input spram_wr,
output reg [13:0] bg_map_addr,
input [7:0] bg_map_data,
input [7:0] bg_attr_data,
output reg [16:0] bg_tile_addr,
input [7:0] bg_tile_data,
output reg [10:0] vram_addr,
input [7:0] vram1_data,
input [7:0] vram2_data,
output reg [13:0] tx_tile_addr,
input [7:0] tx_tile_data,
output reg [7:0] prom_addr,
input [3:0] prom1_data,
input [3:0] prom2_data,
input [3:0] prom3_data,
output reg [15:0] spr_gfx_addr,
input [7:0] spr_gfx_data,
input spr_gfx_rdy,
output reg [7:0] spr_bnk_addr,
input [3:0] spr_bnk_data,
output reg [7:0] spr_lut_addr,
input [3:0] spr_lut_data,
output reg [2:0] r, g,
output reg [1:0] b,
input h_flip,
input v_flip,
input hb,
input bg_on,
input tx_on,
input sp_on
);
// object RAM
// 4 bytes/sprite
// offset 0 - Y
// offset 1 - code[7:0]
// offset 2 - attr
// offset 3 - X
reg [7:0] info[255:0];
reg [7:0] smap[255:0]; // object ram copy
wire [8:0] vh = v_flip ? {vv[8], ~vv[7:0]} : vv;
wire [8:0] hr = h_flip ? {hh[8], ~hh[7:0]} : hh;
// line buffers
reg spbuf_wren_a;
reg [8:0] spbuf_addr_a;
reg [5:0] spbuf_data_a;
wire [5:0] spbuf_q_b;
wire [8:0] hr_sp = hr - (h_flip ? -4'd13 : 4'd13);
dpram #(9,6) spbuf(
.clock ( clk ),
.address_a ( spbuf_addr_a ),
.data_a ( spbuf_data_a ),
.q_a ( ),
.rden_a ( 1'b0 ),
.wren_a ( spbuf_wren_a ),
.address_b ( { ~vh[0], hr_sp[7:0] } ),
.data_b ( 6'h3f ),
.q_b ( spbuf_q_b ),
.rden_b ( 1'b1 ),
.wren_b ( ce_pix & ~hr_sp[8] )
);
// sprite registers
reg [3:0] sp_next;
reg [3:0] sp_state;
reg [7:0] spri;
reg [7:0] attr;
reg [8:0] spx;
reg [7:0] spy;
reg [8:0] code;
wire [7:0] smap_q = smap[spri];
wire [8:0] spy_next = v_flip ? smap_q - 1'd1 : 8'd239 - smap_q;
wire [7:0] spxa = spx[7:0] - 8'd128;
wire [7:0] sdy = vv - spy;
wire [3:0] sdyf = (!v_flip ^ attr[7]) ? sdy[3:0] : 4'd15 - sdy[3:0];
reg [3:0] sdx;
wire [3:0] sdxf = attr[6] ? 4'd15 - sdx[3:0] : sdx[3:0];
wire [3:0] sp_color_code = spr_gfx_data[sdx[0]*4+:4];
// bg registers
reg [10:0] scx_reg;
reg [10:0] scy_reg;
reg [7:0] bg_attr_data_d;
reg [7:0] bg_attr_data_d2;
reg [7:0] bg_tile_data_d;
wire [10:0] sh = {h_flip & hr[8], h_flip & hr[8], hr} + scx_reg;
wire [10:0] sv = vh + scy_reg;
wire [3:0] bg_color_code = bg_tile_data_d[sh[0]*4+:4];
// txt registers
reg [7:0] vram2_data_d;
reg [7:0] vram2_data_d2;
reg [7:0] tx_tile_data_d;
wire [3:0] tx_color_code = tx_tile_data_d[hr[0]*4+:4];
reg color_ok;
reg [3:0] rstate;
reg [3:0] rnext;
reg [5:0] bg, tx;
reg [7:0] smap_addr;
reg copied;
// sprite rendering to dual-line buffer
always @(posedge clk) begin
spram_dout <= info[spram_addr];
if (spram_wr) info[spram_addr] <= spram_din;
if (vv == 0 && hh == 0) begin
scx_reg <= scrollx;
scy_reg <= scrolly;
copied = 1'b0;
end
if (vv > 250 && ~copied) begin
smap[smap_addr] <= info[smap_addr];
smap_addr <= smap_addr + 8'd1;
if (smap_addr == 8'd255) copied <= 1'b1;
end
spbuf_wren_a <= 0;
case (sp_state)
4'd0: begin
spri <= 8'd0;
sp_state <= (hh == 0 && vv < 256 && sp_on) ? 4'd1 : 4'd0;
end
4'd1: begin
spy <= spy_next; // spri=0
if (vv >= spy_next && vv < (spy_next+16)) begin
// sprite is visible
sp_state <= 4'd2;
spri <= spri + 1'd1;
end
else begin
// not visible, check next or finish
if (spri == 8'd252) sp_state <= 4'd0;
else spri <= spri + 4'd4;
end
end
4'd2: begin
code[7:0] <= smap_q; // spri=1
spri <= spri + 1'd1;
sp_state <= 4'd3;
end
4'd3: begin
attr <= smap_q; // spri=2
spri <= spri + 1'd1;
sp_state <= 4'd4;
end
4'd4: begin
spx <= { attr[0], smap_q }; // range is 0-511 visible area is 128-383 (spri=3)
code[8] <= attr[1];
spri <= spri + 1'd1;
sp_state <= 4'd5;
sdx <= 4'd0;
end
4'd5: begin
spr_gfx_addr <= { sdx[1], code, sdyf[3:0], sdx[3:2] };
spr_bnk_addr <= code[8:2];
`ifdef EXT_ROM
if (spr_gfx_rdy) sp_state <= 4'd6;
`else
sp_state <= 4'd14; // for internal ROMs only
sp_next <= 4'd6;
`endif
end
4'd6: begin
spr_lut_addr <= { spr_bnk_data, sp_color_code };
sp_state <= 4'd14;
sp_next <= 4'd7;
end
4'd7: begin
if (spx+sdxf > 128 && spx+sdxf < 256+128 && spr_lut_data != 4'hf) begin
spbuf_addr_a <= { vh[0], spxa+sdxf };
spbuf_data_a <= { (spr_lut_data[3] ? spr_bnk_data[3:2] : spr_bnk_data[1:0]), sp_color_code };
spbuf_wren_a <= 1;
end
sdx <= sdx + 4'd1;
sp_state <= sdx[0] ? 4'd5 : 4'd6;
if (sdx == 4'd15) begin
sp_state <= spri == 0 ? 4'd0 : 4'd1;
end
end
4'd14: sp_state <= 4'd15;
4'd15: sp_state <= sp_next;
endcase
end
// scrolling background layer
always @(posedge clk) begin
if (ce_pix) begin
if(sh[2:0] == (3'b111 ^ {3{h_flip}}))
bg_map_addr <= {sv[10:4], sh[10:4]};
if(sh[0] ^ h_flip) begin
bg_tile_addr <= { bg_attr_data[1:0], bg_map_data, sv[3:0], ~sh[3], sh[2:1] };
bg_tile_data_d <= bg_tile_data;
bg_attr_data_d <= bg_attr_data;
bg_attr_data_d2 <= bg_attr_data_d;
end
bg <= { (bg_color_code[3] ? bg_attr_data_d2[6:5] : bg_attr_data_d2[4:3]), bg_color_code };
end
end
// text layer
always @(posedge clk) begin
if (ce_pix) begin
if(hh[2:0] == 3'b111)
vram_addr <= { hr[7:3], vh[7:3] };
if(hh[0]) begin
tx_tile_addr <= { vram2_data[0], vram1_data, vh[2:0], hr[2:1] };
tx_tile_data_d <= tx_tile_data;
vram2_data_d <= vram2_data;
vram2_data_d2 <= vram2_data_d;
end
tx <= { (tx_color_code[3] ? vram2_data_d2[6:5] : vram2_data_d2[4:3]), tx_color_code };
end
end
// display output
always @(posedge clk) begin
if (ce_pix) begin
color_ok <= 1'b0;
if (~layers[1]) begin
prom_addr <= { 2'b11, bg };
color_ok <= 1'b1;
end
if (spbuf_q_b[3:0] != 4'hf) begin
prom_addr <= { 2'b10, spbuf_q_b };
color_ok <= 1'b1;
end
if (~layers[2] && tx[3:0] != 4'hf) begin
prom_addr <= { 2'b00, tx };
color_ok <= 1'b1;
end
if (layers[0] && spbuf_q_b[3:0] != 4'hf) begin
prom_addr <= { 2'b10, spbuf_q_b };
color_ok <= 1'b1;
end
if (color_ok) begin
r <= prom1_data[3:1];
g <= prom2_data[3:1];
b <= prom3_data[3:2];
end
else begin
{ r, g, b } <= 8'd0;
end
end
end
endmodule

4
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_mist.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_mist.ppf"]

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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire6_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire6_bv(0 DOWNTO 0) <= "0";
sub_wire6 <= To_stdlogicvector(sub_wire6_bv);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
sub_wire4 <= inclk0;
sub_wire5 <= sub_wire6(0 DOWNTO 0) & sub_wire4;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 9,
clk0_duty_cycle => 50,
clk0_multiply_by => 32,
clk0_phase_shift => "0",
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
inclk => sub_wire5,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "96.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "48.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "96.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

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@ -0,0 +1,363 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input cpu1_cs,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
output reg cpu1_valid,
input cpu2_cs,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
output reg cpu2_valid,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [15:0] port2_q,
input [22:1] gfx1_addr,
output reg [15:0] gfx1_q,
input [22:1] gfx2_addr,
output reg [15:0] gfx2_q,
input [22:1] gfx3_addr,
output reg [15:0] gfx3_q,
output gfx3_ready
);
parameter MHZ = 80; // 80 MHz default clock, adjust to calculate the refresh rate correctly
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 16'd78*MHZ/10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 2
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2;
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [22:1] addr_last2[4];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
reg [1:0] gfx3_ok = 0;
assign gfx3_ready = |gfx3_ok;
localparam PORT_NONE = 3'd0;
localparam PORT_CPU1 = 3'd1;
localparam PORT_CPU2 = 3'd2;
localparam PORT_GFX1 = 3'd1;
localparam PORT_GFX2 = 3'd2;
localparam PORT_GFX3 = 3'd3;
localparam PORT_REQ = 3'd4;
reg [2:0] next_port[2];
reg [2:0] port[2];
wire oe_next, we_next;
wire [1:0] ds_next;
wire [15:0] din_next;
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = 0;
ds_next = 2'b00;
{ oe_next, we_next } = 2'b00;
din_next = 0;
if (refresh) begin
// nothing
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
ds_next = port1_ds;
{ oe_next, we_next } = { ~port1_we, port1_we };
din_next = port1_d;
end else if (cpu1_cs & !cpu1_valid) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
ds_next = 2'b11;
{ oe_next, we_next } = { 2'b10 };
end else if (cpu2_cs & !cpu2_valid) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
ds_next = 2'b11;
{ oe_next, we_next } = { 2'b10 };
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (gfx1_addr != addr_last2[PORT_GFX1]) begin
next_port[1] = PORT_GFX1;
addr_latch_next[1] = { 2'b10, gfx1_addr };
end else if (gfx2_addr != addr_last2[PORT_GFX2]) begin
next_port[1] = PORT_GFX2;
addr_latch_next[1] = { 2'b10, gfx2_addr };
end else if (gfx3_addr != addr_last2[PORT_GFX3]) begin
next_port[1] = PORT_GFX3;
addr_latch_next[1] = { 2'b10, gfx3_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
gfx3_ok <= {gfx3_ok[0], 1'b0};
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if (!cpu1_cs) cpu1_valid <= 0;
if (!cpu2_cs) cpu2_valid <= 0;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= { oe_next, we_next };
ds[0] <= ds_next;
din_latch[0] <= din_next;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
end
if (next_port[0] == PORT_REQ) port1_state <= port1_req;
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][22:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; cpu1_valid <= 1; end
PORT_CPU2: begin cpu2_q <= sd_din; cpu2_valid <= 1; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q <= sd_din;
PORT_GFX1: gfx1_q <= sd_din;
PORT_GFX2: gfx2_q <= sd_din;
PORT_GFX3: begin gfx3_q <= sd_din; gfx3_ok <= 2'b01; end
default: ;
endcase;
end
end
end
endmodule

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// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: spram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module spram (
address_a,
address_b,
clock,
data_a,
data_b,
rden_a,
rden_b,
wren_a,
wren_b,
q_a,
q_b);
input [7:0] address_a;
input [5:0] address_b;
input clock;
input [7:0] data_a;
input [31:0] data_b;
input rden_a;
input rden_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [31:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri1 rden_a;
tri1 rden_b;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [31:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [31:0] q_b = sub_wire1[31:0];
altsyncram altsyncram_component (
.address_a (address_a),
.address_b (address_b),
.clock0 (clock),
.data_a (data_a),
.data_b (data_b),
.rden_a (rden_a),
.rden_b (rden_b),
.wren_a (wren_a),
.wren_b (wren_b),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus ());
defparam
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK0",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.numwords_b = 64,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_b = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 8,
altsyncram_component.widthad_b = 6,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 32,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "1024"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "1"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "64"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "6"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 8 0 INPUT NODEFVAL "address_a[7..0]"
// Retrieval info: USED_PORT: address_b 0 0 6 0 INPUT NODEFVAL "address_b[5..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
// Retrieval info: USED_PORT: rden_a 0 0 0 0 INPUT VCC "rden_a"
// Retrieval info: USED_PORT: rden_b 0 0 0 0 INPUT VCC "rden_b"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address_a 0 0 8 0
// Retrieval info: CONNECT: @address_b 0 0 6 0 address_b 0 0 6 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden_a 0 0 0 0
// Retrieval info: CONNECT: @rden_b 0 0 0 0 rden_b 0 0 0 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL spram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL spram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL spram_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf

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module video(
input clk,
input ce_pix,
output reg hs,
output reg vs,
output reg hb,
output reg vb,
output reg [8:0] hcount,
output reg [8:0] vcount,
output reg frame,
input [3:0] hoffs,
input [3:0] voffs
);
initial begin
hs <= 1'b1;
vs <= 1'b1;
end
always @(posedge clk) begin
frame <= 1'b0;
if (ce_pix) begin
hcount <= hcount + 9'd1;
case (hcount)
16: hb <= 1'b0;
271: hb <= 1'b1;
(308 - $signed(hoffs)): hs <= 1'b0;
(340 - $signed(hoffs)): hs <= 1'b1;
383: begin
vcount <= vcount + 9'd1;
hcount <= 9'b0;
case (vcount)
15: vb <= 1'b0;
239: vb <= 1'b1;
(249 - $signed(voffs)) : vs <= 1'b0;
(252 - $signed(voffs)) : vs <= 1'b1;
262: vcount <= 9'd0;
endcase
end
endcase
end
end
endmodule