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IremM62: close to original video timings

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This commit is contained in:
Gyorgy Szombathelyi 2020-03-07 19:20:18 +01:00
parent c1fdb9b431
commit 920ab77b6f
10 changed files with 108 additions and 72 deletions
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2
Arcade_MiST/IremM62 Hardware/IremM62.sdc
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@ -54,7 +54,7 @@ set_time_format -unit ns -decimal_places 3
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set vid_clk "pll|altpll_component|auto_generated|pll1|clk[2]"
set game_clk "pll|altpll_component|auto_generated|pll1|clk[1]"
set aud_clk "pll|altpll_component|auto_generated|pll1|clk[3]"

8
Arcade_MiST/IremM62 Hardware/rtl/Graphics.VHD
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@ -15,6 +15,7 @@ entity Graphics is
port
(
hwsel : in integer;
hires : in std_logic;
sprite_prom : in prom_a(0 to 31);
bitmap_ctl_i : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
@ -71,12 +72,7 @@ begin
graphics_o.vblank <= video_o_s.vblank;
--graphics_o.vblank <= from_video_ctl.vblank;
irem62_hsize <= 384+16 when hwsel = HW_LDRUN or
hwsel = HW_LDRUN2 or
hwsel = HW_LDRUN3 or
hwsel = HW_LDRUN4 or
hwsel = HW_KIDNIKI else
256+16;
irem62_hsize <= 384+16 when hires = '1' else 256+16;
pace_video_controller_inst : entity work.pace_video_controller
generic map

17
Arcade_MiST/IremM62 Hardware/rtl/IremM62_MiST.sv
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@ -52,7 +52,7 @@ assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_sd;
assign SDRAM_CKE = 1;
wire clk_sys, clk_aud, clk_sd, clk_vid;
wire clk_sys, clk_vid, clk_aud, clk_sd;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
@ -144,8 +144,7 @@ data_io data_io(
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 20'h30000;
reg clkref;
always @(posedge clk_vid) clkref <= ~clkref;
wire clkref;
reg port1_req, port2_req;
sdram sdram(
@ -223,8 +222,8 @@ wire blankn = 1'b1;//todo
wire [3:0] g,b,r;
target_top target_top(
.clock_sys(clk_sys),//4xclk_vid
.clock_vid(clk_vid),//11MHz
.clock_sys(clk_sys),//24 MHz
.vid_clk_en(clkref),
.clk_aud(clk_aud),//0.895MHz
.reset_in(reset),
.hwsel(core_mod),
@ -265,10 +264,10 @@ target_top target_top(
.gfx1_do(chr1_do),
.gfx2_addr(sp_addr),
.gfx2_do(sp_do)
);
);
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(11)) mist_video(
.clk_sys ( clk_vid ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
@ -283,7 +282,7 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video(
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( { 1'b1, rotate } ),
.ce_divider ( 1'b0 ),
.ce_divider ( 1'b1 ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.blend ( blend ),

2
Arcade_MiST/IremM62 Hardware/rtl/pace.vhd
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@ -19,6 +19,7 @@ entity PACE is
-- hardware variant
hwsel : in integer;
hires : in std_logic;
-- misc I/O
buttons_i : in from_BUTTONS_t;
@ -153,6 +154,7 @@ begin
Port Map
(
hwsel => hwsel,
hires => hires,
sprite_prom => sprite_prom,
bitmap_ctl_i => to_bitmap_ctl,

8
Arcade_MiST/IremM62 Hardware/rtl/platform_pkg.vhd
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@ -28,11 +28,11 @@ package platform_pkg is
-- constant PACE_VIDEO_H_SYNC_POLARITY : std_logic := '0';
-- constant PACE_VIDEO_V_SYNC_POLARITY : std_logic := '0';
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_PAL_576x288_50Hz;
constant PACE_CLK0_DIVIDE_BY : natural := 27;
constant PACE_CLK0_MULTIPLY_BY : natural := 44; -- 27*44/27 = 44MHz
constant PACE_VIDEO_CONTROLLER_TYPE : PACEVideoController_t := PACE_VIDEO_IREMM62;
constant PACE_CLK0_DIVIDE_BY : natural := 9;
constant PACE_CLK0_MULTIPLY_BY : natural := 8; -- 27*8/9 = 24MHz
constant PACE_CLK1_DIVIDE_BY : natural := 27;
constant PACE_CLK1_MULTIPLY_BY : natural := 11; -- 27*11/27 = 11MHz
constant PACE_CLK1_MULTIPLY_BY : natural := 8; -- 27*8/9 = 24MHz
constant PACE_VIDEO_H_SCALE : integer := 1;
constant PACE_VIDEO_V_SCALE : integer := 1;
constant PACE_ENABLE_ADV724 : std_logic := '1';

40
Arcade_MiST/IremM62 Hardware/rtl/pll_mist.vhd
View File

@ -164,17 +164,17 @@ BEGIN
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 88,
clk0_multiply_by => 8,
clk0_phase_shift => "0",
clk1_divide_by => 27,
clk1_divide_by => 9,
clk1_duty_cycle => 50,
clk1_multiply_by => 44,
clk1_multiply_by => 8,
clk1_phase_shift => "0",
clk2_divide_by => 27,
clk2_divide_by => 9,
clk2_duty_cycle => 50,
clk2_multiply_by => 11,
clk2_multiply_by => 16,
clk2_phase_shift => "0",
clk3_divide_by => 5400,
clk3_duty_cycle => 50,
@ -263,15 +263,15 @@ END SYN;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "88.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "44.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "11.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "24.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "48.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "0.895000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@ -303,12 +303,12 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "44"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "11"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "88"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "88.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "44.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "11.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "24.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "48.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "0.89500000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
@ -369,17 +369,17 @@ END SYN;
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "88"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "44"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5400"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"

32
Arcade_MiST/IremM62 Hardware/rtl/sdram.sv
View File

@ -66,6 +66,8 @@ module sdram (
output reg [31:0] sp_q
);
parameter MHZ = 16'd80; // 80 MHz default clock, set it to proper value to calculate refresh rate
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
@ -75,8 +77,8 @@ localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single acc
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// 64ms/8192 rows = 7.8us
localparam RFRSH_CYCLES = 16'd78*MHZ/4'd10;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
@ -86,35 +88,37 @@ localparam RFRSH_CYCLES = 10'd842;
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0
0 RAS0 data1 returned
1 ras0 - data1 returned
2 data1 returned
3 CAS0
2
3 CAS0
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
7 cas1 - data0 read burst terminated
8
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_RAS0 = 4'd0; // first state in cycle
localparam STATE_RAS1 = 4'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd2;
localparam STATE_DS1b = 3'd7;
localparam STATE_READ1b = 3'd3;
localparam STATE_LAST = 3'd7;
localparam STATE_READ1 = 4'd1;
localparam STATE_DS1b = 4'd7;
localparam STATE_READ1b = 4'd2;
localparam STATE_LAST = 4'd8;
reg [2:0] t;
reg [3:0] t;
always @(posedge clk) begin
reg clkref_d;
clkref_d <= clkref;
t <= t + 1'd1;
// t <= t + 1'd1;
if ((~clkref_d && clkref && t == 4'd2) || (t != 4'd2)) t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
if (~clkref_d & clkref) t <= STATE_RAS0;
// if (~clkref_d & clkref) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------

29
Arcade_MiST/IremM62 Hardware/rtl/target_top.vhd
View File

@ -7,10 +7,11 @@ library work;
use work.pace_pkg.all;
use work.video_controller_pkg.all;
use work.platform_pkg.all;
use work.platform_variant_pkg.all;
entity target_top is port(
clock_sys : in std_logic;
clock_vid : in std_logic;
vid_clk_en : out std_logic;
clk_aud : in std_logic;
reset_in : in std_logic;
hwsel : in integer;
@ -69,9 +70,27 @@ architecture SYN of target_top is
signal platform_o : to_PLATFORM_IO_t;
signal sound_data : std_logic_vector(7 downto 0);
signal hires : std_logic;
signal count : std_logic_vector(1 downto 0);
begin
hires <= '1' when hwsel = HW_LDRUN or hwsel = HW_LDRUN2 or hwsel = HW_LDRUN3 or hwsel = HW_LDRUN4 or hwsel = HW_KIDNIKI else '0';
process(clock_sys) begin
if rising_edge(clock_sys) then
-- video clock enable: 24MHz/3 when hires, else 24MHz/4
if hires = '1' and count = 2 then
count <= "00";
else
count <= count + 1;
end if;
end if;
end process;
clkrst_i.clk(0) <= clock_sys;
clkrst_i.clk(1) <= clock_vid;
-- clkrst_i.clk(1) <= clock_vid;
clkrst_i.clk(1) <= clock_sys;
clkrst_i.arst <= reset_in;
clkrst_i.arst_n <= not clkrst_i.arst;
@ -88,8 +107,11 @@ GEN_RESETS : for i in 0 to 3 generate
end process;
end generate GEN_RESETS;
vid_clk_en <= video_i.clk_ena;
video_i.clk <= clkrst_i.clk(1);
video_i.clk_ena <= '1';
-- video_i.clk_ena <= '1';
video_i.clk_ena <= '1' when count = "00" else '0';
video_i.reset <= clkrst_i.rst(1);
VGA_R <= video_o.rgb.r(9 downto 6);
VGA_G <= video_o.rgb.g(9 downto 6);
@ -113,6 +135,7 @@ pace_inst : entity work.pace
port map(
clkrst_i => clkrst_i,
hwsel => hwsel,
hires => hires,
buttons_i => buttons_i,
switches_i => switches_i,
inputs_i => inputs_i,

40
Arcade_MiST/IremM62 Hardware/rtl/video_controller.vhd
View File

@ -262,16 +262,18 @@ begin
v_back_porch_r <= 13;
v_border_r <= (240-VIDEO_V_SIZE)/2;
when PACE_VIDEO_PAL_576x288_50Hz =>
-- pixclk=11 MHz
h_front_porch_r <= 2*6;
h_sync_r <= 2*28;
h_back_porch_r <= 2*30;
h_border_r <= (576-VIDEO_H_SIZE)/2;
v_front_porch_r <= 8;
when PACE_VIDEO_IREMM62 =>
-- Irem M62 original timings
-- 512x282@8MHz or 384x282@6Mhz, (384x256 or 256x256 active display), 55 Hz
-- use 312 lines here, for 50 Hz PAL compatiblity.
h_front_porch_r <= 12;
h_sync_r <= 38;
h_back_porch_r <= 62;
h_border_r <= 0;--(576-VIDEO_H_SIZE)/2;
v_front_porch_r <= 10+15;
v_sync_r <= 3;
v_back_porch_r <= 13;
v_border_r <= (288-VIDEO_V_SIZE)/2;
v_back_porch_r <= 13+15;
v_border_r <= 0;--(288-VIDEO_V_SIZE)/2;
when others =>
null;
@ -280,7 +282,7 @@ begin
h_video_r <= VIDEO_H_SIZE;
v_video_r <= VIDEO_V_SIZE;
border_rgb_r <= BORDER_RGB;
--end if;
end process reg_proc;
@ -420,9 +422,10 @@ begin
vblank_v_r := (others => '0');
stb_cnt_v := (others => '1');
elsif rising_edge(clk) and clk_ena = '1' then
-- hblank
-- register control signals and handle scaling
video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers
-- video_ctl_o.hblank <= not hactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers
video_ctl_o.vblank <= not vactive_s after SIM_DELAY; -- used only by the bitmap/tilemap/sprite controllers
-- handle scaling
video_ctl_o.stb <= stb_cnt_v(H_SCALE-1) after SIM_DELAY;
@ -433,11 +436,20 @@ begin
end if;
video_ctl_o.x <= std_logic_vector(resize(x_s(x_s'left downto H_SCALE-1), video_ctl_o.x'length)) after SIM_DELAY;
video_ctl_o.y <= std_logic_vector(resize(y_s(y_s'left downto V_SCALE-1), video_ctl_o.y'length)) after SIM_DELAY;
-- register video outputs
if hactive_v = '1' and vactive_v = '1' then
-- set hblank used only by the bitmap/tilemap/sprite controllers early
if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY-7) or
x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY-7) then
video_ctl_o.hblank <= '1';
else
video_o.rgb <= rgb_i after SIM_DELAY;
video_ctl_o.hblank <= '0'; -- used only by the bitmap/tilemap/sprite controllers
end if;
-- active video
if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or
if x_s(x_s'left downto H_SCALE-1) < (L_CROP + PIPELINE_DELAY) or
x_s(x_s'left downto H_SCALE-1) >= (H_SIZE - R_CROP + PIPELINE_DELAY) then
video_o.rgb <= RGB_BLACK after SIM_DELAY;
else

2
Arcade_MiST/IremM62 Hardware/rtl/video_controller_pkg.vhd
View File

@ -22,7 +22,7 @@ package video_controller_pkg is
PACE_VIDEO_ARCADE_STD_336x240_60Hz_28M64, -- arcade std resolution (28.64MHz)
PACE_VIDEO_CVBS_720x288p_50Hz, -- generic composite
PACE_VIDEO_LCM_320x240_60Hz, -- DE2 LCD
PACE_VIDEO_PAL_576x288_50Hz
PACE_VIDEO_IREMM62
);
type PACEVideoDisplay_t is