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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-19 17:27:59 +00:00

Rename Signal

This commit is contained in:
Marcel 2021-06-18 21:54:26 +02:00
parent 22fc239c6f
commit 95595bd789
10 changed files with 32 additions and 34 deletions

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@ -31,7 +31,7 @@ entity canyon_bomber is
port(
clk_12 : in std_logic; -- 12MHz input clock
Reset_I : in std_logic; -- Reset button (Active low)
RGB : out std_logic_vector(7 downto 0);
VID : out std_logic_vector(7 downto 0);
Vblank_O : out std_logic;
HBlank_O : out std_logic;
HSync_O : out std_logic;
@ -233,15 +233,13 @@ Sync_O <= CompSync_n_s;
HBlank_O <= HBlank;
VBlank_O <= VBlank;
HSync_O <= HSync;
VSync_O <= VSync;
VID: process(clk_12, Video)
Vid_Mix: process(clk_12, Video)
begin
case Video is
when "01" => RGB <= ("10000000");
when "10" => RGB <= ("01010000");
when "11" => RGB <= ("11111111");
when others => RGB <= ("00000000");
when "01" => VID <= ("10000000");
when "10" => VID <= ("01010000");
when "11" => VID <= ("11111111");
when others => VID <= ("00000000");
end case;
end process;

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@ -59,7 +59,7 @@ wire hs, vs;
canyon_bomber canyon_bomber(
.clk_12(clk_12),
.Reset_I(~(status[0] | buttons[1])),
.RGB(vid),
.VID(vid),
.Vblank_O(vb),
.HBlank_O(hb),
.HSync_O(hs),

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@ -1,2 +1,2 @@
`define BUILD_DATE "210524"
`define BUILD_TIME "164622"
`define BUILD_DATE "210618"
`define BUILD_TIME "214731"

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@ -35,7 +35,7 @@ port(
Vs : out std_logic;
Vb : out std_logic;
Hb : out std_logic;
RGB : out std_logic_vector(7 downto 0);
VID : out std_logic_vector(7 downto 0);
Audio : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter
Coin1_I : in std_logic; -- Coin switches (Active low)
Coin2_I : in std_logic;
@ -235,13 +235,13 @@ Vs <= Vsync;
Video(0) <= (not BlackPF_n) nor CompBlank_s;
Video(1) <= (not WhitePF_n);
VID: process(clk_12, Video)
Vid_Mix: process(clk_12, Video)
begin
case Video is
when "01" => RGB <= ("10000000");
when "10" => RGB <= ("01010000");
when "11" => RGB <= ("11111111");
when others => RGB <= ("00000000");
when "01" => VID <= ("10000000");
when "10" => VID <= ("01010000");
when "11" => VID <= ("11111111");
when others => VID <= ("00000000");
end case;
end process;

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@ -64,7 +64,7 @@ dominos dominos (
.Vs(vs),
.Vb(vb),
.Hb(hb),
.RGB(vid),
.VID(vid),
.Audio(audio),
.Coin1_I(~m_coin1),
.Coin2_I(~m_coin2),

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@ -31,7 +31,7 @@ entity sprint2 is
port(
clk_12 : in std_logic; -- 12MHz input clock
Reset_n : in std_logic; -- Reset button (Active low)
RGB : out std_logic_vector(7 downto 0);
VID : out std_logic_vector(7 downto 0);
Sync_O : out std_logic; -- Composite sync output (1.2k)
Audio1_O : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter
Audio2_O : out std_logic_vector(6 downto 0);
@ -399,13 +399,13 @@ Hb <= HBLANK;
Hs <= Hsync;
Vs <= Vsync;
VID: process(clk_12, Video)
col: process(clk_12, Video)
begin
case Video is
when "01" => RGB <= ("10000000");
when "10" => RGB <= ("01010000");
when "11" => RGB <= ("11111111");
when others => RGB <= ("00000000");
when "01" => VID <= ("10000000");
when "10" => VID <= ("01010000");
when "11" => VID <= ("11111111");
when others => VID <= ("00000000");
end case;
end process;

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@ -61,7 +61,7 @@ sprint2 sprint2(
.Vs(vs),
.Vb(vb),
.Hb(hb),
.RGB(vid),
.VID(vid),
.Audio1_O(audio1),
.Audio2_O(audio2),
.Coin1_I(~m_coin1),

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@ -170,10 +170,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(sprint2_mist)
# ------------------------
# ------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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@ -36,7 +36,7 @@ port(
Vs : out std_logic;
Vb : out std_logic;
Hb : out std_logic;
RGB : out std_logic_vector(7 downto 0);
VID : out std_logic_vector(7 downto 0);
Audio : out std_logic_vector(6 downto 0);
Coin1_I : in std_logic; -- Coin switches (Active low)
Coin2_I : in std_logic;
@ -341,13 +341,13 @@ Hb <= HBLANK;
Hs <= Hsync;
Vs <= Vsync;
VID: process(clk_12, Video)
col: process(clk_12, Video)
begin
case Video is
when "01" => RGB <= ("10000000");
when "10" => RGB <= ("01010000");
when "11" => RGB <= ("11111111");
when others => RGB <= ("00000000");
when "01" => VID <= ("10000000");
when "10" => VID <= ("01010000");
when "11" => VID <= ("11111111");
when others => VID <= ("00000000");
end case;
end process;

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@ -57,7 +57,7 @@ wire hs, vs;
sprint1 sprint1(
.clk_12(clk_12),
.Reset_n(~(status[0] | buttons[1])),
.RGB(vid),
.VID(vid),
.Hs(hs),
.Vs(vs),
.Vb(vb),