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https://github.com/Gehstock/Mist_FPGA.git
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Rename Signal
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parent
22fc239c6f
commit
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@ -31,7 +31,7 @@ entity canyon_bomber is
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port(
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clk_12 : in std_logic; -- 12MHz input clock
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Reset_I : in std_logic; -- Reset button (Active low)
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RGB : out std_logic_vector(7 downto 0);
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VID : out std_logic_vector(7 downto 0);
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Vblank_O : out std_logic;
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HBlank_O : out std_logic;
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HSync_O : out std_logic;
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@ -233,15 +233,13 @@ Sync_O <= CompSync_n_s;
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HBlank_O <= HBlank;
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VBlank_O <= VBlank;
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HSync_O <= HSync;
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VSync_O <= VSync;
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VID: process(clk_12, Video)
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Vid_Mix: process(clk_12, Video)
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begin
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case Video is
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when "01" => RGB <= ("10000000");
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when "10" => RGB <= ("01010000");
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when "11" => RGB <= ("11111111");
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when others => RGB <= ("00000000");
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when "01" => VID <= ("10000000");
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when "10" => VID <= ("01010000");
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when "11" => VID <= ("11111111");
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when others => VID <= ("00000000");
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end case;
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end process;
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@ -59,7 +59,7 @@ wire hs, vs;
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canyon_bomber canyon_bomber(
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.clk_12(clk_12),
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.Reset_I(~(status[0] | buttons[1])),
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.RGB(vid),
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.VID(vid),
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.Vblank_O(vb),
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.HBlank_O(hb),
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.HSync_O(hs),
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@ -1,2 +1,2 @@
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`define BUILD_DATE "210524"
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`define BUILD_TIME "164622"
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`define BUILD_DATE "210618"
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`define BUILD_TIME "214731"
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@ -35,7 +35,7 @@ port(
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Vs : out std_logic;
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Vb : out std_logic;
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Hb : out std_logic;
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RGB : out std_logic_vector(7 downto 0);
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VID : out std_logic_vector(7 downto 0);
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Audio : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter
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Coin1_I : in std_logic; -- Coin switches (Active low)
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Coin2_I : in std_logic;
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@ -235,13 +235,13 @@ Vs <= Vsync;
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Video(0) <= (not BlackPF_n) nor CompBlank_s;
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Video(1) <= (not WhitePF_n);
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VID: process(clk_12, Video)
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Vid_Mix: process(clk_12, Video)
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begin
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case Video is
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when "01" => RGB <= ("10000000");
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when "10" => RGB <= ("01010000");
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when "11" => RGB <= ("11111111");
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when others => RGB <= ("00000000");
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when "01" => VID <= ("10000000");
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when "10" => VID <= ("01010000");
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when "11" => VID <= ("11111111");
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when others => VID <= ("00000000");
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end case;
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end process;
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@ -64,7 +64,7 @@ dominos dominos (
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.Vs(vs),
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.Vb(vb),
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.Hb(hb),
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.RGB(vid),
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.VID(vid),
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.Audio(audio),
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.Coin1_I(~m_coin1),
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.Coin2_I(~m_coin2),
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@ -31,7 +31,7 @@ entity sprint2 is
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port(
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clk_12 : in std_logic; -- 12MHz input clock
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Reset_n : in std_logic; -- Reset button (Active low)
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RGB : out std_logic_vector(7 downto 0);
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VID : out std_logic_vector(7 downto 0);
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Sync_O : out std_logic; -- Composite sync output (1.2k)
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Audio1_O : out std_logic_vector(6 downto 0); -- Ideally this should have a simple low pass filter
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Audio2_O : out std_logic_vector(6 downto 0);
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@ -399,13 +399,13 @@ Hb <= HBLANK;
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Hs <= Hsync;
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Vs <= Vsync;
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VID: process(clk_12, Video)
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col: process(clk_12, Video)
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begin
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case Video is
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when "01" => RGB <= ("10000000");
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when "10" => RGB <= ("01010000");
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when "11" => RGB <= ("11111111");
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when others => RGB <= ("00000000");
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when "01" => VID <= ("10000000");
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when "10" => VID <= ("01010000");
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when "11" => VID <= ("11111111");
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when others => VID <= ("00000000");
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end case;
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end process;
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@ -61,7 +61,7 @@ sprint2 sprint2(
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.Vs(vs),
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.Vb(vb),
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.Hb(hb),
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.RGB(vid),
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.VID(vid),
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.Audio1_O(audio1),
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.Audio2_O(audio2),
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.Coin1_I(~m_coin1),
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@ -170,10 +170,10 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# end DESIGN_PARTITION(Top)
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# -------------------------
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# end ENTITY(sprint2_mist)
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# ------------------------
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# ------------------------
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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@ -36,7 +36,7 @@ port(
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Vs : out std_logic;
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Vb : out std_logic;
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Hb : out std_logic;
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RGB : out std_logic_vector(7 downto 0);
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VID : out std_logic_vector(7 downto 0);
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Audio : out std_logic_vector(6 downto 0);
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Coin1_I : in std_logic; -- Coin switches (Active low)
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Coin2_I : in std_logic;
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@ -341,13 +341,13 @@ Hb <= HBLANK;
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Hs <= Hsync;
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Vs <= Vsync;
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VID: process(clk_12, Video)
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col: process(clk_12, Video)
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begin
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case Video is
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when "01" => RGB <= ("10000000");
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when "10" => RGB <= ("01010000");
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when "11" => RGB <= ("11111111");
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when others => RGB <= ("00000000");
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when "01" => VID <= ("10000000");
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when "10" => VID <= ("01010000");
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when "11" => VID <= ("11111111");
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when others => VID <= ("00000000");
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end case;
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end process;
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@ -57,7 +57,7 @@ wire hs, vs;
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sprint1 sprint1(
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.clk_12(clk_12),
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.Reset_n(~(status[0] | buttons[1])),
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.RGB(vid),
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.VID(vid),
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.Hs(hs),
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.Vs(vs),
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.Vb(vb),
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