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Add AY8912 Sound

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Gehstock
2018-12-02 11:56:30 +01:00
parent 8857570d1a
commit 9c41b57dd9
13 changed files with 103 additions and 85 deletions
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11
Computer_MiST/Galaksija_MiST/Galaksija_Mist.srf
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@@ -12,6 +12,17 @@
{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(218): incomplete case statement has no default case item" { } { } 0 10270 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(300): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(302): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(305): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(306): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(320): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(317): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(301): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(303): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(307): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(321): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Case Statement warning at galaksija_top.sv(318): case item expression covers a value already covered by a previous case item" { } { } 0 10272 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10296 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}

7
Computer_MiST/Galaksija_MiST/README.txt
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@@ -1,8 +1,7 @@
WIP
VGA Only
No Lowercase on Keboard
48k Ram
Rom 1+2
32k Ram
Rom 1+2+3
AY8910

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Computer_MiST/Galaksija_MiST/Snapshot/Galaksija_Mist.rbf
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16
Computer_MiST/Galaksija_MiST/rtl/AY8912.sv
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@@ -33,16 +33,6 @@ wire [7:0] volTableAy[16] =
8'h90, 8'hb5, 8'hd7, 8'hff
};
wire [7:0] volTableYm[32] =
'{8'h00, 8'h01, 8'h01, 8'h02,
8'h02, 8'h03, 8'h03, 8'h04,
8'h06, 8'h07, 8'h09, 8'h0a,
8'h0c, 8'h0e, 8'h11, 8'h13,
8'h17, 8'h1b, 8'h20, 8'h25,
8'h2c, 8'h35, 8'h3e, 8'h47,
8'h54, 8'h66, 8'h77, 8'h88,
8'ha1, 8'hc0, 8'he0, 8'hff
};
// Read from AY
assign DO = dout;
@@ -280,9 +270,9 @@ wire [4:0] A = ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | poly17[0])) ? 5
wire [4:0] B = ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | poly17[0])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]};
wire [4:0] C = ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | poly17[0])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]};
assign CHANNEL_A = volTableYm[A];
assign CHANNEL_B = volTableYm[B];
assign CHANNEL_C = volTableYm[C];
assign CHANNEL_A = volTableAy[A[4:1]];
assign CHANNEL_B = volTableAy[B[4:1]];
assign CHANNEL_C = volTableAy[C[4:1]];
endmodule

11
Computer_MiST/Galaksija_MiST/rtl/Galaksija_MiST.sv
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@@ -23,6 +23,7 @@ localparam CONF_STR = {
"Galaksija;;",
// "F,GAL,Load Program;",
"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"O4,Sound,Off,On;",
"T9,Reset;",
"V,v1.00.",`BUILD_DATE
};
@@ -75,9 +76,9 @@ video_mixer (
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( video[5:0] ),
.G ( video[5:0] ),
.B ( video[5:0] ),
.R ( video[5:0] ),
.G ( video[5:0] ),
.B ( video[5:0] ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
@@ -105,14 +106,14 @@ galaksija_top galaksija_top (
.video_dat(video),
.video_hs(hs),
.video_vs(vs),
.video_blankn()//todo
.video_blank()
);
dac #(
.msbi_g(7))
dac (
.clk_i(clk_25),
.res_n_i(1'b1),
.res_n_i(status[4] ? 1'b1 : 1'b0),
.dac_i(audio),
.dac_o(AUDIO_L)
);

4
Computer_MiST/Galaksija_MiST/rtl/build_id.v
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@@ -1,2 +1,2 @@
`define BUILD_DATE "181130"
`define BUILD_TIME "230736"
`define BUILD_DATE "181202"
`define BUILD_TIME "114154"

135
Computer_MiST/Galaksija_MiST/rtl/galaksija_top.sv
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@@ -9,7 +9,7 @@ module galaksija_top(
output [7:0] video_dat,
output video_hs,
output video_vs,
output video_blankn
output video_blank
);
reg [6:0] reset_cnt = 0;
@@ -97,7 +97,7 @@ rom2(
.q(rom2_out)
);
/*//todo CS Signal
wire [7:0] rom3_out;
reg rd_rom3;
@@ -109,18 +109,18 @@ rom3(
.address(addr[11:0]),
.clock(sysclk & rd_rom3),
.q(rom3_out)
);*/
);
reg rd_mram, wr_mram;
wire cs_mram0 = ~addr[15] & ~addr[14];
wire we_mram0 = wr_mram & cs_mram0;
wire [7:0] mram0_out;
spram #(
.widthad_a(14),
spram #(//2k
.widthad_a(11),
.width_a(8))
ram00(
.address(addr[13:0]),
.address(addr[10:0]),
.clock(sysclk),
.wren(we_mram0),
.data(odata),
@@ -131,11 +131,11 @@ wire cs_mram1 = ~addr[15] & addr[14];
wire we_mram1 = wr_mram & cs_mram1;
wire [7:0] mram1_out;
spram #(
.widthad_a(14),
spram #(//2k
.widthad_a(11),
.width_a(8))
ram01(
.address(addr[13:0]),
.address(addr[10:0]),
.clock(sysclk),
.wren(we_mram1),
.data(odata),
@@ -146,7 +146,7 @@ wire cs_mram2 = addr[15] & ~addr[14];
wire we_mram2 = wr_mram & cs_mram2;
wire [7:0] mram2_out;
spram #(
spram #(//16k
.widthad_a(14),
.width_a(8))
ram02(
@@ -156,12 +156,12 @@ ram02(
.data(odata),
.q(mram2_out)
);
/*
wire cs_mram3 = addr[15] & addr[14];
wire we_mram3 = wr_mram & cs_mram3;
wire [7:0] mram3_out;
spram #(
spram #(//16k
.widthad_a(14),
.width_a(8))
ram03(
@@ -170,14 +170,13 @@ ram03(
.wren(we_mram3),
.data(odata),
.q(mram3_out)
);*/
);
reg rd_vram;
reg wr_vram;
wire [7:0] vram_out;
galaksija_video
#(
galaksija_video#(
.h_visible(10'd640),
.h_front(10'd16),
.h_sync(10'd96),
@@ -185,16 +184,14 @@ galaksija_video
.v_visible(10'd480),
.v_front(10'd10),
.v_sync(10'd2),
.v_back(10'd33)
)
galaksija_video
(
.v_back(10'd33))
galaksija_video(
.clk(sysclk),
.resetn(reset_in),
.vga_dat(video_dat),
.vga_hsync(video_hs),
.vga_vsync(video_vs),
.vga_blankn(video_blankn),
.vga_blank(video_blank),
.rd_ram1(rd_vram),
.wr_ram1(wr_vram),
.ram1_out(vram_out),
@@ -208,6 +205,7 @@ galaksija_video
begin
rd_rom1 = 1'b0;
rd_rom2 = 1'b0;
rd_rom3 = 1'b0;
rd_vram = 1'b0;
rd_mram = 1'b0;
wr_vram = 1'b0;
@@ -216,29 +214,32 @@ galaksija_video
wr_latch = 1'b0;
casex ({~wr_n,~rd_n,mreq_n,addr[15:0]})
// CS & RD Signals
{3'b010,16'b0000xxxxxxxxxxxx}: begin idata = rom1_out; rd_rom1 = 1'b1; end // 0x0000-0x0fff
{3'b010,16'b0001xxxxxxxxxxxx}: begin idata = rom2_out; rd_rom2 = 1'b1; end // 0x1000-0x1fff
// {3'b010,16'b0001xxxxxxxxxxxx}: begin idata = rom3_out; rd_rom3 = 1'b1; end // todo ROM3 CS
{3'b010,16'b00100xxxxxxxxxxx}: begin idata = key_out; rd_key = 1'b1; end // 0x2000-0x27ff
{3'b010,16'b00101xxxxxxxxxxx}: begin idata = vram_out; rd_vram = 1'b1; end // 0x2800-0x2fff
{3'b010,16'b00110xxxxxxxxxxx}: begin idata = mram0_out; rd_mram = 1'b1; end // 0x3000-0x37ff
{3'b010,16'b00111xxxxxxxxxxx}: begin idata = mram0_out; rd_mram = 1'b1; end // 0x3800-0x3fff
{3'b010,16'b01xxxxxxxxxxxxxx}: begin idata = mram1_out; rd_mram = 1'b1; end // 0x4000-0xffff
{3'b010,16'b10xxxxxxxxxxxxxx}: begin idata = mram2_out; rd_mram = 1'b1; end // 0x4000-0xffff
// {3'b010,16'b11xxxxxxxxxxxxxx}: begin idata = mram3_out; rd_mram = 1'b1; end // 0x4000-0xffff //not enough BRAM for this
// WE Signals
{3'b100,16'b00100xxxxxxxxxxx}: wr_latch= 1'b1; // 0x2000-0x27ff
{3'b100,16'b00101xxxxxxxxxxx}: wr_vram= 1'b1; // 0x2800-0x2fff
{3'b100,16'b00110xxxxxxxxxxx}: wr_mram= 1'b1; // 0x3000-0x37ff
{3'b100,16'b00111xxxxxxxxxxx}: wr_mram= 1'b1; // 0x3000-0x37ff
//$0000...$0FFF — ROM "A" or "1" – 4 KB contains bootstrap, core control and Galaksija BASIC interpreter code
{3'b010,16'b0000xxxxxxxxxxxx}: begin idata = rom1_out; rd_rom1 = 1'b1; end
//$1000...$1FFF — ROM "B" or "2" – 4 KB (optional) – additional Galaksija BASIC commands, assembler, machine code monitor, etc.
{3'b010,16'b0001xxxxxxxxxxxx}: begin idata = rom2_out; rd_rom2 = 1'b1; end
//$2000...$27FF — keyboard and latch
{3'b010,16'b00100xxxxxxxxxxx}: begin idata = key_out; rd_key = 1'b1; end
{3'b100,16'b00100xxxxxxxxxxx}: wr_latch= 1'b1;
//$2800...$2FFF — RAM "C": 2 KB ($2800...$2BFF – Video RAM)
{3'b010,16'b00101xxxxxxxxxxx}: begin idata = vram_out; rd_vram = 1'b1; end
{3'b100,16'b00101xxxxxxxxxxx}: wr_vram= 1'b1;
//$3000...$37FF — RAM "D": 2 KB
{3'b010,16'b00110xxxxxxxxxxx}: begin idata = mram0_out; rd_mram = 1'b1; end
{3'b100,16'b00110xxxxxxxxxxx}: wr_mram= 1'b1;
//$3800...$3FFF — RAM "E": 2 KB
{3'b010,16'b00111xxxxxxxxxxx}: begin idata = mram1_out; rd_mram = 1'b1; end
{3'b100,16'b00111xxxxxxxxxxx}: wr_mram= 1'b1;
//$4000...$7FFF — RAM IC9, IC10: 16 KB
{3'b010,16'b01xxxxxxxxxxxxxx}: begin idata = mram2_out; rd_mram = 1'b1; end
{3'b100,16'b01xxxxxxxxxxxxxx}: wr_mram= 1'b1;
//$8000...$BFFF — RAM IC11, IC12: 16 KB
{3'b010,16'b10xxxxxxxxxxxxxx}: begin idata = mram3_out; rd_mram = 1'b1; end
{3'b100,16'b10xxxxxxxxxxxxxx}: wr_mram= 1'b1;
{3'b100,16'b11xxxxxxxxxxxxxx}: wr_mram= 1'b1;
endcase
//$E000...$FFFF — ROM "3" + "4" IC13: 8 KB – Graphic primitives in BASIC language, Full Screen Source Editor and soft scrolling
{3'b010,16'b1110000000000000}: begin idata = rom3_out; rd_rom3 = 1'b1; end
//default :
endcase
end
@@ -249,21 +250,17 @@ integer num;
initial
begin
for(num=0;num<63;num=num+1)
for(num=0;num<64;num=num+1)
begin
keys[num] <= 0;
end
end
always @(posedge sysclk) begin
if (rd_key)
begin
key_out <= (keys[addr[5:0]]==1) ? 8'hfe : 8'hff;
for (num=0;num<63;num=num+1) keys[num] = 1'b0;
end
if (rd_key) key_out <= (keys[addr[5:0]]==1) ? 8'hfe : 8'hff;
if(sysclk)
begin
for(num=0;num<63;num=num+1)
for(num=0;num<64;num=num+1)
begin
keys[num] = 1'b0;
end
@@ -307,8 +304,8 @@ always @(posedge sysclk) begin
8'h36 : keys[8'd38] = 1'b1; // 6
8'h3D : keys[8'd39] = 1'b1; // 7
8'h3E : keys[8'd40] = 1'b1; // 8
8'h46 : keys[8'd41] = 1'b1; // 9
//NUM Block
8'h46 : keys[8'd41] = 1'b1; // 9
// NUM Block
8'h70 : keys[8'd32] = 1'b1; // 0
8'h69 : keys[8'd33] = 1'b1; // 1
8'h72 : keys[8'd34] = 1'b1; // 2
@@ -318,9 +315,8 @@ always @(posedge sysclk) begin
8'h74 : keys[8'd38] = 1'b1; // 6
8'h6C : keys[8'd39] = 1'b1; // 7
8'h75 : keys[8'd40] = 1'b1; // 8
8'h7D : keys[8'd41] = 1'b1; // 9
8'h7D : keys[8'd41] = 1'b1; // 9
8'h4C : keys[8'd42] = 1'b1; // ; //todo "Ö" on german keyboard
8'h7C : keys[8'd43] = 1'b1; // : //todo NUM block for now
8'h41 : keys[8'd44] = 1'b1; // ,
@@ -331,12 +327,10 @@ always @(posedge sysclk) begin
8'h76 : keys[8'd49] = 1'b1; // ESC
8'h52 : begin keys[8'd33] = 1'b1; keys[8'd53] = 1'b1; end // ! ////todo "Ä" on german keyboard
8'h52 : begin keys[8'd34] = 1'b1; keys[8'd53] = 1'b1; end // " ////todo shift GALAKSIJA
//8'h52 : begin keys[8'd34] = 1'b1; keys[8'd53] = 1'b1; end // " ////todo shift GALAKSIJA
8'h12 : keys[8'd53] = 1'b1; // SHIFT L
8'h59 : keys[8'd53] = 1'b1; // SHIFT R
/*
8'h1C : keys[8'd01] = 1'b1; // a
8'h32 : keys[8'd02] = 1'b1; // b
@@ -363,11 +357,34 @@ always @(posedge sysclk) begin
8'h1D : keys[8'd23] = 1'b1; // w
8'h22 : keys[8'd24] = 1'b1; // x
8'h35 : keys[8'd25] = 1'b1; // y
8'h1A : keys[8'd26] = 1'b1; // z
*/
8'h1A : keys[8'd26] = 1'b1; // z*/
endcase
end
end
end
wire PIN_A = (1'b1 & 1'b1 & wr_n);
wire [7:0]chan_A, chan_B, chan_C;
wire A02 = ~(C00 | PIN_A);//nor
wire B02 = ~(C00 | addr[0]);//nor
wire D02 = ~(addr[6] | iorq_n);//nor
wire C00 = ~(D02 | m1_n);//nand
assign audio = chan_A & chan_B & chan_C;
AY8912 AY8912(
.CLK(sysclk),
.CE(audclk),
.RESET(~reset_in),
.BDIR(A02),
.BC(B02),
.DI(odata),
.DO(),//not used
.CHANNEL_A(chan_A),
.CHANNEL_B(chan_B),
.CHANNEL_C(chan_C),
.SEL(1'b1),//divider?
.IO_in(),//not used
.IO_out()//not used
);
endmodule

4
Computer_MiST/Galaksija_MiST/rtl/galaksija_video.sv
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@@ -5,7 +5,7 @@ module galaksija_video
output reg [7:0] vga_dat,
output reg vga_hsync,
output reg vga_vsync,
output reg vga_blankn,
output reg vga_blank,
input rd_ram1,
input wr_ram1,
input [10:0] addr,
@@ -65,7 +65,7 @@ begin
h_pos <= h_pos + 1;
rgb_data <= (h_pos > 5 && h_pos < 32*8*2+4 && v_pos < 200*2) ? data_out_rotated[h_pos[3:1]] ? 24'h000000 : 24'hffffff : 24'h000000;
end
vga_blankn <= !visible;
vga_blank <= !visible;
vga_hsync <= !((h_pos >= (h_visible + h_front)) && (h_pos < (h_visible + h_front + h_sync)));
vga_vsync <= !((v_pos >= (v_visible + v_front)) && (v_pos < (v_visible + v_front + v_sync)));
vga_dat <= rgb_data[7:0];

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Computer_MiST/Sharp - MZ-80K_MiST/mz80k_mist.qws
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