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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 01:34:38 +00:00

Update the CPU in Irem sound boards

This commit is contained in:
Gyorgy Szombathelyi 2020-03-11 12:57:25 +01:00
parent 5b1d4264fa
commit a071c8a43d
9 changed files with 7 additions and 11896 deletions

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@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:52 FEBRUARY 01, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:src/build_id.tcl"
@ -205,7 +205,6 @@ set_global_assignment -name VHDL_FILE src/video_controller.vhd
set_global_assignment -name VHDL_FILE src/moon_patrol_sound_board.vhd
set_global_assignment -name VHDL_FILE src/moon_patrol_sound_prog.vhd
set_global_assignment -name SYSTEMVERILOG_FILE src/YM2149.sv
set_global_assignment -name VHDL_FILE src/cpu68.vhd
set_global_assignment -name VHDL_FILE src/Z80.vhd
set_global_assignment -name VHDL_FILE src/tilemapctl.vhd
set_global_assignment -name VHDL_FILE src/sprom.vhd
@ -229,4 +228,5 @@ set_global_assignment -name VHDL_FILE src/Clock.vhd
set_global_assignment -name VHDL_FILE src/build_id.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/6800/cpu68.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

File diff suppressed because it is too large Load Diff

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@ -197,7 +197,7 @@ process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
select_sound_r(7) <= '0';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then

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@ -188,11 +188,11 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/TraverseUSA_MiST.sv
set_global_assignment -name VHDL_FILE rtl/traverse_usa.vhd
set_global_assignment -name VHDL_FILE rtl/moon_patrol_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/6800/cpu68.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

File diff suppressed because it is too large Load Diff

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@ -200,7 +200,7 @@ process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
select_sound_r(7) <= '0';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then

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@ -227,10 +227,10 @@ set_global_assignment -name VHDL_FILE rtl/TropicalAngel.vhd
set_global_assignment -name VHDL_FILE rtl/moon_patrol_sound_board.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu68.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/6800/cpu68.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

File diff suppressed because it is too large Load Diff

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@ -198,7 +198,7 @@ process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '1';
select_sound_r(7) <= '0';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then