mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-01-24 19:21:31 +00:00
alternate Lunar Rescue Core
This commit is contained in:
Marcel
parent
f81a2f458a
commit
a0b3c3b8dc
Binary file not shown.
@ -0,0 +1,86 @@
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library ieee;
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use ieee.std_logic_1164.all,ieee.numeric_std.all;
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entity col is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(9 downto 0);
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data : out std_logic_vector(7 downto 0)
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);
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end entity;
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architecture prom of col is
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type rom is array(0 to 1023) of std_logic_vector(7 downto 0);
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signal rom_data: rom := (
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",X"0F",
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X"0D",X"0D",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0C",X"0C",X"0E",X"0F",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0C",X"0B",X"0E",X"0F",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0D",X"0D",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0C",X"09",X"0F",X"0E",X"0E",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0E",X"0E",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0E",X"0E",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"0E",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"09",X"09",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0B",X"0B",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0F",X"0F",X"0C",X"0D",X"0B",X"0E",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0F",X"0F",X"0C",X"0C",X"0B",X"0E",X"0F",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0F",X"0F",X"0B",X"0C",X"0C",X"0E",X"0F",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0D",
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X"0F",X"0F",X"0C",X"0C",X"0C",X"0C",X"0C",X"0C",X"09",X"09",X"09",X"0D",X"0D",X"0D",X"0D",X"0E",
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X"0E",X"0E",X"0B",X"0B",X"0B",X"0C",X"0C",X"0C",X"0C",X"0D",X"0D",X"0F",X"09",X"0F",X"0D",X"0C");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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data <= rom_data(to_integer(unsigned(addr)));
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end if;
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end process;
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end architecture;
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@ -18,7 +18,7 @@
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#
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# Quartus II 64-Bit
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# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
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# Date created = 18:02:27 March 08, 2019
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# Date created = 20:49:14 June 04, 2019
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#
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# -------------------------------------------------------------------------- #
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#
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@ -44,6 +44,31 @@ set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
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set_global_assignment -name SMART_RECOMPILE ON
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set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
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set_global_assignment -name SYSTEMVERILOG_FILE rtl/TheEnd.sv
|
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set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd
|
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set_global_assignment -name VHDL_FILE rtl/scramble.vhd
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set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd
|
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set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/i82c55.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
@ -83,6 +108,7 @@ set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
@ -127,42 +153,6 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
|
||||
# --------------------
|
||||
# start ENTITY(TheEnd)
|
||||
|
||||
# start LOGICLOCK_REGION(Region_0)
|
||||
# --------------------------------
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
|
||||
# end LOGICLOCK_REGION(Region_0)
|
||||
# ------------------------------
|
||||
|
||||
# start LOGICLOCK_REGION(Region_1)
|
||||
# --------------------------------
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
|
||||
# end LOGICLOCK_REGION(Region_1)
|
||||
# ------------------------------
|
||||
|
||||
# start LOGICLOCK_REGION(Region_2)
|
||||
# --------------------------------
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
|
||||
# end LOGICLOCK_REGION(Region_2)
|
||||
# ------------------------------
|
||||
|
||||
# start LOGICLOCK_REGION(Region_3)
|
||||
# --------------------------------
|
||||
|
||||
# LogicLock Region Assignments
|
||||
# ============================
|
||||
|
||||
# end LOGICLOCK_REGION(Region_3)
|
||||
# ------------------------------
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
@ -177,31 +167,4 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
|
||||
|
||||
# end ENTITY(TheEnd)
|
||||
# ------------------
|
||||
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TheEnd.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/scramble_top.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/scramble.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/scramble_video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/scramble_audio.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/YM2149_linmix_sep.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/MULT18X18.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/i82c55.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80sed.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_SND_0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_PGM.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_1.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_OBJ_0.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/ROM/ROM_LUT.vhd
|
||||
set_global_assignment -name QIP_FILE rtl/pll.qip
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/dac.vhd
|
||||
set_global_assignment -name CDF_FILE output_files/Chain3.cdf
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
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Binary file not shown.
@ -1,23 +0,0 @@
|
||||
@echo off
|
||||
|
||||
|
||||
|
||||
|
||||
copy /b ic13_1t.bin + ic14_2t.bin + ic15_3t.bin + ic16_4t.bin + ic17_5t.bin + ic18_6t.bin CPU1.bin
|
||||
romgen.exe CPU1.bin ROM_PGM_0 14 a r > rom0.vhd
|
||||
|
||||
copy /b ic56_1.bin ROM_SND_0.bin
|
||||
romgen.exe ROM_SND_0.bin ROM_SND_0 11 a r > ROM_SND_0.vhd
|
||||
|
||||
copy /b ic55_2.bin ROM_SND_1.bin
|
||||
romgen.exe ROM_SND_1.bin ROM_SND_1 11 a r > ROM_SND_1.vhd
|
||||
|
||||
|
||||
copy /b ic30_2c.bin ROM_OBJ_0.bin
|
||||
romgen.exe ROM_OBJ_0.bin ROM_OBJ_0 11 a r > ROM_OBJ_0.vhd
|
||||
|
||||
copy /b ic31_1c.bin ROM_OBJ_1.bin
|
||||
romgen.exe ROM_OBJ_1.bin ROM_OBJ_1 11 a r > ROM_OBJ_1.vhd
|
||||
|
||||
|
||||
pause
|
||||
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@ -44,8 +44,6 @@ output [7:0] audio_s,
|
||||
input key_strobe,
|
||||
input key_pressed,
|
||||
input [7:0] key_code,
|
||||
//input PS2_KBCLK,
|
||||
//input PS2_KBDAT,
|
||||
input [9:0] SWITCH,
|
||||
input UART_RXD,
|
||||
output UART_TXD
|
||||
@ -966,19 +964,6 @@ end
|
||||
|
||||
always @ (posedge CLK50MHZ) // 50MHz
|
||||
KB_CLK <= KB_CLK + 1'b1; // 50/32 = 1.5625 MHz
|
||||
/*
|
||||
ps2_keyboard KEYBOARD(
|
||||
.RESET_N(RESET_N),
|
||||
.CLK(KB_CLK[4]),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.PS2_CLK(PS2_KBCLK),
|
||||
.PS2_DATA(PS2_KBDAT),
|
||||
.RX_SCAN(SCAN),
|
||||
.RX_PRESSED(PRESS),
|
||||
.RX_EXTENDED(EXTENDED)
|
||||
);*/
|
||||
|
||||
assign PRESS_N = ~key_pressed;
|
||||
|
||||
|
||||
@ -72,8 +72,6 @@ LASER310_TOP LASER310_TOP(
|
||||
.VGA_VS(vs),
|
||||
.AUD_ADCDAT(audio),
|
||||
.audio_s(audio_s),
|
||||
// .PS2_KBCLK(ps2_kbd_clk),
|
||||
// .PS2_KBDAT(ps2_kbd_data),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
|
||||
@ -1,227 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* gbfpgaapple APPLE ][e core.
|
||||
*
|
||||
*
|
||||
* Ver 1.0
|
||||
* July 2006
|
||||
* Latest version from gbfpgaapple.tripod.com
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* CPU section copyrighted by Daniel Wallner
|
||||
*
|
||||
******************************************************************************
|
||||
*
|
||||
* Apple ][e compatible system on a chip
|
||||
*
|
||||
* Version : 1.0
|
||||
*
|
||||
* Copyright (c) 2006 Gary Becker (gary_l_becker@yahoo.com)
|
||||
*
|
||||
* All rights reserved
|
||||
*
|
||||
* Redistribution and use in source and synthezised forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* Redistributions in synthesized form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* Neither the name of the author nor the names of other contributors may
|
||||
* be used to endorse or promote products derived from this software without
|
||||
* specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Please report bugs to the author, but before you do so, please
|
||||
* make sure that this is not a derivative work and that
|
||||
* you have the latest version of this file.
|
||||
*
|
||||
* The latest version of this file can be found at:
|
||||
* http://gbfpgaapple.tripod.com
|
||||
*******************************************************************************/
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module ps2_keyboard (
|
||||
CLK,
|
||||
RESET_N,
|
||||
PS2_CLK,
|
||||
PS2_DATA,
|
||||
RX_PRESSED,
|
||||
RX_EXTENDED,
|
||||
RX_SCAN
|
||||
);
|
||||
|
||||
input CLK;
|
||||
input RESET_N;
|
||||
input PS2_CLK;
|
||||
input PS2_DATA;
|
||||
output RX_PRESSED;
|
||||
reg RX_PRESSED;
|
||||
output RX_EXTENDED;
|
||||
reg RX_EXTENDED;
|
||||
output [7:0] RX_SCAN;
|
||||
reg [7:0] RX_SCAN;
|
||||
|
||||
reg KB_CLK;
|
||||
reg KB_DATA;
|
||||
reg KB_CLK_B;
|
||||
reg KB_DATA_B;
|
||||
reg PRESSED_N;
|
||||
reg EXTENDED;
|
||||
reg [2:0] BIT;
|
||||
reg [7:0] STATE;
|
||||
reg [7:0] SCAN;
|
||||
wire PARITY;
|
||||
reg [10:0] TIMER;
|
||||
reg KILLER;
|
||||
wire RESET_X;
|
||||
|
||||
// Double buffer
|
||||
always @ (posedge CLK)
|
||||
begin
|
||||
KB_CLK_B <= PS2_CLK;
|
||||
KB_DATA_B <= PS2_DATA;
|
||||
KB_CLK <= KB_CLK_B;
|
||||
KB_DATA <= KB_DATA_B;
|
||||
end
|
||||
assign PARITY = ~(((SCAN[0]^SCAN[1])
|
||||
^(SCAN[2]^SCAN[3]))
|
||||
^((SCAN[4]^SCAN[5])
|
||||
^(SCAN[6]^SCAN[7])));
|
||||
|
||||
assign RESET_X = RESET_N & KILLER;
|
||||
always @ (negedge CLK or negedge RESET_N)
|
||||
if(!RESET_N)
|
||||
begin
|
||||
KILLER <= 1'b1;
|
||||
TIMER <= 11'h000;
|
||||
end
|
||||
else
|
||||
case(TIMER)
|
||||
11'h000:
|
||||
begin
|
||||
KILLER <= 1'b1;
|
||||
if(STATE != 8'h00)
|
||||
TIMER <= 11'h001;
|
||||
end
|
||||
11'h7FD:
|
||||
begin
|
||||
KILLER <= 1'b0;
|
||||
TIMER <= 11'h7FE;
|
||||
end
|
||||
default:
|
||||
if(STATE == 8'h00)
|
||||
TIMER <= 11'h000;
|
||||
else
|
||||
TIMER <= TIMER + 1'b1;
|
||||
endcase
|
||||
|
||||
always @ (posedge CLK or negedge RESET_X)
|
||||
begin
|
||||
if(!RESET_X)
|
||||
begin
|
||||
STATE <= 8'h00;
|
||||
SCAN <= 8'h00;
|
||||
BIT <= 3'b000;
|
||||
RX_SCAN <= 8'h00;
|
||||
RX_PRESSED <= 1'b0;
|
||||
PRESSED_N <= 1'b0;
|
||||
EXTENDED <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
|
||||
case (STATE)
|
||||
8'h00: // Hunt for start bit
|
||||
begin
|
||||
SCAN <= 8'h00;
|
||||
BIT <= 3'b000;
|
||||
RX_SCAN <= 8'h00;
|
||||
RX_PRESSED <= 1'b0;
|
||||
if(~KB_DATA & ~KB_CLK)
|
||||
STATE <= 8'h01;
|
||||
end
|
||||
8'h01: // Started
|
||||
begin
|
||||
if(KB_CLK)
|
||||
STATE <= 8'h02;
|
||||
end
|
||||
8'h02: // Hunt for Bit
|
||||
begin
|
||||
if(~KB_CLK)
|
||||
STATE <= 8'h03;
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
if(KB_CLK)
|
||||
begin
|
||||
SCAN[BIT] <= KB_DATA;
|
||||
BIT <= BIT + 1'b1;
|
||||
if(BIT == 3'b111)
|
||||
STATE <= 8'h04;
|
||||
else
|
||||
STATE <= 8'h02;
|
||||
end
|
||||
end
|
||||
8'h04: // Hunt for Bit
|
||||
begin
|
||||
if(~KB_CLK)
|
||||
STATE <= 8'h05;
|
||||
end
|
||||
8'h05: // Test parity
|
||||
begin
|
||||
if(KB_CLK)
|
||||
begin
|
||||
if(KB_DATA == PARITY)
|
||||
STATE <= 8'h06;
|
||||
else
|
||||
begin
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
if(SCAN == 8'hE0)
|
||||
begin
|
||||
EXTENDED <= 1'b1;
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
else
|
||||
if(SCAN == 8'hF0)
|
||||
begin
|
||||
PRESSED_N <= 1'b1;
|
||||
STATE <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
RX_SCAN <= SCAN;
|
||||
RX_PRESSED <= ~PRESSED_N;
|
||||
RX_EXTENDED <= EXTENDED;
|
||||
PRESSED_N <= 1'b0;
|
||||
EXTENDED <= 1'b0;
|
||||
STATE <= 8'h07;
|
||||
end
|
||||
end
|
||||
8'h07:
|
||||
STATE <= 8'h00;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user