1
0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 00:52:09 +00:00

Update mc6809.qip

This commit is contained in:
Gehstock 2020-05-13 16:48:20 +02:00
parent 598949923b
commit a34b1d21d8

View File

@ -1,4 +1,4 @@
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) cpu09l_128a.vhd ]
set_global_assignment -name VERILOG [file join $::quartus(qip_path) mc6809.v ]
set_global_assignment -name VERILOG [file join $::quartus(qip_path) mc6809i.v ]
set_global_assignment -name VERILOG [file join $::quartus(qip_path) mc6809is.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809i.v ]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mc6809is.v ]