New Core ZigZag

2026-03-10 04:24:25 +00:00 · 2018-12-20 15:06:04 +01:00
parent 532c451254
commit a42e87b2c2
45 changed files with 10978 additions and 1 deletions
--- a/Hardware/ReadMe.txt
+++ b/Hardware/ReadMe.txt
@@ -3,4 +3,5 @@ Games that should work on this hardware
 Maze Invaders 
 Millipede (2xPokey)
 Tube Chase / Tunnel Hunt / Vertigo (2xPokey)
-Warlords
+Warlords
+Bulls Eye Darts
--- a/Arcade_MiST/Galaxian
+++ b/Arcade_MiST/Galaxian
--- a/Hardware/ZigZag_MiST/README.txt
+++ b/Hardware/ZigZag_MiST/README.txt
@@ -0,0 +1,23 @@
+---------------------------------------------------------------------------------
+-- 
+-- Arcade: ZigZag port to MiST by Gehstock
+-- 20 December 2018
+-- 
+---------------------------------------------------------------------------------
+-- A simulation model of Galaxian hardware
+-- Copyright(c) 2004 Katsumi Degawa
+---------------------------------------------------------------------------------
+-- 
+-- Only controls are rotated on VGA output.
+-- 
+-- 
+-- Keyboard inputs :
+--
+--   F2         : Coin + Start 2 players
+--   F1         : Coin + Start 1 player
+--   SPACE 	: Fire
+--   ARROW KEYS : Movements
+--
+-- Joystick support.
+-- 
+---------------------------------------------------------------------------------
--- a/Hardware/ZigZag_MiST/Release/ZigZag.rbf
+++ b/Hardware/ZigZag_MiST/Release/ZigZag.rbf
--- a/Hardware/ZigZag_MiST/ZigZag.qpf
+++ b/Hardware/ZigZag_MiST/ZigZag.qpf
@@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 20:32:02  December 08, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "20:32:02  December 08, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "ZigZag"
+PROJECT_REVISION = "Galaxian"
--- a/Hardware/ZigZag_MiST/ZigZag.qsf
+++ b/Hardware/ZigZag_MiST/ZigZag.qsf
@@ -0,0 +1,179 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:56:28  December 20, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		ZigZag_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30  APRIL 20, 2017"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ZigZag_MiST.sv
+set_global_assignment -name VHDL_FILE rtl/ZigZag.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_video.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_stars.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_sprite.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_logic.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_ld_pls.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_inport.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_hv_count.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_col_pal.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_clut.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_bram.vhd
+set_global_assignment -name VHDL_FILE rtl/mc_adec.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80as.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Reg.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_Pack.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_MCode.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80_ALU.vhd
+set_global_assignment -name VHDL_FILE rtl/cpu/T80.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ym2149.sv
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VHDL_FILE rtl/pll.vhd
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/keyboard.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name TOP_LEVEL_ENTITY ZigZag_MiST
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# -------------------------
+# start ENTITY(ZigZag_MiST)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+		set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+		set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+		set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(ZigZag_MiST)
+# -----------------------
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/Hardware/ZigZag_MiST/clean.bat
+++ b/Hardware/ZigZag_MiST/clean.bat
@@ -0,0 +1,37 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+cd sys
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+cd ..
+for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+
+pause
--- a/Hardware/ZigZag_MiST/rtl/Rom/col.hex
+++ b/Hardware/ZigZag_MiST/rtl/Rom/col.hex
@@ -0,0 +1,3 @@
+:1000000000C7F03F00DBC63800F0151F00F60607FA
+:10001000009107F600F0FE07003807FE00073FFEDC
+:00000001FF
--- a/Hardware/ZigZag_MiST/rtl/Rom/h.hex
+++ b/Hardware/ZigZag_MiST/rtl/Rom/h.hex
@@ -0,0 +1,257 @@
+:10000000387CC282867C38000202FEFE420200007A
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--- a/Hardware/ZigZag_MiST/rtl/Rom/k.hex
+++ b/Hardware/ZigZag_MiST/rtl/Rom/k.hex
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--- a/Hardware/ZigZag_MiST/rtl/Rom/prog.hex
+++ b/Hardware/ZigZag_MiST/rtl/Rom/prog.hex
--- a/Hardware/ZigZag_MiST/rtl/ZigZag.vhd
+++ b/Hardware/ZigZag_MiST/rtl/ZigZag.vhd
@@ -0,0 +1,369 @@
+------------------------------------------------------------------------------
+-- FPGA ZigZag
+--
+-- Version  downto  2.50
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important  not
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004- 4-30  galaxian modify by K.DEGAWA
+-- 2004- 5- 6  first release.
+-- 2004- 8-23  Improvement with T80-IP.
+-- 2004- 9-22  The problem which missile didn't sometimes come out from was improved.
+------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity ZigZag is
+	port(
+		W_CLK_12M  : in  std_logic;
+		W_CLK_6M   : in  std_logic;
+
+		I_COIN1    : in  std_logic;   --  active high
+		I_COIN2    : in  std_logic;   --  active high
+		I_LEFT     : in  std_logic;   --  active high
+		I_RIGHT    : in  std_logic;   --  active high
+		I_UP       : in  std_logic;   --  active high
+		I_DOWN     : in  std_logic;   --  active high
+		I_FIRE     : in  std_logic;   --  active high
+		I_1P_START : in  std_logic;   --  active high
+		I_2P_START : in  std_logic;   --  active high
+		I_RESET    : in  std_logic;
+
+		W_R        : out std_logic_vector(2 downto 0);
+		W_G        : out std_logic_vector(2 downto 0);
+		W_B        : out std_logic_vector(2 downto 0);
+		HBLANK     : out std_logic;
+		VBLANK     : out std_logic;
+		W_H_SYNC   : out std_logic;
+		W_V_SYNC   : out std_logic;
+		O_AUDIO    : out std_logic_vector(9 downto 0)
+	);
+end;
+
+architecture RTL of ZigZag is
+	--    CPU ADDRESS BUS
+	signal W_A                : std_logic_vector(15 downto 0) := (others => '0');
+	--    CPU IF
+	signal W_CPU_CLK          : std_logic := '0';
+	signal W_CPU_MREQn        : std_logic := '0';
+	signal W_CPU_NMIn         : std_logic := '0';
+	signal W_CPU_RDn          : std_logic := '0';
+	signal W_CPU_RFSHn        : std_logic := '0';
+	signal W_CPU_WAITn        : std_logic := '0';
+	signal W_CPU_WRn          : std_logic := '0';
+	signal W_CPU_WR           : std_logic := '0';
+	signal W_RESETn           : std_logic := '0';
+	signal W_ROM_SWP          : std_logic := '0';
+	-------- H and V COUNTER -------------------------
+	signal W_C_BLn            : std_logic := '0';
+	signal W_C_BLnX           : std_logic := '0';
+	signal W_C_BLXn           : std_logic := '0';
+	signal W_H_BL             : std_logic := '0';
+	signal W_H_SYNC_int       : std_logic := '0';
+	signal W_V_BLn            : std_logic := '0';
+	signal W_V_BL2n           : std_logic := '0';
+	signal W_V_SYNC_int       : std_logic := '0';
+	signal W_H_CNT            : std_logic_vector(8 downto 0) := (others => '0');
+	signal W_V_CNT            : std_logic_vector(7 downto 0) := (others => '0');
+	-------- CPU RAM  ----------------------------
+	signal W_CPU_RAM_DO       : std_logic_vector(7 downto 0) := (others => '0');
+	-------- ADDRESS DECDER ----------------------
+	signal W_BD_G             : std_logic := '0';
+	signal W_CPU_RAM_CS       : std_logic := '0';
+	signal W_CPU_RAM_RD       : std_logic := '0';
+--	signal W_CPU_RAM_WR       : std_logic := '0';
+	signal W_CPU_ROM_CS       : std_logic := '0';
+	signal W_DIP_OE           : std_logic := '0';
+	signal W_H_FLIP           : std_logic := '0';
+	signal W_DRIVER_WE        : std_logic := '0';
+	signal W_OBJ_RAM_RD       : std_logic := '0';
+	signal W_OBJ_RAM_RQ       : std_logic := '0';
+	signal W_OBJ_RAM_WR       : std_logic := '0';
+	signal W_PITCH            : std_logic := '0';
+	signal W_SOUND_WE         : std_logic := '0';
+	signal W_STARS_ON         : std_logic := '0';
+	signal W_STARS_OFFn       : std_logic := '0';
+	signal W_SW0_OE           : std_logic := '0';
+	signal W_SW1_OE           : std_logic := '0';
+	signal W_V_FLIP           : std_logic := '0';
+	signal W_VID_RAM_RD       : std_logic := '0';
+	signal W_VID_RAM_WR       : std_logic := '0';
+	signal W_WDR_OE           : std_logic := '0';
+	--------- INPORT -----------------------------
+	signal W_SW_DO            : std_logic_vector( 7 downto 0) := (others => '0');
+	--------- VIDEO  -----------------------------
+	signal W_VID_DO           : std_logic_vector( 7 downto 0) := (others => '0');
+	-----  DATA I/F -------------------------------------
+	signal W_CPU_ROM_DO       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_CPU_ROM_DOB      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_BDO              : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_BDI              : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_CPU_RAM_CLK      : std_logic := '0';
+	signal W_VOL1             : std_logic := '0';
+	signal W_VOL2             : std_logic := '0';
+	signal W_FIRE             : std_logic := '0';
+	signal W_HIT              : std_logic := '0';
+	signal W_FS               : std_logic_vector( 2 downto 0) := (others => '0');
+
+	signal blx_comb           : std_logic := '0';
+	signal W_1VF              : std_logic := '0';
+	signal W_256HnX           : std_logic := '0';
+	signal W_8HF              : std_logic := '0';
+	signal W_DAC_A            : std_logic := '0';
+	signal W_DAC_B            : std_logic := '0';
+	signal W_MISSILEn         : std_logic := '0';
+	signal W_SHELLn           : std_logic := '0';
+	signal W_MS_D             : std_logic := '0';
+	signal W_MS_R             : std_logic := '0';
+	signal W_MS_G             : std_logic := '0';
+	signal W_MS_B             : std_logic := '0';
+
+	signal new_sw             : std_logic_vector( 2 downto 0) := (others => '0');
+	signal in_game            : std_logic_vector( 1 downto 0) := (others => '0');
+	signal ROM_D              : std_logic_vector( 7 downto 0) := (others => '0');
+	signal rst_count          : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_COL              : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_STARS_B          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_STARS_G          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_STARS_R          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_VID              : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_VIDEO_B          : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_VIDEO_G          : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_VIDEO_R          : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_WAV_A0           : std_logic_vector(18 downto 0) := (others => '0');
+	signal W_WAV_A1           : std_logic_vector(18 downto 0) := (others => '0');
+	signal W_WAV_A2           : std_logic_vector(18 downto 0) := (others => '0');
+	signal W_WAV_D0           : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_WAV_D1           : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_WAV_D2           : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_DAC              : std_logic_vector( 3 downto 0) := (others => '0');
+	signal PSG_EN             : std_logic;
+	signal PSG_D              : std_logic_vector(7 downto 0);
+	signal PSG_A,PSG_B,PSG_C  : std_logic_vector(7 downto 0);
+	
+	component ym2149
+	port (
+		CLK       : in  std_logic;
+		CE        : in  std_logic;
+		RESET     : in  std_logic;
+		BDIR      : in  std_logic;
+		BC        : in  std_logic;
+		DI        : in  std_logic_vector(7 downto 0);
+		DO        : out std_logic_vector(7 downto 0);
+		CHANNEL_A : out std_logic_vector(7 downto 0);
+		CHANNEL_B : out std_logic_vector(7 downto 0);
+		CHANNEL_C : out std_logic_vector(7 downto 0)
+	);
+	end component;
+	
+begin
+
+mc_vid : entity work.MC_VIDEO
+	port map(
+		I_CLK_12M     => W_CLK_12M,
+		I_CLK_6M      => W_CLK_6M,
+		I_H_CNT       => W_H_CNT,
+		I_V_CNT       => W_V_CNT,
+		I_H_FLIP      => W_H_FLIP,
+		I_V_FLIP      => W_V_FLIP,
+		I_V_BLn       => W_V_BLn,
+		I_C_BLn       => W_C_BLn,
+		I_A           => W_A(9 downto 0),
+		I_BD          => W_BDI,
+		I_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
+		I_OBJ_RAM_RD  => W_OBJ_RAM_RD,
+		I_OBJ_RAM_WR  => W_OBJ_RAM_WR,
+		I_VID_RAM_RD  => W_VID_RAM_RD,
+		I_VID_RAM_WR  => W_VID_RAM_WR,
+		O_C_BLnX      => W_C_BLnX,
+		O_BD          => W_VID_DO,
+		O_VID         => W_VID,
+		O_COL         => W_COL
+	);
+
+
+	cpu : entity work.T80as
+	port map (
+		RESET_n       => W_RESETn,
+		CLK_n         => W_CPU_CLK,
+		WAIT_n        => W_CPU_WAITn,
+		INT_n         => '1',
+		NMI_n         => W_CPU_NMIn,
+		BUSRQ_n       => '1',
+		MREQ_n        => W_CPU_MREQn,
+		RD_n          => W_CPU_RDn,
+		WR_n          => W_CPU_WRn,
+		RFSH_n        => W_CPU_RFSHn,
+		A             => W_A,
+		DI            => W_BDO,
+		DO            => W_BDI,
+		M1_n          => open,
+		IORQ_n        => open,
+		HALT_n        => open,
+		BUSAK_n       => open,
+		DOE           => open
+	);
+
+	mc_cpu_ram : entity work.MC_CPU_RAM
+	port map (
+		I_CLK         => W_CPU_RAM_CLK,
+		I_ADDR        => W_A(9 downto 0),
+		I_D           => W_BDI,
+		I_WE          => W_CPU_WR,
+		I_OE          => W_CPU_RAM_RD,
+		O_D           => W_CPU_RAM_DO
+	);
+
+mc_adec : entity work.MC_ADEC
+	port map(
+		I_CLK_12M     => W_CLK_12M,
+		I_CLK_6M      => W_CLK_6M,
+		I_CPU_CLK     => W_CPU_CLK,
+		I_RSTn        => W_RESETn,
+
+		I_CPU_A       => W_A,
+		I_CPU_D       => W_BDI(0),
+		I_MREQn       => W_CPU_MREQn,
+		I_RFSHn       => W_CPU_RFSHn,
+		I_RDn         => W_CPU_RDn,
+		I_WRn         => W_CPU_WRn,
+		I_H_BL        => W_H_BL,
+		I_V_BLn       => W_V_BLn,
+
+		O_WAITn       => W_CPU_WAITn,
+		O_NMIn        => W_CPU_NMIn,
+		O_CPU_ROM_CS  => W_CPU_ROM_CS,
+		O_CPU_RAM_RD  => W_CPU_RAM_RD,
+		O_CPU_RAM_CS  => W_CPU_RAM_CS,
+		O_OBJ_RAM_RD  => W_OBJ_RAM_RD,
+		O_OBJ_RAM_WR  => W_OBJ_RAM_WR,
+		O_OBJ_RAM_RQ  => W_OBJ_RAM_RQ,
+		O_VID_RAM_RD  => W_VID_RAM_RD,
+		O_VID_RAM_WR  => W_VID_RAM_WR,
+		O_SW0_OE      => W_SW0_OE,
+		O_SW1_OE      => W_SW1_OE,
+		O_DIP_OE      => W_DIP_OE,
+		O_H_FLIP      => W_H_FLIP,
+		O_V_FLIP      => W_V_FLIP,
+		O_ROM_SWP     => W_ROM_SWP
+	);
+
+-- active high buttons
+	mc_inport : entity work.MC_INPORT
+	port map (
+		I_COIN1       => I_COIN1,
+		I_COIN2       => I_COIN2,
+		I_1P_START    => I_1P_START,
+		I_2P_START    => I_2P_START,
+		I_LEFT        => I_LEFT,
+		I_RIGHT       => I_RIGHT,
+		I_UP          => I_UP,
+		I_DOWN        => I_DOWN,
+		I_FIRE        => I_FIRE,
+
+		I_SW0_OE      => W_SW0_OE,
+		I_SW1_OE      => W_SW1_OE,
+		I_DIP_OE      => W_DIP_OE,
+		O_D           => W_SW_DO
+	);
+
+	mc_hv : entity work.MC_HV_COUNT
+	port map(
+		I_CLK         => W_CLK_6M,
+		I_RSTn        => W_RESETn,
+		O_H_CNT       => W_H_CNT,
+		O_H_SYNC      => W_H_SYNC_int,
+		O_H_BL        => W_H_BL,
+		O_V_CNT       => W_V_CNT,
+		O_V_SYNC      => W_V_SYNC_int,
+		O_V_BL2n      => W_V_BL2n,
+		O_V_BLn       => W_V_BLn,
+		O_C_BLn       => W_C_BLn
+	);
+
+	mc_col_pal : entity work.MC_COL_PAL
+	port map(
+		I_CLK_6M      => W_CLK_6M,
+		I_VID         => W_VID,
+		I_COL         => W_COL,
+		O_R           => W_R,
+		O_G           => W_G,
+		O_B           => W_B
+	);
+
+	
+mc_roms1 : entity work.sprom
+	generic map (
+		init_file	=>  "./Rom/prog.hex",
+		widthad_a	=> 14,
+		width_a		=> 8)
+	port map (
+		address	=>  W_A(13) & (W_A(12) xor (W_ROM_SWP and W_A(13))) & W_A(11 downto 0),
+		clock		=> W_CLK_12M, 
+		q			=> W_CPU_ROM_DO
+	);
+
+-------- VIDEO  -----------------------------
+	W_V_SYNC <= not W_V_SYNC_int;
+	W_H_SYNC <= not W_H_SYNC_int;
+
+	process(W_CLK_6M)
+	begin
+		if rising_edge(W_CLK_6M) then
+			HBLANK   <= not W_C_BLnX;
+			VBLANK   <= not W_V_BL2n;
+		end if;
+	end process;
+
+
+-----  CPU I/F  -------------------------------------
+
+	W_CPU_CLK     <= W_H_CNT(0);
+	W_CPU_RAM_CLK <= W_CLK_12M and W_CPU_RAM_CS;
+
+	W_CPU_ROM_DOB <= W_CPU_ROM_DO when W_CPU_ROM_CS = '1' else (others=>'0');
+
+	W_RESETn  <= not I_RESET;
+	W_BDO     <= W_SW_DO  or W_VID_DO or W_CPU_RAM_DO or W_CPU_ROM_DOB ;
+	W_CPU_WR  <= not W_CPU_WRn;
+
+-------------------------------------------------------------------------------
+
+	PSG_EN <= '1' when W_A(15 downto 11) = "01001" and W_A(9) = '0' and W_CPU_MREQn = '0' and W_CPU_WRn = '0' else '0';
+	
+	process(W_CPU_CLK)
+	begin
+		if rising_edge(W_CPU_CLK) then
+			if PSG_EN = '1' and W_A(8) = '1' then
+				PSG_D <= W_A(7 downto 0);
+			end if;
+		end if;
+	end process;
+
+	O_AUDIO <= ("00" & PSG_A) + ("00" & PSG_B) + ("00" & PSG_C);
+
+	psg : ym2149
+	port map
+	(
+		CLK       => W_CPU_CLK,
+		CE        => '1',
+		RESET     => I_RESET,
+
+		BDIR      => PSG_EN and W_A(0) and not W_A(8),
+		BC        => W_A(1),
+		DI        => PSG_D,
+
+		CHANNEL_A => PSG_A,
+		CHANNEL_B => PSG_B,
+		CHANNEL_C => PSG_C
+	);
+
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv
+++ b/Hardware/ZigZag_MiST/rtl/ZigZag_MiST.sv
@@ -0,0 +1,182 @@
+//============================================================================
+//  Arcade: ZigZag
+//
+//  Port to MiST
+//  Copyright (C) 2018 Sorgelig
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module ZigZag_MiST
+(
+	output        LED,
+	output  [5:0] VGA_R,
+	output  [5:0] VGA_G,
+	output  [5:0] VGA_B,
+	output        VGA_HS,
+	output        VGA_VS,
+	output        AUDIO_L,
+	output        AUDIO_R,
+	input         SPI_SCK,
+	output        SPI_DO,
+	input         SPI_DI,
+	input         SPI_SS2,
+	input         SPI_SS3,
+	input         CONF_DATA0,
+	input         CLOCK_27
+);
+
+`include "rtl\build_id.v" 
+
+localparam CONF_STR = {
+	"ZigZag;;",
+	"O2,Joystick Control,Upright,Normal;",
+	"O34,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;",
+	"T6,Reset;",
+	"V,v1.10.",`BUILD_DATE
+};
+
+wire [31:0] status;
+wire  [1:0] buttons;
+wire  [1:0] switches;
+wire  [9:0] kbjoy;
+wire  [7:0] joystick_0;
+wire  [7:0] joystick_1;
+wire        scandoubler_disable;
+wire        ypbpr;
+wire        ps2_kbd_clk, ps2_kbd_data;
+
+assign LED = 1;
+
+wire clk_24, clk_18, clk_12, clk_6;
+wire pll_locked;
+
+pll pll
+(
+	.inclk0(CLOCK_27),
+	.areset(0),
+	.c0(clk_24),
+	.c1(clk_18),
+	.c2(clk_12),
+	.c3(clk_6)
+);
+
+wire m_up     = status[2] ? kbjoy[6] | joystick_0[1] | joystick_1[1] : kbjoy[4] | joystick_0[3] | joystick_1[3];
+wire m_down   = status[2] ? kbjoy[7] | joystick_0[0] | joystick_1[0] : kbjoy[5] | joystick_0[2] | joystick_1[2];
+wire m_left   = status[2] ? kbjoy[5] | joystick_0[2] | joystick_1[2] : kbjoy[6] | joystick_0[1] | joystick_1[1];
+wire m_right  = status[2] ? kbjoy[4] | joystick_0[3] | joystick_1[3] : kbjoy[7] | joystick_0[0] | joystick_1[0];
+
+wire m_fire   = kbjoy[0] | joystick_0[4] | joystick_1[4];
+wire m_start1 = kbjoy[1];
+wire m_start2 = kbjoy[2];
+wire m_coin   = kbjoy[3];
+
+ZigZag ZigZag
+(
+	.W_CLK_12M(clk_12),
+	.W_CLK_6M(clk_6),
+	.I_RESET(status[0] | status[6] | buttons[1]),
+	.I_COIN1(m_coin),
+	.I_COIN2(0),
+	.I_LEFT(m_left),
+	.I_RIGHT(m_right),
+	.I_UP(m_up),
+	.I_DOWN(m_down),
+	.I_FIRE(m_fire),
+	.I_1P_START(m_start1),
+	.I_2P_START(m_start2),
+	.W_R(r),
+	.W_G(g),
+	.W_B(b),
+	.W_H_SYNC(hs),
+	.W_V_SYNC(vs),
+	.HBLANK(hblank),
+	.VBLANK(vblank),
+	.O_AUDIO(audio)
+);
+
+wire [9:0] audio;
+
+dac #(
+	.msbi_g(15))
+dac (
+	.clk_i(clk_24),
+	.res_n_i(1),
+	.dac_i({audio, 6'd0}),
+	.dac_o(AUDIO_L)
+	);
+
+assign AUDIO_R = AUDIO_L;
+
+wire hs, vs;
+wire [2:0] r, g, b;
+wire hblank, vblank;
+wire blankn = ~(hblank | vblank);
+video_mixer #(.LINE_LENGTH(480), .HALF_DEPTH(1)) video_mixer
+(
+	.clk_sys(clk_24),
+	.ce_pix(clk_6),
+	.ce_pix_actual(clk_6),
+	.SPI_SCK(SPI_SCK),
+	.SPI_SS3(SPI_SS3),
+	.SPI_DI(SPI_DI),
+	.R(blankn?r:"000"),
+	.G(blankn?g:"000"),
+	.B(blankn?b:"000"),
+	.HSync(hs),
+	.VSync(vs),
+	.VGA_R(VGA_R),
+	.VGA_G(VGA_G),
+	.VGA_B(VGA_B),
+	.VGA_VS(VGA_VS),
+	.VGA_HS(VGA_HS),
+	.scandoubler_disable(scandoubler_disable),
+	.scanlines(scandoubler_disable ? 2'b00 : {status[4:3] == 2'b11, status[4:3] == 2'b10, status[4:3] == 2'b01}),
+	.hq2x(0),
+	.ypbpr_full(1),
+	.line_start(0),
+	.mono(0)
+);
+
+mist_io #(.STRLEN(($size(CONF_STR)>>3))) mist_io
+(
+	.clk_sys        (clk_24   	     ),
+	.conf_str       (CONF_STR       ),
+	.SPI_SCK        (SPI_SCK        ),
+	.CONF_DATA0     (CONF_DATA0     ),
+	.SPI_SS2			 (SPI_SS2        ),
+	.SPI_DO         (SPI_DO         ),
+	.SPI_DI         (SPI_DI         ),
+	.buttons        (buttons        ),
+	.switches   	 (switches       ),
+	.scandoubler_disable(scandoubler_disable),
+	.ypbpr          (ypbpr          ),
+	.ps2_kbd_clk    (ps2_kbd_clk    ),
+	.ps2_kbd_data   (ps2_kbd_data   ),
+	.joystick_0   	 (joystick_0     ),
+	.joystick_1     (joystick_1     ),
+	.status         (status         )
+);
+
+keyboard keyboard(
+	.clk(clk_24),
+	.reset(0),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data),
+	.joystick(kbjoy)
+	);
+
+
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/build_id.tcl
+++ b/Hardware/ZigZag_MiST/rtl/build_id.tcl
@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "rtl/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog
--- a/Hardware/ZigZag_MiST/rtl/build_id.v
+++ b/Hardware/ZigZag_MiST/rtl/build_id.v
@@ -0,0 +1,2 @@
+`define BUILD_DATE "181220"
+`define BUILD_TIME "145810"
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80.vhd
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80_ALU.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80_ALU.vhd
@@ -0,0 +1,371 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0238 : Fixed zero flag for 16 bit SBC and ADC
+--
+--      0240 : Added GB operations
+--
+--      0242 : Cleanup
+--
+--      0247 : Cleanup
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_ALU is
+	generic(
+		Mode : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		Arith16	: in  std_logic;
+		Z16		: in  std_logic;
+		ALU_Op	: in  std_logic_vector(3 downto 0);
+		IR			: in  std_logic_vector(5 downto 0);
+		ISet		: in  std_logic_vector(1 downto 0);
+		BusA		: in  std_logic_vector(7 downto 0);
+		BusB		: in  std_logic_vector(7 downto 0);
+		F_In		: in  std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
+	);
+end T80_ALU;
+
+architecture rtl of T80_ALU is
+
+	procedure AddSub(A		: std_logic_vector;
+					 B				: std_logic_vector;
+					 Sub			: std_logic;
+					 Carry_In	: std_logic;
+			  signal Res		: out std_logic_vector;
+			  signal Carry		: out std_logic) is
+
+		variable B_i			: unsigned(A'length - 1 downto 0);
+		variable Res_i			: unsigned(A'length + 1 downto 0);
+	begin
+		if Sub = '1' then
+			B_i := not unsigned(B);
+		else
+			B_i :=     unsigned(B);
+		end if;
+
+		Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
+		Carry <= Res_i(A'length + 1);
+		Res <= std_logic_vector(Res_i(A'length downto 1));
+	end;
+
+	-- AddSub variables (temporary signals)
+	signal UseCarry                : std_logic;
+	signal Carry7_v                : std_logic;
+	signal Overflow_v              : std_logic;
+	signal HalfCarry_v             : std_logic;
+	signal Carry_v                 : std_logic;
+	signal Q_v                     : std_logic_vector(7 downto 0);
+
+	signal BitMask                 : std_logic_vector(7 downto 0);
+
+begin
+
+	with IR(5 downto 3) select BitMask <= "00000001" when "000",
+										  "00000010" when "001",
+										  "00000100" when "010",
+										  "00001000" when "011",
+										  "00010000" when "100",
+										  "00100000" when "101",
+										  "01000000" when "110",
+										  "10000000" when others;
+
+	UseCarry <= not ALU_Op(2) and ALU_Op(0);
+	AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
+	AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
+	AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
+
+	-- bug fix - parity flag is just parity for 8080, also overflow for Z80
+	process (Carry_v, Carry7_v, Q_v)
+	begin
+		if(Mode=2) then
+			OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
+					   Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7));  else
+			OverFlow_v <= Carry_v xor Carry7_v;
+		end if;
+	end process;
+
+	process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
+		variable Q_t : std_logic_vector(7 downto 0);
+		variable DAA_Q : unsigned(8 downto 0);
+	begin
+		Q_t := "--------";
+		F_Out <= F_In;
+		DAA_Q := "---------";
+		case ALU_Op is
+		when "0000" | "0001" |  "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_C) <= '0';
+			case ALU_OP(2 downto 0) is
+			when "000" | "001" => -- ADD, ADC
+				Q_t := Q_v;
+				F_Out(Flag_C) <= Carry_v;
+				F_Out(Flag_H) <= HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "010" | "011" | "111" => -- SUB, SBC, CP
+				Q_t := Q_v;
+				F_Out(Flag_N) <= '1';
+				F_Out(Flag_C) <= not Carry_v;
+				F_Out(Flag_H) <= not HalfCarry_v;
+				F_Out(Flag_P) <= OverFlow_v;
+			when "100" => -- AND
+				Q_t(7 downto 0) := BusA and BusB;
+				F_Out(Flag_H) <= '1';
+			when "101" => -- XOR
+				Q_t(7 downto 0) := BusA xor BusB;
+				F_Out(Flag_H) <= '0';
+			when others => -- OR "110"
+				Q_t(7 downto 0) := BusA or BusB;
+				F_Out(Flag_H) <= '0';
+			end case;
+			if ALU_Op(2 downto 0) = "111" then -- CP
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			else
+				F_Out(Flag_X) <= Q_t(3);
+				F_Out(Flag_Y) <= Q_t(5);
+			end if;
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				if Z16 = '1' then
+					F_Out(Flag_Z) <= F_In(Flag_Z);      -- 16 bit ADC,SBC
+				end if;
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			case ALU_Op(2 downto 0) is
+			when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
+			when others =>
+				F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+					Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			end case;
+			if Arith16 = '1' then
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+				F_Out(Flag_P) <= F_In(Flag_P);
+			end if;
+		when "1100" =>
+			-- DAA
+			F_Out(Flag_H) <= F_In(Flag_H);
+			F_Out(Flag_C) <= F_In(Flag_C);
+			DAA_Q(7 downto 0) := unsigned(BusA);
+			DAA_Q(8) := '0';
+			if F_In(Flag_N) = '0' then
+				-- After addition
+				-- Alow > 9 or H = 1
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if (DAA_Q(3 downto 0) > 9) then
+						F_Out(Flag_H) <= '1';
+					else
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q := DAA_Q + 6;
+				end if;
+				-- new Ahigh > 9 or C = 1
+				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q + 96; -- 0x60
+				end if;
+			else
+				-- After subtraction
+				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+					if DAA_Q(3 downto 0) > 5 then
+						F_Out(Flag_H) <= '0';
+					end if;
+					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+				end if;
+				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+					DAA_Q := DAA_Q - 352; -- 0x160
+				end if;
+			end if;
+			F_Out(Flag_X) <= DAA_Q(3);
+			F_Out(Flag_Y) <= DAA_Q(5);
+			F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
+			Q_t := std_logic_vector(DAA_Q(7 downto 0));
+			if DAA_Q(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= DAA_Q(7);
+			F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
+				DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
+		when "1101" | "1110" =>
+			-- RLD, RRD
+			Q_t(7 downto 4) := BusA(7 downto 4);
+			if ALU_Op(0) = '1' then
+				Q_t(3 downto 0) := BusB(7 downto 4);
+			else
+				Q_t(3 downto 0) := BusB(3 downto 0);
+			end if;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_S) <= Q_t(7);
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+		when "1001" =>
+			-- BIT
+			Q_t(7 downto 0) := BusB and BitMask;
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+				F_Out(Flag_P) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+				F_Out(Flag_P) <= '0';
+			end if;
+			F_Out(Flag_H) <= '1';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= '0';
+			F_Out(Flag_Y) <= '0';
+			if IR(2 downto 0) /= "110" then
+				F_Out(Flag_X) <= BusB(3);
+				F_Out(Flag_Y) <= BusB(5);
+			end if;
+		when "1010" =>
+			-- SET
+			Q_t(7 downto 0) := BusB or BitMask;
+		when "1011" =>
+			-- RES
+			Q_t(7 downto 0) := BusB and not BitMask;
+		when "1000" =>
+			-- ROT
+			case IR(5 downto 3) is
+			when "000" => -- RLC
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := BusA(7);
+				F_Out(Flag_C) <= BusA(7);
+			when "010" => -- RL
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(7);
+			when "001" => -- RRC
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(0);
+				F_Out(Flag_C) <= BusA(0);
+			when "011" => -- RR
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := F_In(Flag_C);
+				F_Out(Flag_C) <= BusA(0);
+			when "100" => -- SLA
+				Q_t(7 downto 1) := BusA(6 downto 0);
+				Q_t(0) := '0';
+				F_Out(Flag_C) <= BusA(7);
+			when "110" => -- SLL (Undocumented) / SWAP
+				if Mode = 3 then
+					Q_t(7 downto 4) := BusA(3 downto 0);
+					Q_t(3 downto 0) := BusA(7 downto 4);
+					F_Out(Flag_C) <= '0';
+				else
+					Q_t(7 downto 1) := BusA(6 downto 0);
+					Q_t(0) := '1';
+					F_Out(Flag_C) <= BusA(7);
+				end if;
+			when "101" => -- SRA
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := BusA(7);
+				F_Out(Flag_C) <= BusA(0);
+			when others => -- SRL
+				Q_t(6 downto 0) := BusA(7 downto 1);
+				Q_t(7) := '0';
+				F_Out(Flag_C) <= BusA(0);
+			end case;
+			F_Out(Flag_H) <= '0';
+			F_Out(Flag_N) <= '0';
+			F_Out(Flag_X) <= Q_t(3);
+			F_Out(Flag_Y) <= Q_t(5);
+			F_Out(Flag_S) <= Q_t(7);
+			if Q_t(7 downto 0) = "00000000" then
+				F_Out(Flag_Z) <= '1';
+			else
+				F_Out(Flag_Z) <= '0';
+			end if;
+			F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
+				Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
+			if ISet = "00" then
+				F_Out(Flag_P) <= F_In(Flag_P);
+				F_Out(Flag_S) <= F_In(Flag_S);
+				F_Out(Flag_Z) <= F_In(Flag_Z);
+			end if;
+		when others =>
+			null;
+		end case;
+		Q <= Q_t;
+	end process;
+end;
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80_MCode.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80_MCode.vhd
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80_Pack.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80_Pack.vhd
@@ -0,0 +1,220 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0242
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package T80_Pack is
+
+	component T80
+	generic(
+		Mode			: integer := 0;    -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait		: integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C		: integer := 0;
+		Flag_N		: integer := 1;
+		Flag_P		: integer := 2;
+		Flag_X		: integer := 3;
+		Flag_H		: integer := 4;
+		Flag_Y		: integer := 5;
+		Flag_Z		: integer := 6;
+		Flag_S		: integer := 7
+	);
+	port(
+		RESET_n		: in  std_logic;
+		CLK_n			: in  std_logic;
+		CEN			: in  std_logic;
+		WAIT_n		: in  std_logic;
+		INT_n			: in  std_logic;
+		NMI_n			: in  std_logic;
+		BUSRQ_n		: in  std_logic;
+		M1_n			: out std_logic;
+		IORQ			: out std_logic;
+		NoRead		: out std_logic;
+		Write			: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A				: out std_logic_vector(15 downto 0);
+		DInst			: in  std_logic_vector(7 downto 0);
+		DI				: in  std_logic_vector(7 downto 0);
+		DO				: out std_logic_vector(7 downto 0);
+		MC				: out std_logic_vector(2 downto 0);
+		TS				: out std_logic_vector(2 downto 0);
+		IntCycle_n	: out std_logic;
+		IntE			: out std_logic;
+		Stop			: out std_logic
+	);
+	end component;
+
+	component T80_Reg
+	port(
+		Clk			: in  std_logic;
+		CEN			: in  std_logic;
+		WEH			: in  std_logic;
+		WEL			: in  std_logic;
+		AddrA			: in  std_logic_vector(2 downto 0);
+		AddrB			: in  std_logic_vector(2 downto 0);
+		AddrC			: in  std_logic_vector(2 downto 0);
+		DIH			: in  std_logic_vector(7 downto 0);
+		DIL			: in  std_logic_vector(7 downto 0);
+		DOAH			: out std_logic_vector(7 downto 0);
+		DOAL			: out std_logic_vector(7 downto 0);
+		DOBH			: out std_logic_vector(7 downto 0);
+		DOBL			: out std_logic_vector(7 downto 0);
+		DOCH			: out std_logic_vector(7 downto 0);
+		DOCL			: out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+	component T80_MCode
+	generic(
+		Mode   : integer := 0;
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		IR				: in  std_logic_vector(7 downto 0);
+		ISet			: in  std_logic_vector(1 downto 0);
+		MCycle		: in  std_logic_vector(2 downto 0);
+		F				: in  std_logic_vector(7 downto 0);
+		NMICycle		: in  std_logic;
+		IntCycle		: in  std_logic;
+		XY_State		: in  std_logic_vector(1 downto 0);
+		MCycles		: out std_logic_vector(2 downto 0);
+		TStates		: out std_logic_vector(2 downto 0);
+		Prefix		: out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
+		Inc_PC		: out std_logic;
+		Inc_WZ		: out std_logic;
+		IncDec_16	: out std_logic_vector(3 downto 0); -- BC,DE,HL,SP   0 is inc
+		Read_To_Reg	: out std_logic;
+		Read_To_Acc	: out std_logic;
+		Set_BusA_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
+		Set_BusB_To	: out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
+		ALU_Op		: out std_logic_vector(3 downto 0);
+			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
+		Save_ALU		: out std_logic;
+		PreserveC	: out std_logic;
+		Arith16		: out std_logic;
+		Set_Addr_To	: out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
+		IORQ			: out std_logic;
+		Jump			: out std_logic;
+		JumpE			: out std_logic;
+		JumpXY		: out std_logic;
+		Call			: out std_logic;
+		RstP			: out std_logic;
+		LDZ			: out std_logic;
+		LDW			: out std_logic;
+		LDSPHL		: out std_logic;
+		Special_LD	: out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
+		ExchangeDH	: out std_logic;
+		ExchangeRp	: out std_logic;
+		ExchangeAF	: out std_logic;
+		ExchangeRS	: out std_logic;
+		I_DJNZ		: out std_logic;
+		I_CPL			: out std_logic;
+		I_CCF			: out std_logic;
+		I_SCF			: out std_logic;
+		I_RETN		: out std_logic;
+		I_BT			: out std_logic;
+		I_BC			: out std_logic;
+		I_BTR			: out std_logic;
+		I_RLD			: out std_logic;
+		I_RRD			: out std_logic;
+		I_INRC		: out std_logic;
+		SetDI			: out std_logic;
+		SetEI			: out std_logic;
+		IMode			: out std_logic_vector(1 downto 0);
+		Halt			: out std_logic;
+		NoRead		: out std_logic;
+		Write			: out std_logic;
+		XYbit_undoc	: out std_logic
+	);
+	end component;
+
+	component T80_ALU
+	generic(
+		Mode		: integer := 0;
+		Flag_C	: integer := 0;
+		Flag_N	: integer := 1;
+		Flag_P	: integer := 2;
+		Flag_X	: integer := 3;
+		Flag_H	: integer := 4;
+		Flag_Y	: integer := 5;
+		Flag_Z	: integer := 6;
+		Flag_S	: integer := 7
+	);
+	port(
+		Arith16	: in  std_logic;
+		Z16		: in  std_logic;
+		ALU_Op	: in  std_logic_vector(3 downto 0);
+		IR			: in  std_logic_vector(5 downto 0);
+		ISet		: in  std_logic_vector(1 downto 0);
+		BusA		: in  std_logic_vector(7 downto 0);
+		BusB		: in  std_logic_vector(7 downto 0);
+		F_In		: in  std_logic_vector(7 downto 0);
+		Q			: out std_logic_vector(7 downto 0);
+		F_Out		: out std_logic_vector(7 downto 0)
+	);
+	end component;
+
+end;
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80_Reg.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80_Reg.vhd
@@ -0,0 +1,105 @@
+--
+-- T80 Registers, technology independent
+--
+-- Version : 0244
+--
+-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t51/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0242 : Initial release
+--
+--	0244 : Changed to single register file
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity T80_Reg is
+	port(
+		Clk			: in std_logic;
+		CEN			: in std_logic;
+		WEH			: in std_logic;
+		WEL			: in std_logic;
+		AddrA		: in std_logic_vector(2 downto 0);
+		AddrB		: in std_logic_vector(2 downto 0);
+		AddrC		: in std_logic_vector(2 downto 0);
+		DIH			: in std_logic_vector(7 downto 0);
+		DIL			: in std_logic_vector(7 downto 0);
+		DOAH		: out std_logic_vector(7 downto 0);
+		DOAL		: out std_logic_vector(7 downto 0);
+		DOBH		: out std_logic_vector(7 downto 0);
+		DOBL		: out std_logic_vector(7 downto 0);
+		DOCH		: out std_logic_vector(7 downto 0);
+		DOCL		: out std_logic_vector(7 downto 0)
+	);
+end T80_Reg;
+
+architecture rtl of T80_Reg is
+
+	type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
+	signal	RegsH	: Register_Image(0 to 7);
+	signal	RegsL	: Register_Image(0 to 7);
+
+begin
+
+	process (Clk)
+	begin
+		if Clk'event and Clk = '1' then
+			if CEN = '1' then
+				if WEH = '1' then
+					RegsH(to_integer(unsigned(AddrA))) <= DIH;
+				end if;
+				if WEL = '1' then
+					RegsL(to_integer(unsigned(AddrA))) <= DIL;
+				end if;
+			end if;
+		end if;
+	end process;
+
+	DOAH <= RegsH(to_integer(unsigned(AddrA)));
+	DOAL <= RegsL(to_integer(unsigned(AddrA)));
+	DOBH <= RegsH(to_integer(unsigned(AddrB)));
+	DOBL <= RegsL(to_integer(unsigned(AddrB)));
+	DOCH <= RegsH(to_integer(unsigned(AddrC)));
+	DOCL <= RegsL(to_integer(unsigned(AddrC)));
+
+end;
--- a/Hardware/ZigZag_MiST/rtl/cpu/T80as.vhd
+++ b/Hardware/ZigZag_MiST/rtl/cpu/T80as.vhd
@@ -0,0 +1,283 @@
+------------------------------------------------------------------------------
+-- t80as.vhd : The non-tristate signal edition of t80a.vhd
+--
+-- 2003.2.7 non-tristate modification by Tatsuyuki Satoh
+--
+-- 1.separate 'D' to 'DO' and 'DI'.
+-- 2.added 'DOE' to 'DO' enable signal.(data direction)
+-- 3.MREQ_n,IORQ_n,RD_n,WR_n,RFSH_n,A doesn't become the condition of 'Z'. 
+--
+-- There is a mark of "--AS" in all the change points. 
+--
+------------------------------------------------------------------------------
+
+--
+-- Z80 compatible microprocessor core, asynchronous top level
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--	http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--	0208 : First complete release
+--
+--	0211 : Fixed interrupt cycle
+--
+--	0235 : Updated for T80 interface change
+--
+--	0238 : Updated for T80 interface change
+--
+--	0240 : Updated for T80 interface change
+--
+--	0242 : Updated for T80 interface change
+--
+--	0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+entity T80as is
+	generic(
+		Mode : integer := 0	-- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+	);
+	port(
+		RESET_n		: in std_logic;
+		CLK_n		: in std_logic;
+		WAIT_n		: in std_logic;
+		INT_n		: in std_logic;
+		NMI_n		: in std_logic;
+		BUSRQ_n		: in std_logic;
+		M1_n		: out std_logic;
+		MREQ_n		: out std_logic;
+		IORQ_n		: out std_logic;
+		RD_n		: out std_logic;
+		WR_n		: out std_logic;
+		RFSH_n		: out std_logic;
+		HALT_n		: out std_logic;
+		BUSAK_n		: out std_logic;
+		A			: out std_logic_vector(15 downto 0);
+--AS--	D			: inout std_logic_vector(7 downto 0)
+--AS>>
+		DI			: in  std_logic_vector(7 downto 0); 
+		DO			: out std_logic_vector(7 downto 0);
+		DOE			: out std_logic
+--<<AS
+	);
+end T80as;
+
+architecture RTL of T80as is
+
+	signal CEN			: std_logic;
+	signal Reset_s		: std_logic;
+	signal IntCycle_n	: std_logic;
+	signal IORQ			: std_logic;
+	signal NoRead		: std_logic;
+	signal Write		: std_logic;
+	signal MREQ			: std_logic;
+	signal MReq_Inhibit	: std_logic;
+	signal Req_Inhibit	: std_logic;
+	signal RD			: std_logic;
+	signal MREQ_n_i		: std_logic;
+	signal IORQ_n_i		: std_logic;
+	signal RD_n_i		: std_logic;
+	signal WR_n_i		: std_logic;
+	signal RFSH_n_i		: std_logic;
+	signal BUSAK_n_i	: std_logic;
+	signal A_i			: std_logic_vector(15 downto 0);
+--AS--	signal DO			: std_logic_vector(7 downto 0);
+	signal DI_Reg		: std_logic_vector (7 downto 0);	-- Input synchroniser
+	signal Wait_s		: std_logic;
+	signal MCycle		: std_logic_vector(2 downto 0);
+	signal TState		: std_logic_vector(2 downto 0);
+
+begin
+
+	CEN <= '1';
+
+	BUSAK_n <= BUSAK_n_i;
+	MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
+	RD_n_i <= not RD or Req_Inhibit;
+
+--AS--	MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
+--AS--	IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
+--AS--	RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
+--AS--	WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
+--AS--	RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
+--AS--	A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
+--AS--	D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
+--AS>>
+	MREQ_n <= MREQ_n_i;
+	IORQ_n <= IORQ_n_i;
+	RD_n <= RD_n_i;
+	WR_n <= WR_n_i;
+	RFSH_n <= RFSH_n_i;
+	A <= A_i;
+	DOE <= Write when BUSAK_n_i = '1' else '0';
+--<<AS
+	process (RESET_n, CLK_n)
+	begin
+		if RESET_n = '0' then
+			Reset_s <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			Reset_s <= '1';
+		end if;
+	end process;
+
+	u0 : T80
+		generic map(
+			Mode => Mode,
+			IOWait => 1)
+		port map(
+			CEN => CEN,
+			M1_n => M1_n,
+			IORQ => IORQ,
+			NoRead => NoRead,
+			Write => Write,
+			RFSH_n => RFSH_n_i,
+			HALT_n => HALT_n,
+			WAIT_n => Wait_s,
+			INT_n => INT_n,
+			NMI_n => NMI_n,
+			RESET_n => Reset_s,
+			BUSRQ_n => BUSRQ_n,
+			BUSAK_n => BUSAK_n_i,
+			CLK_n => CLK_n,
+			A => A_i,
+--			DInst => D,
+			DInst => DI,
+			DI => DI_Reg,
+			DO => DO,
+			MC => MCycle,
+			TS => TState,
+			IntCycle_n => IntCycle_n);
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '0' then
+			Wait_s <= WAIT_n;
+			if TState = "011" and BUSAK_n_i = '1' then
+--AS--				DI_Reg <= to_x01(D);
+--AS>>
+				DI_Reg <= to_x01(DI);
+--<<AS
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			WR_n_i <= '1';
+		elsif CLK_n'event and CLK_n = '1' then
+			WR_n_i <= '1';
+			if TState = "001" then	-- To short for IO writes !!!!!!!!!!!!!!!!!!!
+				WR_n_i <= not Write;
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			Req_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '1' then
+			if MCycle = "001" and TState = "010" then
+				Req_Inhibit <= '1';
+			else
+				Req_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process (Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			MReq_Inhibit <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+			if MCycle = "001" and TState = "010" then
+				MReq_Inhibit <= '1';
+			else
+				MReq_Inhibit <= '0';
+			end if;
+		end if;
+	end process;
+
+	process(Reset_s,CLK_n)
+	begin
+		if Reset_s = '0' then
+			RD <= '0';
+			IORQ_n_i <= '1';
+			MREQ <= '0';
+		elsif CLK_n'event and CLK_n = '0' then
+
+			if MCycle = "001" then
+				if TState = "001" then
+					RD <= IntCycle_n;
+					MREQ <= IntCycle_n;
+					IORQ_n_i <= IntCycle_n;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '1';
+				end if;
+				if TState = "100" then
+					MREQ <= '0';
+				end if;
+			else
+				if TState = "001" and NoRead = '0' then
+					RD <= not Write;
+					IORQ_n_i <= not IORQ;
+					MREQ <= not IORQ;
+				end if;
+				if TState = "011" then
+					RD <= '0';
+					IORQ_n_i <= '1';
+					MREQ <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;
--- a/Hardware/ZigZag_MiST/rtl/dac.vhd
+++ b/Hardware/ZigZag_MiST/rtl/dac.vhd
@@ -0,0 +1,71 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dac is
+
+  generic (
+    msbi_g : integer := 11
+  );
+  port (
+    clk_i   : in  std_logic;
+    res_n_i : in  std_logic;
+    dac_i   : in  std_logic_vector(msbi_g downto 0);
+    dac_o   : out std_logic
+  );
+
+end dac;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dac is
+
+  signal DACout_q      : std_logic;
+  signal DeltaAdder_s,
+         SigmaAdder_s,
+         SigmaLatch_q,
+         DeltaB_s      : unsigned(msbi_g+2 downto 0);
+
+begin
+
+  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
+                                        SigmaLatch_q(msbi_g+2);
+  DeltaB_s(msbi_g   downto        0) <= (others => '0');
+
+  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
+
+  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
+
+  seq: process (clk_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
+      DACout_q     <= '0';
+
+    elsif clk_i'event and clk_i = '1' then
+      SigmaLatch_q <= SigmaAdder_s;
+      DACout_q     <= SigmaLatch_q(msbi_g+2);
+    end if;
+  end process seq;
+
+  dac_o <= DACout_q;
+
+end rtl;
--- a/Hardware/ZigZag_MiST/rtl/dpram.vhd
+++ b/Hardware/ZigZag_MiST/rtl/dpram.vhd
@@ -0,0 +1,75 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+entity dpram is
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address_a	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		address_b	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		enable_a		: IN STD_LOGIC  := '1';
+		enable_b		: IN STD_LOGIC  := '1';
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		q_b			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "NORMAL",
+		clock_enable_input_b => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone V",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		numwords_b => 2**addr_width_g,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		widthad_b => addr_width_g,
+		width_a => data_width_g,
+		width_b => data_width_g,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		address_a => address_a,
+		address_b => address_b,
+		clock0 => clock_a,
+		clock1 => clock_b,
+		clocken0 => enable_a,
+		clocken1 => enable_b,
+		data_a => data_a,
+		data_b => data_b,
+		wren_a => wren_a,
+		wren_b => wren_b,
+		q_a => q_a,
+		q_b => q_b
+	);
+
+END SYN;
--- a/Hardware/ZigZag_MiST/rtl/hq2x.sv
+++ b/Hardware/ZigZag_MiST/rtl/hq2x.sv
@@ -0,0 +1,454 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+	wire [DWIDTH:0] out[2];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+
+module hq2x_out #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input      [1:0] rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input      [1:0] wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
+	wire  [DWIDTH:0] out[4];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
+endmodule
+
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input	            clock,
+	input	 [DWIDTH:0] data,
+	input	 [AWIDTH:0] rdaddress,
+	input	 [AWIDTH:0] wraddress,
+	input	            wren,
+	output [DWIDTH:0] q
+);
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b(q),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({(DWIDTH+1){1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = NUMWORDS,
+		altsyncram_component.numwords_b = NUMWORDS,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = AWIDTH+1,
+		altsyncram_component.widthad_b = AWIDTH+1,
+		altsyncram_component.width_a = DWIDTH+1,
+		altsyncram_component.width_b = DWIDTH+1,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [17:0] rgb1,
+	input [17:0] rgb2,
+	output result
+);
+
+	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
+	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
+	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
+	wire [6:0] t = $signed(r) + $signed(b);
+	wire [6:0] gx = {g[5], g};
+	wire [7:0] y = $signed(t) + $signed(gx);
+	wire [6:0] u = $signed(r) - $signed(b);
+	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-24..24)
+	wire y_inside = (y < 8'h18 || y >= 8'he8);
+
+	// if u is inside (-4, 4)
+	wire u_inside = (u < 7'h4 || u >= 7'h7c);
+
+	// if v is inside (-6, 6)
+	wire v_inside = (v < 8'h6 || v >= 8'hfA);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [5:0] A,
+	input  [5:0] B,
+	input  [5:0] C,
+	output [5:0] O
+);
+
+	function  [8:0] mul6x3;
+		input  [5:0] op1;
+		input  [2:0] op2;
+	begin
+		mul6x3 = 9'd0;
+		if(op2[0]) mul6x3 = mul6x3 + op1;
+		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
+		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [8:0] Amul = mul6x3(A, Op[7:5]);
+	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
+	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
+	wire [8:0] At =  Amul;
+	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[9:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [17:0] E,
+	input  [17:0] A,
+	input  [17:0] B,
+	input  [17:0] D,
+	input  [17:0] F,
+	input  [17:0] H,
+	output [17:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = 11'bx;
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [17:0] Input1 = E;
+	wire [17:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
+	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
+	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
+endmodule
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input               clk,
+	input               ce_x4,
+	input    [DWIDTH:0] inputpixel,
+	input               mono,
+	input               disable_hq2x,
+	input               reset_frame,
+	input               reset_line,
+	input         [1:0] read_y,
+	input  [AWIDTH+1:0] read_x,
+	output   [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+localparam DWIDTH = HALF_DEPTH ? 8 : 17;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
+reg [17:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] i;
+reg  [7:0] y;
+
+wire curbuf = y[0];
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
+wire [17:0] blend_result;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
+
+reg             Curr2_addr1;
+reg  [AWIDTH:0] Curr2_addr2;
+wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
+wire [DWIDTH:0] Curr2tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [17:0] h2rgb;
+	input  [8:0] v;
+begin
+	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
+end
+endfunction
+
+function  [8:0] rgb2h;
+	input [17:0] v;
+begin
+	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(Curr2_addr2),
+	.rdbuf(Curr2_addr1),
+	.q(Curr2tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg         [1:0] wrout_addr1;
+reg  [AWIDTH+1:0] wrout_addr2;
+reg               wrout_en;
+reg    [DWIDTH:0] wrdata;
+
+hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
+(
+	.clk(clk),
+
+	.rdaddr(read_x),
+	.rdbuf(read_y),
+	.q(outpixel),
+
+	.wraddr(wrout_addr2),
+	.wrbuf(wrout_addr1),
+	.data(wrdata),
+	.wren(wrout_en)
+);
+
+always @(posedge clk) begin
+	reg [AWIDTH:0] offs;
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+
+		if(~&offs) begin
+			if (i == 0) begin
+				Curr2_addr1 <= prevbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 1) begin
+				Prev2 <= Curr2;
+				Curr2_addr1 <= curbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 2) begin
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+			if (i == 3) begin
+				offs <= offs + 1'd1;
+			end
+
+			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
+			else           wrdata <= blend_result;
+
+			wrout_addr1 <= {curbuf, i[1]};
+			wrout_addr2 <= {offs, i[1]^i[0]};
+			wrout_en    <= 1;
+		end
+
+		if(i==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		i <= i + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			i <= 0;
+			y <= y + 1'd1;
+			prevbuf <= curbuf;
+			if(old_reset_frame & ~reset_frame) begin
+				y <= 0;
+				prevbuf <= 0;
+			end
+		end
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule  // Hq2x
--- a/Hardware/ZigZag_MiST/rtl/keyboard.v
+++ b/Hardware/ZigZag_MiST/rtl/keyboard.v
@@ -0,0 +1,82 @@
+
+
+module keyboard
+(
+	input  clk,
+	input  reset,
+	input  ps2_kbd_clk,
+	input  ps2_kbd_data,
+
+	output reg[7:0] joystick
+);
+
+reg [11:0] shift_reg = 12'hFFF;
+wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
+wire [7:0] kcode = kdata[9:2];
+reg        release_btn = 0;
+
+reg  [7:0] code;
+reg        input_strobe = 0;
+
+always @(negedge clk) begin
+	reg old_reset = 0;
+
+	old_reset <= reset;
+
+	if(~old_reset & reset)begin
+		joystick <= 0;
+	end
+
+	if(input_strobe) begin
+		case(code)
+			'h16: joystick[1] <= ~release_btn; // 1
+			'h1E: joystick[2] <= ~release_btn; // 2
+
+			'h75: joystick[4] <= ~release_btn; // arrow up
+			'h72: joystick[5] <= ~release_btn; // arrow down
+			'h6B: joystick[6] <= ~release_btn; // arrow left
+			'h74: joystick[7] <= ~release_btn; // arrow right
+
+			'h29: joystick[0] <= ~release_btn; // Space
+			'h11: joystick[1] <= ~release_btn; // Left Alt
+			'h0d: joystick[2] <= ~release_btn; // Tab
+			'h76: joystick[3] <= ~release_btn; // Escape
+		endcase
+	end
+end
+
+always @(posedge clk) begin
+	reg [3:0] prev_clk  = 0;
+	reg       old_reset = 0;
+	reg       action = 0;
+
+	old_reset <= reset;
+	input_strobe <= 0;
+
+	if(~old_reset & reset)begin
+		prev_clk  <= 0;
+		shift_reg <= 12'hFFF;
+	end else begin
+		prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
+		if(prev_clk == 1) begin
+			if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
+				shift_reg <= 12'hFFF;
+				if (kcode == 8'he0) ;
+				// Extended key code follows
+				else if (kcode == 8'hf0)
+					// Release code follows
+					action <= 1;
+				else begin
+					// Cancel extended/release flags for next time
+					action <= 0;
+					release_btn <= action;
+					code <= kcode;
+					input_strobe <= 1;
+				end
+			end else begin
+				shift_reg <= kdata;
+			end
+		end
+	end
+end
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/mc_adec.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_adec.vhd
@@ -0,0 +1,253 @@
+---------------------------------------------------------------------
+-- FPGA GALAXIAN ADDRESS DECDER
+--
+-- Version : 2.01
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004- 4-30  galaxian modify by K.DEGAWA
+-- 2004- 5- 6  first release.
+-- 2004- 8-23  Improvement with T80-IP.
+---------------------------------------------------------------------
+--
+--GALAXIAN Address Map
+--
+-- Address      Item(R..read-mode W..wight-mode)        Parts
+--0000 - 1FFF   CPU-ROM..R                            ( 7H or 7K )
+--2000 - 3FFF   CPU-ROM..R                            ( 7L )
+--4000 - 47FF   CPU-RAM..RW                           ( 7N  & 7P )
+--5000 - 57FF   VID-RAM..RW
+--5800 - 5FFF   OBJ-RAM..RW
+--6000 -        SW0..R   LAMP......W
+--6800 -        SW1..R   SOUND.....W
+--7000 -        DIP..R
+--7001                   NMI_ON....W
+--7004                   STARS_ON..W
+--7006                   H_FLIP....W
+--7007                   V-FLIP....W
+--7800          WDR..R   PITCH.....W
+--
+--W MODE
+--6000                  1P START
+--6001                  2P START
+--6002                  COIN LOCKOUT
+--6003                  COIN COUNTER
+--6004 - 6007           SOUND CONTROL(OSC)
+--
+--6800                  SOUND CONTROL(FS1)
+--6801                  SOUND CONTROL(FS2)
+--6802                  SOUND CONTROL(FS3)
+--6803                  SOUND CONTROL(HIT)
+--6805                  SOUND CONTROL(SHOT)
+--6806                  SOUND CONTROL(VOL1)
+--6807                  SOUND CONTROL(VOL2)
+--
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_ADEC is
+	port (
+		I_CLK_12M     : in  std_logic;
+		I_CLK_6M      : in  std_logic;
+		I_CPU_CLK     : in  std_logic;
+		I_RSTn        : in  std_logic;
+
+		I_CPU_A       : in  std_logic_vector(15 downto 0);
+		I_CPU_D       : in  std_logic;
+		I_MREQn       : in  std_logic;
+		I_RFSHn       : in  std_logic;
+		I_RDn         : in  std_logic;
+		I_WRn         : in  std_logic;
+		I_H_BL        : in  std_logic;
+		I_V_BLn       : in  std_logic;
+
+		O_WAITn       : out std_logic;
+		O_NMIn        : out std_logic;
+		O_CPU_ROM_CS  : out std_logic;
+		O_CPU_RAM_RD  : out std_logic;
+		O_CPU_RAM_WR  : out std_logic;
+		O_CPU_RAM_CS  : out std_logic;
+		O_OBJ_RAM_RD  : out std_logic;
+		O_OBJ_RAM_WR  : out std_logic;
+		O_OBJ_RAM_RQ  : out std_logic;
+		O_VID_RAM_RD  : out std_logic;
+		O_VID_RAM_WR  : out std_logic;
+		O_SW0_OE      : out std_logic;
+		O_SW1_OE      : out std_logic;
+		O_DIP_OE      : out std_logic;
+		O_WDR_OE      : out std_logic;
+		O_DRIVER_WE   : out std_logic;
+		O_SOUND_WE    : out std_logic;
+		O_PITCH       : out std_logic;
+		O_H_FLIP      : out std_logic;
+		O_V_FLIP      : out std_logic;
+		O_BD_G        : out std_logic;
+		O_ROM_SWP     : out std_logic;
+		O_STARS_ON    : out std_logic
+	);
+end;
+
+architecture RTL of MC_ADEC is
+	signal W_8E1_Q   : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_8E2_Q   : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_8P_Q    : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_8N_Q    : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_8M_Q    : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_9N_Q    : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_NMI_ONn : std_logic := '0';
+	--------  CPU WAITn  ----------------------------------------------
+--	signal W_6S1_Q   : std_logic := '0';
+	signal W_6S1_Qn  : std_logic := '0';
+--	signal W_6S2_Qn  : std_logic := '0';
+
+	signal W_V_BL    : std_logic := '0';
+
+begin
+		W_NMI_ONn <= W_9N_Q(1); --  galaxian
+
+--		O_WAITn <= '1' ; -- No Wait
+		O_WAITn <= W_6S1_Qn;
+
+	process(I_CPU_CLK, I_V_BLn)
+	begin
+		if (I_V_BLn = '0') then
+--			W_6S1_Q  <= '0';
+			W_6S1_Qn <= '1';
+		elsif rising_edge(I_CPU_CLK) then
+--			W_6S1_Q  <= not (I_H_BL or W_8P_Q(2));
+			W_6S1_Qn <=      I_H_BL or W_8P_Q(2);
+		end if;
+	end process;
+
+--	process(I_CPU_CLK)
+--	begin
+--		if falling_edge(I_CPU_CLK) then
+--			W_6S2_Qn <= not W_6S1_Q;
+--		end if;
+--	end process;
+
+--------  CPU NMIn  -----------------------------------------------
+	W_V_BL <= not I_V_BLn;
+	process(W_V_BL, W_NMI_ONn)
+	begin
+		if (W_NMI_ONn = '0') then
+			O_NMIn  <= '1';
+		elsif rising_edge(W_V_BL) then
+			O_NMIn  <= '0';
+		end if;
+	end process;
+
+	-------------------------------------------------------------------
+	u_8e1 : entity work.LOGIC_74XX139
+	port map (
+		I_G      => I_MREQn,
+		I_Sel(1) => I_CPU_A(15),
+		I_Sel(0) => I_CPU_A(14),
+		O_Q      => W_8E1_Q
+	);
+
+	----------   CPU_ROM CS    0000 - 3FFF  ---------------------------
+	u_8e2 : entity work.LOGIC_74XX139
+	port map (
+		I_G      => I_RDn,
+		I_Sel(1) => W_8E1_Q(0),
+		I_Sel(0) => I_CPU_A(13),
+		O_Q      => W_8E2_Q
+	);
+
+	O_CPU_ROM_CS  <= not (W_8E2_Q(0) and W_8E2_Q(1) ) ;  --   0000 - 3FFF
+	-------------------------------------------------------------------
+	--                  ADDRESS
+	--    W_8E1_Q[0] = 0000 - 3FFF    ---- CPU_ROM_USE
+	--    W_8E1_Q[1] = 4000 - 7FFF    ---- GALAXIAN USE   *1
+	--    W_8E1_Q[2] = 8000 - BFFF    ---- MOONCREST USE
+	--    W_8E1_Q[3] = C000 - FFFF
+
+	u_8p : entity work.LOGIC_74XX138
+	port map (
+		I_G1  => I_RFSHn,
+		I_G2a => W_8E1_Q(1),   -- <= *1
+		I_G2b => W_8E1_Q(1),   -- <= *1
+		I_Sel => I_CPU_A(13 downto 11),
+		O_Q   => W_8P_Q
+	);
+
+	u_8n : entity work.LOGIC_74XX138
+	port map (
+		I_G1  => '1',
+		I_G2a => I_RDn,
+		I_G2b => W_8E1_Q(1),   -- <= *1
+		I_Sel => I_CPU_A(13 downto 11),
+		O_Q   => W_8N_Q
+	);
+
+	u_8m : entity work.LOGIC_74XX138
+	port map (
+	--	I_G1  => W_6S2_Qn,
+		I_G1  => '1', -- No Wait
+		I_G2a => I_WRn,
+		I_G2b => W_8E1_Q(1),   -- <= *1
+		I_Sel => I_CPU_A(13 downto 11),
+		O_Q   => W_8M_Q
+	);
+
+	O_BD_G        <= not (W_8E1_Q(0) and W_8P_Q(0));
+	O_OBJ_RAM_RQ  <= not W_8P_Q(3);
+
+	O_CPU_RAM_CS  <= not (W_8N_Q(0) and W_8M_Q(0));
+
+	O_WDR_OE      <= not W_8N_Q(7);
+	O_DIP_OE      <= not W_8N_Q(6);
+	O_SW1_OE      <= not W_8N_Q(5);
+	O_SW0_OE      <= not W_8N_Q(4);
+	O_OBJ_RAM_RD  <= not W_8N_Q(3);
+	O_VID_RAM_RD  <= not W_8N_Q(2);
+--	UNUSED        <= not W_8N_Q(1);
+	O_CPU_RAM_RD  <= not W_8N_Q(0);
+
+	O_PITCH       <= not W_8M_Q(7);
+--	STARS_ON_ENA  <= not W_8M_Q(6);
+	O_SOUND_WE    <= not W_8M_Q(5);
+	O_DRIVER_WE   <= not W_8M_Q(4);
+	O_OBJ_RAM_WR  <= not W_8M_Q(3);
+	O_VID_RAM_WR  <= not W_8M_Q(2);
+--	UNUSED        <= not W_8M_Q(1);
+	O_CPU_RAM_WR  <= not W_8M_Q(0);
+
+	-----  Parts 9N ---------
+
+	process(I_CLK_12M, I_RSTn)
+	begin
+		if (I_RSTn = '0') then
+			W_9N_Q <= (others => '0');
+		elsif rising_edge(I_CLK_12M) then
+			if (W_8M_Q(6) = '0') then
+				case I_CPU_A(2 downto 0) is
+					when "000"  => W_9N_Q(0) <= I_CPU_D;
+					when "001"  => W_9N_Q(1) <= I_CPU_D;
+					when "010"  => W_9N_Q(2) <= I_CPU_D;
+					when "011"  => W_9N_Q(3) <= I_CPU_D;
+					when "100"  => W_9N_Q(4) <= I_CPU_D;
+					when "101"  => W_9N_Q(5) <= I_CPU_D;
+					when "110"  => W_9N_Q(6) <= I_CPU_D;
+					when "111"  => W_9N_Q(7) <= I_CPU_D;
+					when others => null;
+				end case;
+			end if;
+		end if;
+	end process;
+
+	O_STARS_ON <= W_9N_Q(4);
+	O_H_FLIP   <= W_9N_Q(6);
+	O_V_FLIP   <= W_9N_Q(7);
+	O_ROM_SWP  <= W_9N_Q(2);
+
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_bram.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_bram.vhd
@@ -0,0 +1,178 @@
+------------------------------------------------------------------------------
+-- FPGA MOONCRESTA & GALAXIAN
+--      FPGA BLOCK RAM I/F (XILINX SPARTAN)
+--
+-- Version : 2.50
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use. 
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- mc_col_rom(6L) added by k.Degawa
+--
+-- 2004- 5- 6  first release.
+-- 2004- 8-23  Improvement with T80-IP.    K.Degawa
+-- 2004- 9-18  added Xilinx Device         K.Degawa
+------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+--  mc_top.v use
+entity MC_CPU_RAM is
+	port (
+		I_CLK  : in  std_logic;
+		I_ADDR : in  std_logic_vector(9 downto 0);
+		I_D    : in  std_logic_vector(7 downto 0);
+		I_WE   : in  std_logic;
+		I_OE   : in  std_logic;
+		O_D    : out std_logic_vector(7 downto 0)
+	);
+end;
+architecture RTL of MC_CPU_RAM is
+
+	signal W_D : std_logic_vector(7 downto 0) := (others => '0');
+begin
+	O_D <= W_D when I_OE ='1' else (others=>'0');
+
+	ram_inst : work.spram generic map(10,8)
+	port map
+	(
+		address  => I_ADDR,
+		clock    => I_CLK,
+		data     => I_D,
+		wren		=> I_WE,
+		q			=> W_D
+	);
+end RTL;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+--  mc_video.v use
+entity MC_OBJ_RAM is
+	port(
+		I_CLKA  : in  std_logic := '0';
+		I_WEA   : in  std_logic := '0';
+		I_CEA   : in  std_logic := '0';
+		I_ADDRA : in  std_logic_vector(7 downto 0);
+		I_DA    : in  std_logic_vector(7 downto 0);
+		O_DA    : out std_logic_vector(7 downto 0);
+
+		I_CLKB  : in  std_logic := '0';
+		I_WEB   : in  std_logic := '0';
+		I_CEB   : in  std_logic := '0';
+		I_ADDRB : in  std_logic_vector(7 downto 0);
+		I_DB    : in  std_logic_vector(7 downto 0);
+		O_DB    : out std_logic_vector(7 downto 0)
+	);
+	end;
+
+architecture RTL of MC_OBJ_RAM is
+begin
+
+	ram_inst : work.dpram generic map(8,8)
+	port map
+	(
+		clock_a		=> I_CLKA,
+		address_a	=> I_ADDRA,
+		data_a		=> I_DA,
+		q_a			=> O_DA,
+		enable_a    => I_CEA,
+		wren_a		=> I_WEA,
+
+		clock_b		=> I_CLKB,
+		address_b	=> I_ADDRB,
+		data_b		=> I_DB,
+		q_b			=> O_DB,
+		enable_b    => I_CEB,
+		wren_b		=> I_WEB
+	);
+end RTL;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+--  mc_video.v use
+entity MC_VID_RAM is
+	port (
+		I_CLKA  : in  std_logic := '0';
+		I_WEA   : in  std_logic := '0';
+		I_CEA   : in  std_logic := '0';
+		I_ADDRA : in  std_logic_vector(9 downto 0);
+		I_DA    : in  std_logic_vector(7 downto 0);
+		O_DA    : out std_logic_vector(7 downto 0);
+
+		I_CLKB  : in  std_logic := '0';
+		I_WEB   : in  std_logic := '0';
+		I_CEB   : in  std_logic := '0';
+		I_ADDRB : in  std_logic_vector(9 downto 0);
+		I_DB    : in  std_logic_vector(7 downto 0);
+		O_DB    : out std_logic_vector(7 downto 0)
+	);
+end;
+
+architecture RTL of MC_VID_RAM is
+begin
+	ram_inst : work.dpram generic map(10,8)
+	port map
+	(
+		clock_a		=> I_CLKA,
+		address_a	=> I_ADDRA,
+		data_a		=> I_DA,
+		q_a			=> O_DA,
+		enable_a    => I_CEA,
+		wren_a		=> I_WEA,
+
+		clock_b		=> I_CLKB,
+		address_b	=> I_ADDRB,
+		data_b		=> I_DB,
+		q_b			=> O_DB,
+		enable_b    => I_CEB,
+		wren_b		=> I_WEB
+	);
+end RTL;
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_LRAM is
+	port (
+		I_CLK   : in  std_logic;
+		I_ADDR  : in  std_logic_vector(7 downto 0);
+		I_D     : in  std_logic_vector(4 downto 0);
+		I_WE    : in  std_logic;
+		O_D     : out std_logic_vector(4 downto 0)
+	);
+end;
+
+architecture RTL of MC_LRAM is
+begin
+
+	ram_inst : work.dpram generic map(8,5)
+	port map
+	(
+		clock_a		=> I_CLK,
+		address_a	=> I_ADDR,
+		data_a		=> I_D,
+		wren_a		=> not I_WE,
+
+		clock_b		=> not I_CLK,
+		address_b	=> I_ADDR,
+		data_b		=> (others => '0'),
+		q_b			=> O_D,
+		enable_b    => '1',
+		wren_b		=> '0'
+	);
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_clut.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_clut.vhd
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all,ieee.numeric_std.all;
+
+entity mc_clut is
+port (
+	clk  : in  std_logic;
+	addr : in  std_logic_vector(4 downto 0);
+	data : out std_logic_vector(7 downto 0)
+);
+end entity;
+
+architecture prom of mc_clut is
+	type rom is array(0 to  31) of std_logic_vector(7 downto 0);
+	signal rom_data: rom := (
+		X"00",X"C7",X"F0",X"3F",X"00",X"DB",X"C6",X"38",X"00",X"F0",X"15",X"1F",X"00",X"F6",X"06",X"07",
+		X"00",X"91",X"07",X"F6",X"00",X"F0",X"FE",X"07",X"00",X"38",X"07",X"FE",X"00",X"07",X"3F",X"FE");
+begin
+process(clk)
+begin
+	if rising_edge(clk) then
+		data <= rom_data(to_integer(unsigned(addr)));
+	end if;
+end process;
+end architecture;
--- a/Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_col_pal.vhd
@@ -0,0 +1,49 @@
+-------------------------------------------------------------------------------
+-- FPGA MOONCRESTA COLOR-PALETTE
+--
+-- Version : 2.00
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004- 9-18 added Xilinx Device.  K.Degawa
+-------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+
+entity MC_COL_PAL is
+port (
+	I_CLK_6M     : in  std_logic;
+	I_VID        : in  std_logic_vector(1 downto 0);
+	I_COL        : in  std_logic_vector(2 downto 0);
+
+	O_R          : out std_logic_vector(2 downto 0);
+	O_G          : out std_logic_vector(2 downto 0);
+	O_B          : out std_logic_vector(2 downto 0)
+);
+end;
+
+architecture RTL of MC_COL_PAL is
+	---    Parts 6M    --------------------------------------------------------
+	signal W_COL_ROM_DO : std_logic_vector(7 downto 0);
+
+begin
+	clut : entity work.mc_clut
+	port map (
+		CLK  => I_CLK_6M,
+		ADDR => I_COL(2 downto 0) & I_VID(1 downto 0),
+		DATA => W_COL_ROM_DO
+	);
+
+	---    VID OUT     --------------------------------------------------------
+	O_R <= W_COL_ROM_DO(2 downto 0);
+	O_G <= W_COL_ROM_DO(5 downto 3);
+	O_B <= W_COL_ROM_DO(7 downto 6) & "0";
+
+end;
--- a/Hardware/ZigZag_MiST/rtl/mc_hv_count.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_hv_count.vhd
@@ -0,0 +1,145 @@
+-----------------------------------------------------------------------
+-- FPGA MOONCRESTA   H & V COUNTER 
+--
+-- Version : 2.00
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use. 
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004- 9-22  
+-----------------------------------------------------------------------
+--  MoonCrest hv_count
+--  H_CNT   0 - 255 , 384 - 511  Total 384 count
+--  V_CNT   0 - 255 , 504 - 511  Total 264 count
+-------------------------------------------------------------------------------------------
+-- H_CNT[0], H_CNT[1], H_CNT[2], H_CNT[3], H_CNT[4], H_CNT[5], H_CNT[6], H_CNT[7], H_CNT[8],  
+--    1 H       2 H       4 H       8 H      16 H      32 H      64 H     128 H    256 H
+-------------------------------------------------------------------------------------------
+-- V_CNT[0], V_CNT[1], V_CNT[2], V_CNT[3], V_CNT[4], V_CNT[5], V_CNT[6], V_CNT[7]  
+--    1 V       2 V       4 V       8 V      16 V      32 V      64 V     128 V 
+-------------------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_HV_COUNT is
+	port(
+		I_CLK    : in  std_logic;
+		I_RSTn   : in  std_logic;
+		O_H_CNT  : out std_logic_vector(8 downto 0);
+		O_H_SYNC : out std_logic;
+		O_H_BL   : out std_logic;
+		O_V_BL2n : out std_logic;
+		O_V_CNT  : out std_logic_vector(7 downto 0);
+		O_V_SYNC : out std_logic;
+		O_V_BLn  : out std_logic;
+		O_C_BLn  : out std_logic
+	);
+end;
+
+architecture RTL of MC_HV_COUNT is
+	signal H_CNT  : std_logic_vector(8 downto 0) := (others => '0');
+	signal V_CNT  : std_logic_vector(8 downto 0) := (others => '0');
+	signal H_SYNC : std_logic := '0';
+	signal H_CLK  : std_logic := '0';
+	signal H_BL   : std_logic := '0';
+	signal V_BLn  : std_logic := '0';
+	signal V_BL2n : std_logic := '0';
+
+begin
+---------   H_COUNT   ----------------------------------------   
+
+	process(I_CLK)
+	begin
+		if rising_edge(I_CLK) then
+			if (H_CNT = 255) then
+				H_CNT <= std_logic_vector(to_unsigned(384, H_CNT'length));
+			else
+				H_CNT <= H_CNT + 1 ;
+			end if;
+		end if;
+	end process;
+
+	O_H_CNT  <= H_CNT;
+
+---------   H_SYNC     ----------------------------------------
+	H_CLK <= H_CNT(4);
+	process(H_CLK, H_CNT(8))
+	begin
+		if (H_CNT(8) = '0') then
+			H_SYNC <= '0';
+		elsif rising_edge(H_CLK) then
+			H_SYNC <= (not H_CNT(6) ) and H_CNT(5);
+		end if;
+	end process;
+
+	O_H_SYNC <= H_SYNC;
+
+---------   H_BL     ------------------------------------------
+
+	process(I_CLK)
+	begin
+		if rising_edge(I_CLK) then
+			if H_CNT = 387 then
+				H_BL <= '1';
+			elsif H_CNT = 503 then
+				H_BL <= '0';
+			end if;
+		end if;
+	end process;
+
+	O_H_BL <= H_BL;
+
+---------   V_COUNT   ----------------------------------------   
+	process(H_SYNC, I_RSTn)
+	begin
+		if (I_RSTn = '0') then
+			V_CNT <= (others => '0');
+		elsif rising_edge(H_SYNC) then
+			if (V_CNT = 255) then
+				V_CNT <= std_logic_vector(to_unsigned(504, V_CNT'length));
+			else
+				V_CNT <= V_CNT + 1 ;
+			end if;
+		end if;
+	end process;
+
+	O_V_CNT  <= V_CNT(7 downto 0);
+	O_V_SYNC <= V_CNT(8);
+
+---------   V_BLn    ------------------------------------------
+
+	process(H_SYNC)
+	begin
+		if rising_edge(H_SYNC) then
+			if V_CNT(7 downto 0) = 239 then
+				V_BLn <= '0';
+			elsif V_CNT(7 downto 0) = 15 then
+				V_BLn <= '1';
+			end if;
+		end if;
+	end process;
+
+	process(H_SYNC)
+	begin
+		if rising_edge(H_SYNC) then
+			if V_CNT(7 downto 0) = 240 then
+				V_BL2n <= '0';
+			elsif V_CNT(7 downto 0) = 15 then
+				V_BL2n <= '1';
+			end if;
+		end if;
+	end process;
+
+	O_V_BLn  <= V_BLn;
+	O_V_BL2n <= V_BL2n;
+-------   C_BLn     ------------------------------------------
+	O_C_BLn  <= V_BLn and (not H_CNT(8));
+
+end;
--- a/Hardware/ZigZag_MiST/rtl/mc_inport.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_inport.vhd
@@ -0,0 +1,74 @@
+-----------------------------------------------------------------------
+-- FPGA MOONCRESTA INPORT
+--
+-- Version : 1.01
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004-4-30  galaxian modify by K.DEGAWA
+-----------------------------------------------------------------------
+
+--    DIP SW        0     1     2     3     4     5
+-----------------------------------------------------------------
+--  COIN CHUTE
+-- 1 COIN/1 PLAY   1'b0  1'b0
+-- 2 COIN/1 PLAY   1'b1  1'b0
+-- 1 COIN/2 PLAY   1'b0  1'b1
+-- FREE PLAY       1'b1  1'b1
+--   BOUNS
+--                             1'b0  1'b0
+--                             1'b1  1'b0
+--                             1'b0  1'b1
+--                             1'b1  1'b1
+--   LIVES
+--     2                                   1'b0
+--     3                                   1'b1
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_INPORT is
+port (
+	I_COIN1    : in  std_logic;   --  active high
+	I_COIN2    : in  std_logic;   --  active high
+	I_LEFT     : in  std_logic;   --  active high
+	I_RIGHT    : in  std_logic;   --  active high
+	I_UP       : in  std_logic;   --  active high
+	I_DOWN     : in  std_logic;
+	I_FIRE     : in  std_logic;
+	I_1P_START : in  std_logic;   --  active high
+	I_2P_START : in  std_logic;   --  active high
+
+	I_SW0_OE   : in  std_logic;
+	I_SW1_OE   : in  std_logic;
+	I_DIP_OE   : in  std_logic;
+	O_D        : out std_logic_vector(7 downto 0)
+);
+
+end;
+
+architecture RTL of MC_INPORT is
+
+	constant W_TABLE   : std_logic := '0';  -- UP = 0;
+	constant W_TEST    : std_logic := '0';
+	constant W_SERVICE : std_logic := '0';
+
+	signal W_SW0_DO : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_SW1_DO : std_logic_vector(7 downto 0) := (others => '0');
+	signal W_DIP_DO : std_logic_vector(7 downto 0) := (others => '0');
+
+begin
+
+	W_SW0_DO <= x"00" when I_SW0_OE = '0' else '0' & I_DOWN & I_UP &  I_FIRE &  I_RIGHT & I_LEFT & I_COIN2 & I_COIN1;
+	W_SW1_DO <= x"00" when I_SW1_OE = '0' else "000000" & I_2P_START & I_1P_START;
+	W_DIP_DO <= x"00" when I_DIP_OE = '0' else "00000011";
+	O_D      <= W_SW0_DO or W_SW1_DO or W_DIP_DO ;
+
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_ld_pls.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_ld_pls.vhd
@@ -0,0 +1,115 @@
+-------------------------------------------------------------------------------
+-- FPGA MOONCRESTA VIDEO-LD_PLS_GEN
+--
+-- Version : 2.00
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-- 2004- 9-22 The problem where missile sometimes didn't come out was fixed.
+-------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_LD_PLS is
+	port (
+		I_CLK_6M     : in  std_logic;
+		I_H_CNT      : in  std_logic_vector(8 downto 0);
+		I_3D_DI      : in  std_logic;
+
+		O_LDn        : out std_logic;
+		O_CNTRLDn    : out std_logic;
+		O_CNTRCLRn   : out std_logic;
+		O_COLLn      : out std_logic;
+		O_VPLn       : out std_logic;
+		O_OBJDATALn  : out std_logic;
+		O_MLDn       : out std_logic;
+		O_SLDn       : out std_logic
+	);
+end;
+
+architecture RTL of MC_LD_PLS is
+	signal W_4C1_Q  : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_4C2_Q  : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_4C1_Q3 : std_logic := '0';
+	signal W_4C2_B  : std_logic := '0';
+	signal W_4D1_G  : std_logic := '0';
+	signal W_4D1_Q  : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_4D2_Q  : std_logic_vector(3 downto 0) := (others => '0');
+	signal W_5C_Q   : std_logic := '0';
+	signal W_HCNT   : std_logic := '0';
+begin
+	O_LDn       <= W_4D1_G;
+	O_CNTRLDn   <= W_4D1_Q(2);
+	O_CNTRCLRn  <= W_4D1_Q(0);
+	O_COLLn     <= W_4D2_Q(2);
+	O_VPLn      <= W_4D2_Q(0);
+	O_OBJDATALn <= W_4C1_Q(2);
+	O_MLDn      <= W_4C2_Q(0);
+	O_SLDn      <= W_4C2_Q(1);
+	W_4D1_G     <= not (I_H_CNT(0) and I_H_CNT(1) and I_H_CNT(2));
+	W_HCNT      <= not (I_H_CNT(6) and I_H_CNT(5) and I_H_CNT(4) and I_H_CNT(3));
+	--    Parts 4D
+	u_4d1 : entity work.LOGIC_74XX139
+	port map(
+		I_G      => W_4D1_G,
+		I_Sel(1) => I_H_CNT(8),
+		I_Sel(0) => I_H_CNT(3),
+		O_Q      =>W_4D1_Q
+	);
+
+	u_4d2 : entity work.LOGIC_74XX139
+	port map(
+		I_G      => W_5C_Q,
+		I_Sel(1) => I_H_CNT(2),
+		I_Sel(0) => I_H_CNT(1),
+		O_Q      => W_4D2_Q
+	);
+
+	--    Parts 4C
+	u_4c1 : entity work.LOGIC_74XX139
+	port map(
+		I_G      => W_4D2_Q(1),
+		I_Sel(1) => I_H_CNT(8),
+		I_Sel(0) => I_H_CNT(3),
+		O_Q      => W_4C1_Q
+	);
+
+	u_4c2 : entity work.LOGIC_74XX139
+	port map(
+		I_G      => W_4D1_Q(3),
+		I_Sel(1) => W_4C2_B,
+		I_Sel(0) => W_HCNT,
+		O_Q      => W_4C2_Q
+	);
+
+	process(I_CLK_6M)
+	begin
+		if falling_edge(I_CLK_6M) then
+			W_5C_Q <= I_H_CNT(0);
+		end if;
+	end process;
+
+	-- 2004-9-22 added
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			W_4C1_Q3 <= W_4C1_Q(3);
+		end if;
+	end process;
+
+	process(W_4C1_Q3)
+	begin
+		if rising_edge(W_4C1_Q3) then
+			W_4C2_B <= I_3D_DI;
+		end if;
+	end process;
+
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_logic.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_logic.vhd
@@ -0,0 +1,92 @@
+-------------------------------------------------------------------------------
+-- FPGA MOONCRESTA    LOGIC IP MODULE
+--
+-- Version : 1.00
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+-- 74xx138
+-- 3-to-8 line decoder
+-------------------------------------------------------------------------------
+entity LOGIC_74XX138 is
+	port (
+		I_G1  : in  std_logic;
+		I_G2a : in  std_logic;
+		I_G2b : in  std_logic;
+		I_Sel : in  std_logic_vector(2 downto 0);
+		O_Q   : out std_logic_vector(7 downto 0)
+	);
+end logic_74xx138;
+
+architecture RTL of LOGIC_74XX138 is
+	signal I_G : std_logic_vector(2 downto 0) := (others => '0');
+
+begin
+	I_G <= I_G1 & I_G2a & I_G2b;
+
+	xx138 : process(I_G, I_Sel)
+	begin
+		if(I_G = "100" ) then
+			case I_Sel is
+				when "000" => O_Q <= "11111110";
+				when "001" => O_Q <= "11111101";
+				when "010" => O_Q <= "11111011";
+				when "011" => O_Q <= "11110111";
+				when "100" => O_Q <= "11101111";
+				when "101" => O_Q <= "11011111";
+				when "110" => O_Q <= "10111111";
+				when "111" => O_Q <= "01111111";
+				when others => null;
+			end case;
+		 else
+				O_Q <= (others => '1');
+		 end if;
+	end process;
+end RTL;
+
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+-------------------------------------------------------------------------------
+-- 74xx139
+-- 2-to-4 line decoder
+-------------------------------------------------------------------------------
+entity LOGIC_74XX139 is
+	port (
+		I_G   : in  std_logic;
+		I_Sel : in  std_logic_vector(1 downto 0);
+		O_Q   : out std_logic_vector(3 downto 0)
+	);
+end;
+
+architecture RTL of LOGIC_74XX139 is
+begin
+	xx139 : process (I_G, I_Sel)
+	begin
+		if I_G = '0' then
+			case I_Sel is
+				when "00" => O_Q <= "1110";
+				when "01" => O_Q <= "1101";
+				when "10" => O_Q <= "1011";
+				when "11" => O_Q <= "0111";
+				when others => null;
+			end case;
+		else
+			O_Q <= "1111";
+		end if;
+	end process;
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_sprite.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_sprite.vhd
@@ -0,0 +1,321 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity mc_sprite is
+	port(
+		I_CLK_12M     : in  std_logic;
+		I_CLK_6M      : in  std_logic;
+		I_H_CNT       : in  std_logic_vector(8 downto 0);
+		I_V_CNT       : in  std_logic_vector(7 downto 0);
+		I_H_FLIP      : in  std_logic;
+		I_V_FLIP      : in  std_logic;
+		I_V_BLn       : in  std_logic;
+		I_C_BLn       : in  std_logic;
+
+		I_A           : in  std_logic_vector(9 downto 0);
+		I_BD          : in  std_logic_vector(7 downto 0);
+		I_OBJ_RAM_RQ  : in  std_logic;
+		I_OBJ_RAM_WR  : in  std_logic;
+
+		O_RAW         : out std_logic_vector(1 downto 0);
+		O_CD          : out std_logic_vector(2 downto 0)
+	);
+end;
+
+architecture RTL of mc_sprite is
+
+	signal WB_LDn       : std_logic := '0';
+	signal WB_CNTRLDn   : std_logic := '0';
+	signal WB_CNTRCLRn  : std_logic := '0';
+	signal WB_COLLn     : std_logic := '0';
+	signal WB_VPLn      : std_logic := '0';
+	signal WB_OBJDATALn : std_logic := '0';
+	signal W_3D         : std_logic := '0';
+	signal W_LDn        : std_logic := '0';
+	signal W_CNTRLDn    : std_logic := '0';
+	signal W_CNTRCLRn   : std_logic := '0';
+	signal W_COLLn      : std_logic := '0';
+	signal W_VPLn       : std_logic := '0';
+	signal W_OBJDATALn  : std_logic := '0';
+	signal W_VID        : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_COL        : std_logic_vector( 2 downto 0) := (others => '0');
+
+	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
+	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_RV         : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_RC         : std_logic_vector( 2 downto 0) := (others => '0');
+
+	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
+	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_CD           : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
+	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
+	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_256HnX       : std_logic := '0';
+	signal W_2N           : std_logic := '0';
+	signal W_45T_CLR      : std_logic := '0';
+	signal W_H_FLIP1      : std_logic := '0';
+	signal W_H_FLIP2      : std_logic := '0';
+	signal W_H_FLIP1X     : std_logic := '0';
+	signal W_H_FLIP2X     : std_logic := '0';
+	signal W_LRAM_AND     : std_logic := '0';
+	signal W_RAW0         : std_logic := '0';
+	signal W_RAW1         : std_logic := '0';
+	signal W_SRLD         : std_logic := '0';
+
+begin
+
+	ld_pls : entity work.MC_LD_PLS
+	port map(
+		I_CLK_6M    => I_CLK_6M,
+		I_H_CNT     => I_H_CNT,
+		I_3D_DI     => W_3D,
+
+		O_LDn       => WB_LDn,
+		O_CNTRLDn   => WB_CNTRLDn,
+		O_CNTRCLRn  => WB_CNTRCLRn,
+		O_COLLn     => WB_COLLn,
+		O_VPLn      => WB_VPLn,
+		O_OBJDATALn => WB_OBJDATALn
+	);
+
+	obj_ram : entity work.MC_OBJ_RAM 
+	port map(
+		I_CLKA  => I_CLK_12M,
+		I_ADDRA => I_A(7 downto 0),
+		I_WEA   => I_OBJ_RAM_WR,
+		I_CEA   => I_OBJ_RAM_RQ,
+		I_DA    => I_BD,
+
+		I_CLKB  => I_CLK_12M,
+		I_ADDRB => W_OBJ_RAM_AB,
+		I_WEB   => '0',
+		I_CEB   => '1',
+		I_DB    => x"00",
+		O_DB    => W_OBJ_RAM_DOB
+	);
+
+	lram : entity work.MC_LRAM
+	port map(
+		I_CLK  => I_CLK_12M,
+		I_ADDR => W_LRAM_A,
+		I_WE   => not I_CLK_6M,
+		I_D    => W_LRAM_DI,
+		O_D    => W_LRAM_DO
+	);
+
+
+
+k_rom : entity work.sprom
+	generic map (
+		init_file	=>  "./Rom/h.hex",
+		widthad_a	=> 11,
+		width_a		=> 8)
+	port map (
+		address	=> W_O_OBJ_ROM_A(10 downto 0),
+		clock		=> I_CLK_12M,
+		q			=> W_1H_D
+	);
+	
+h_rom : entity work.sprom
+	generic map (
+		init_file	=>  "./Rom/k.hex",
+		widthad_a	=> 11,
+		width_a		=> 8)
+	port map (
+		address	=> W_O_OBJ_ROM_A(10 downto 0),
+		clock		=> I_CLK_12M,
+		q			=> W_1K_D
+	);
+
+-----------------------------------------------------------------------------------
+
+	process(I_CLK_12M)
+	begin
+		if falling_edge(I_CLK_12M) then
+			W_LDn       <= WB_LDn;
+			W_CNTRLDn   <= WB_CNTRLDn;
+			W_CNTRCLRn  <= WB_CNTRCLRn;
+			W_COLLn     <= WB_COLLn;
+			W_VPLn      <= WB_VPLn;
+			W_OBJDATALn <= WB_OBJDATALn;
+		end if;
+	end process;
+
+	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
+	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
+	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
+
+	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
+
+	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
+	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
+
+	W_H_FLIP2 <= W_6J_Q(3);
+
+--   Parts  4F,5F
+	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
+
+	process(I_CLK_12M)
+	begin
+		if rising_edge(I_CLK_12M) then
+			W_H_POSI <= W_OBJ_RAM_DOB;
+		end if;
+	end process;
+
+--   Parts  4L
+	process(W_OBJDATALn)
+	begin
+		if rising_edge(W_OBJDATALn) then
+			W_OBJ_D <= W_H_POSI; 
+		end if;
+	end process;
+
+--   Parts  4,5N
+	W_45N_Q <= W_VF_CNT + W_H_POSI;
+	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
+
+	process(W_VPLn, I_V_BLn)
+	begin
+		if (I_V_BLn = '0') then
+			W_2M_Q <= (others => '0');
+		elsif rising_edge(W_VPLn) then
+			W_2M_Q <= W_45N_Q;
+		end if;
+	end process;
+	
+	W_2N <= I_H_CNT(8) and W_OBJ_D(7);
+	W_1M <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
+
+----  VIDEO DATA OUTPUT  --------------
+
+	W_SRLD        <= not (W_LDn or (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))));
+	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
+	W_O_OBJ_ROM_A <= W_OBJ_ROM_AB & W_1M(2 downto 0);
+
+-----------------------------------------------------------------------------------
+
+	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
+	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
+	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
+	C_2HJ   <= W_3L_Y(1 downto 0);
+	C_2KL   <= W_3L_Y(1 downto 0);
+	W_RAW0  <= W_3L_Y(2);
+	W_RAW1  <= W_3L_Y(3);
+
+--------  PARTS 2KL  ---------------------------------------------- 
+
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			case(C_2KL) is
+				when "00" => reg_2KL <= reg_2KL;
+				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
+				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
+				when "11" => reg_2KL <= W_1K_D;
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+--------  PARTS 2HJ  ---------------------------------------------- 
+
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			case(C_2HJ) is
+				when "00" => reg_2HJ <= reg_2HJ;
+				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
+				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
+				when "11" => reg_2HJ <= W_1H_D;
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+-------  SHT2 -----------------------------------------------------
+
+--  Parts 6K
+	process(W_COLLn)
+	begin
+		if rising_edge(W_COLLn) then
+			W_6K_Q <= W_H_POSI(2 downto 0);
+		end if;
+	end process;
+
+--  Parts 6P
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			if (W_LDn = '0') then
+				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
+			else
+				W_6P_Q <= W_6P_Q;
+			end if;
+		end if;
+	end process;
+
+	W_H_FLIP2X <= W_6P_Q(6);
+	W_H_FLIP1X <= W_6P_Q(5);
+	W_256HnX   <= W_6P_Q(3);
+	W_CD       <= W_6P_Q(2 downto 0);
+	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
+
+	process(I_CLK_6M, W_45T_CLR)
+	begin
+		if (W_45T_CLR = '0') then
+			W_45T_Q <= (others => '0');
+		elsif rising_edge(I_CLK_6M) then
+			if (W_CNTRLDn = '0') then
+				W_45T_Q <= W_H_POSI;
+			else
+				W_45T_Q <= W_45T_Q + 1;
+			end if;
+		end if;
+	end process;
+
+	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
+
+	process(I_CLK_6M)
+	begin
+		if falling_edge(I_CLK_6M) then
+			W_RV <= W_LRAM_DO(1 downto 0);
+			W_RC <= W_LRAM_DO(4 downto 2);
+		end if;
+	end process;
+
+	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
+
+	W_VID <= W_RV when W_RV /= "00" else W_RAW1 & W_RAW0;
+	W_COL <= W_RC when W_RV /= "00" else W_CD;
+	W_LRAM_DI <= W_COL & W_VID when W_LRAM_AND = '1' else (others => '0');
+
+	O_RAW <= W_RV;
+	O_CD  <= W_RC;
+
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_stars.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_stars.vhd
@@ -0,0 +1,90 @@
+------------------------------------------------------------------------------
+-- FPGA MOONCRESTA STARS
+--
+-- Version : 2.00
+--
+-- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+--
+-- Important !
+--
+-- This program is freeware for non-commercial use.
+-- The author does not guarantee this program.
+-- You can use this at your own risk.
+--
+------------------------------------------------------------------------------
+library ieee;
+	use ieee.std_logic_1164.all;
+	use ieee.numeric_std.all;
+
+entity MC_STARS is
+	port (
+		I_CLK_18M     : in  std_logic;
+		I_CLK_6M      : in  std_logic;
+		I_H_FLIP      : in  std_logic;
+		I_V_SYNC      : in  std_logic;
+		I_8HF         : in  std_logic;
+		I_256HnX      : in  std_logic;
+		I_1VF         : in  std_logic;
+		I_2V          : in  std_logic;
+		I_STARS_ON    : in  std_logic;
+		I_STARS_OFFn  : in  std_logic;
+
+		O_R           : out std_logic_vector(1 downto 0);
+		O_G           : out std_logic_vector(1 downto 0);
+		O_B           : out std_logic_vector(1 downto 0);
+		O_NOISE       : out std_logic
+	);
+end;
+
+architecture RTL of MC_STARS is
+	signal CLK_1C           : std_logic := '0';
+	signal W_2D_Qn          : std_logic := '0';
+	
+	signal W_3B             : std_logic := '0';
+	signal noise            : std_logic := '0';
+	signal W_2A             : std_logic := '0';
+	signal W_4P             : std_logic := '0';
+	signal CLK_1AB          : std_logic := '0';
+	signal W_1AB_Q          : std_logic_vector(15 downto 0) := (others => '0');
+	signal W_1C_Q           : std_logic_vector( 1 downto 0) := (others => '0');
+begin
+	O_R       <= (W_1AB_Q( 9) & W_1AB_Q (8) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
+	O_G       <= (W_1AB_Q(11) & W_1AB_Q(10) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
+	O_B       <= (W_1AB_Q(13) & W_1AB_Q(12) ) when (W_2A = '0' and W_4P = '0') else (others => '0');
+
+	CLK_1C    <= not (I_CLK_18M and (not I_CLK_6M )and (not I_V_SYNC) and I_256HnX);
+	CLK_1AB   <= not (CLK_1C or (not (I_H_FLIP or W_1C_Q(1))));
+	W_3B      <= W_2D_Qn xor W_1AB_Q(4);
+
+	W_2A      <= '0' when (W_1AB_Q(7 downto 0) = x"ff") else '1';
+	W_4P      <= not (( I_8HF xor I_1VF ) and W_2D_Qn and I_STARS_OFFn);
+
+	O_NOISE   <= noise ;
+
+	process(I_2V)
+	begin
+		if rising_edge(I_2V) then
+			noise <= W_2D_Qn;
+		end if;
+	end process;
+
+	process(CLK_1C, I_V_SYNC)
+	begin
+		if(I_V_SYNC = '1') then
+			W_1C_Q <= (others => '0');
+		elsif rising_edge(CLK_1C) then
+			W_1C_Q <= W_1C_Q(0) & '1';
+		end if;
+	end process;
+
+	process(CLK_1AB, I_STARS_ON)
+	begin
+		if(I_STARS_ON = '0') then
+			W_1AB_Q <= (others => '0');
+			W_2D_Qn <= '1';
+		elsif rising_edge(CLK_1AB) then
+			W_1AB_Q <= W_1AB_Q(14 downto 0) & W_3B;
+			W_2D_Qn <= not W_1AB_Q(15);
+		end if;
+	end process;
+end RTL;
--- a/Hardware/ZigZag_MiST/rtl/mc_video.vhd
+++ b/Hardware/ZigZag_MiST/rtl/mc_video.vhd
@@ -0,0 +1,425 @@
+--------------------------------------------------------------------------------
+---- FPGA GALAXIAN  VIDEO
+----
+---- Version : 2.50
+----
+---- Copyright(c) 2004 Katsumi Degawa , All rights reserved
+----
+---- Important !
+----
+---- This program is freeware for non-commercial use. 
+---- The author does not guarantee this program.
+---- You can use this at your own risk.
+----
+---- 2004- 4-30  galaxian modify by K.DEGAWA
+---- 2004- 5- 6  first release.
+---- 2004- 8-23  Improvement with T80-IP.
+---- 2004- 9-22  The problem where missile sometimes didn't come out was fixed.
+--------------------------------------------------------------------------------
+
+-------------------------------------------------------------------------------------------
+-- H_CNT(0), H_CNT(1), H_CNT(2), H_CNT(3), H_CNT(4), H_CNT(5), H_CNT(6), H_CNT(7), H_CNT(8),  
+--    1 H       2 H       4 H       8 H      16 H     32H        64 H     128 H     256 H
+-------------------------------------------------------------------------------------------
+-- V_CNT(0), V_CNT(1), V_CNT(2), V_CNT(3), V_CNT(4), V_CNT(5), V_CNT(6), V_CNT(7)  
+--    1 V      2 V       4 V       8 V       16 V      32 V      64 V     128 V 
+-------------------------------------------------------------------------------------------
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+entity MC_VIDEO is
+	port(
+		I_CLK_12M     : in  std_logic;
+		I_CLK_6M      : in  std_logic;
+		I_H_CNT       : in  std_logic_vector(8 downto 0);
+		I_V_CNT       : in  std_logic_vector(7 downto 0);
+		I_H_FLIP      : in  std_logic;
+		I_V_FLIP      : in  std_logic;
+		I_V_BLn       : in  std_logic;
+		I_C_BLn       : in  std_logic;
+
+		I_A           : in  std_logic_vector(9 downto 0);
+		I_BD          : in  std_logic_vector(7 downto 0);
+		I_OBJ_RAM_RQ  : in  std_logic;
+		I_OBJ_RAM_RD  : in  std_logic;
+		I_OBJ_RAM_WR  : in  std_logic;
+		I_VID_RAM_RD  : in  std_logic;
+		I_VID_RAM_WR  : in  std_logic;
+
+		O_C_BLnX      : out std_logic;
+		O_8HF         : out std_logic;
+		O_256HnX      : out std_logic;
+		O_1VF         : out std_logic;
+
+		O_BD          : out std_logic_vector(7 downto 0);
+		O_VID         : out std_logic_vector(1 downto 0);
+		O_COL         : out std_logic_vector(2 downto 0)
+	);
+end;
+
+architecture RTL of MC_VIDEO is
+
+	signal WB_LDn       : std_logic := '0';
+	signal WB_CNTRLDn   : std_logic := '0';
+	signal WB_CNTRCLRn  : std_logic := '0';
+	signal WB_COLLn     : std_logic := '0';
+	signal WB_VPLn      : std_logic := '0';
+	signal WB_OBJDATALn : std_logic := '0';
+	signal W_3D         : std_logic := '0';
+	signal W_LDn        : std_logic := '0';
+	signal W_CNTRLDn    : std_logic := '0';
+	signal W_CNTRCLRn   : std_logic := '0';
+	signal W_COLLn      : std_logic := '0';
+	signal W_VPLn       : std_logic := '0';
+	signal W_OBJDATALn  : std_logic := '0';
+	signal W_VID,W_VIDS : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_COL,W_COLS : std_logic_vector( 2 downto 0) := (others => '0');
+
+	signal W_H_POSI     : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_D      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_2M_Q       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_6K_Q       : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_6P_Q       : std_logic_vector( 6 downto 0) := (others => '0');
+	signal W_45T_Q      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal reg_2KL      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal reg_2HJ      : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_RV,W_RV2   : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_RC,W_RC2   : std_logic_vector( 2 downto 0) := (others => '0');
+
+	signal W_O_OBJ_ROM_A  : std_logic_vector(10 downto 0) := (others => '0');
+	signal W_VID_RAM_A    : std_logic_vector(11 downto 0) := (others => '0');
+	signal W_VID_RAM_AA   : std_logic_vector(11 downto 0) := (others => '0');
+	signal W_VID_RAM_AB   : std_logic_vector(11 downto 0) := (others => '0');
+	signal C_2HJ          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal C_2KL          : std_logic_vector( 1 downto 0) := (others => '0');
+	signal W_CD,W_CD2     : std_logic_vector( 2 downto 0) := (others => '0');
+	signal W_1M           : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_A         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_B         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_3L_Y         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_LRAM_DI      : std_logic_vector( 4 downto 0) := (others => '0');
+	signal W_LRAM_DO      : std_logic_vector( 4 downto 0) := (others => '0');
+	signal W_1H_D         : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_1K_D         : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_LRAM_A       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_ROM_A    : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_OBJ_ROM_AB   : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VID_RAM_D    : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VID_RAM_DI   : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VID_RAM_DOA  : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_VID_RAM_DOB  : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_HF_CNT       : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_45N_Q        : std_logic_vector( 7 downto 0) := (others => '0');
+	signal W_6J_Q         : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_6J_DA        : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_6J_DB        : std_logic_vector( 3 downto 0) := (others => '0');
+	signal W_256HnX       : std_logic := '0';
+	signal W_2N           : std_logic := '0';
+	signal W_45T_CLR      : std_logic := '0';
+	signal W_C_BLnX       : std_logic := '0';
+	signal W_H_FLIP1      : std_logic := '0';
+	signal W_H_FLIP2      : std_logic := '0';
+	signal W_H_FLIP1X     : std_logic := '0';
+	signal W_H_FLIP2X     : std_logic := '0';
+	signal W_LRAM_AND     : std_logic := '0';
+	signal W_RAW0         : std_logic := '0';
+	signal W_RAW1         : std_logic := '0';
+	signal W_RAW2         : std_logic_vector(1 downto 0);
+	signal W_SRLD         : std_logic := '0';
+	signal W_VID_RAM_CS   : std_logic := '0';
+
+begin
+
+	ld_pls : entity work.MC_LD_PLS
+	port map(
+		I_CLK_6M    => I_CLK_6M,
+		I_H_CNT     => I_H_CNT,
+		I_3D_DI     => W_3D,
+
+		O_LDn       => WB_LDn,
+		O_CNTRLDn   => WB_CNTRLDn,
+		O_CNTRCLRn  => WB_CNTRCLRn,
+		O_COLLn     => WB_COLLn,
+		O_VPLn      => WB_VPLn,
+		O_OBJDATALn => WB_OBJDATALn
+	);
+
+	obj_ram : entity work.MC_OBJ_RAM 
+	port map(
+		I_CLKA  => I_CLK_12M,
+		I_ADDRA => I_A(7 downto 0),
+		I_WEA   => I_OBJ_RAM_WR,
+		I_CEA   => I_OBJ_RAM_RQ,
+		I_DA    => I_BD,
+		O_DA    => W_OBJ_RAM_DOA,
+
+		I_CLKB  => I_CLK_12M,
+		I_ADDRB => W_OBJ_RAM_AB,
+		I_WEB   => '0',
+		I_CEB   => '1',
+		I_DB    => x"00",
+		O_DB    => W_OBJ_RAM_DOB
+	);
+
+	lram : entity work.MC_LRAM
+	port map(
+		I_CLK  => I_CLK_12M,
+		I_ADDR => W_LRAM_A,
+		I_WE   => not I_CLK_6M,
+		I_D    => W_LRAM_DI,
+		O_D    => W_LRAM_DO
+	);
+
+	vid_ram : entity work.MC_VID_RAM
+	port map (
+		I_CLKA  => I_CLK_12M,
+		I_ADDRA => I_A(9 downto 0),
+		I_DA    => W_VID_RAM_DI,
+		I_WEA   => I_VID_RAM_WR,
+		I_CEA   => W_VID_RAM_CS,
+		O_DA    => W_VID_RAM_DOA,
+
+		I_CLKB  => I_CLK_12M,
+		I_ADDRB => W_VID_RAM_A(9 downto 0),
+		I_DB    => x"00",
+		I_WEB   => '0',
+		I_CEB   => '1',
+		O_DB    => W_VID_RAM_DOB
+	);
+
+	
+h_rom : entity work.sprom
+	generic map (
+		init_file	=>  "./Rom/h.hex",
+		widthad_a	=> 12,
+		width_a		=> 8)
+	port map (
+		address	=> I_H_CNT(8) & W_O_OBJ_ROM_A,
+		clock		=> I_CLK_12M,
+		q			=> W_1H_D
+	);
+	
+k_rom : entity work.sprom
+	generic map (
+		init_file	=>  "./Rom/k.hex",
+		widthad_a	=> 12,
+		width_a		=> 8)
+	port map (
+		address	=> I_H_CNT(8) & W_O_OBJ_ROM_A,
+		clock		=> I_CLK_12M,
+		q			=> W_1K_D
+	);	
+
+-----------------------------------------------------------------------------------
+
+	process(I_CLK_12M)
+	begin
+		if falling_edge(I_CLK_12M) then
+			W_LDn       <= WB_LDn;
+			W_CNTRLDn   <= WB_CNTRLDn;
+			W_CNTRCLRn  <= WB_CNTRCLRn;
+			W_COLLn     <= WB_COLLn;
+			W_VPLn      <= WB_VPLn;
+			W_OBJDATALn <= WB_OBJDATALn;
+		end if;
+	end process;
+
+	W_6J_DA <= I_H_FLIP & W_HF_CNT(7) & W_HF_CNT(3) & I_H_CNT(2);
+	W_6J_DB <= W_OBJ_D(6) & ( W_HF_CNT(3) and I_H_CNT(1) ) & I_H_CNT(2) & I_H_CNT(1);
+	W_6J_Q  <= W_6J_DB when I_H_CNT(8) = '1' else W_6J_DA;
+
+	W_H_FLIP1 <= (not I_H_CNT(8)) and I_H_FLIP;
+
+	W_HF_CNT(7 downto 3)  <= not I_H_CNT(7 downto 3) when W_H_FLIP1 = '1' else I_H_CNT(7 downto 3);
+	W_VF_CNT              <= not I_V_CNT             when I_V_FLIP  = '1' else I_V_CNT;
+
+	O_8HF <= W_HF_CNT(3);
+	O_1VF <= W_VF_CNT(0);
+	W_H_FLIP2 <= W_6J_Q(3);
+
+--   Parts  4F,5F
+	W_OBJ_RAM_AB <= "0" & I_H_CNT(8) & W_6J_Q(2) & W_HF_CNT(6 downto 4) & W_6J_Q(1 downto 0);
+
+	process(I_CLK_12M)
+	begin
+		if rising_edge(I_CLK_12M) then
+			W_H_POSI <= W_OBJ_RAM_DOB;
+		end if;
+	end process;
+
+	W_OBJ_RAM_D <= W_OBJ_RAM_DOA when I_OBJ_RAM_RD = '1' else (others => '0');
+
+--   Parts  4L
+	process(W_OBJDATALn)
+	begin
+		if rising_edge(W_OBJDATALn) then
+			W_OBJ_D <= W_H_POSI; 
+		end if;
+	end process;
+
+--   Parts  4,5N
+	W_45N_Q <= W_VF_CNT + W_H_POSI;
+	W_3D    <= '0' when W_45N_Q = x"FF" else '1'; 
+
+	process(W_VPLn, I_V_BLn)
+	begin
+		if (I_V_BLn = '0') then
+			W_2M_Q <= (others => '0');
+		elsif rising_edge(W_VPLn) then
+			W_2M_Q <= W_45N_Q;
+		end if;
+	end process;
+	
+	W_2N          <= I_H_CNT(8) and W_OBJ_D(7);
+	W_1M          <= W_2M_Q(3 downto 0) xor (W_2N & W_2N & W_2N & W_2N);
+	W_VID_RAM_CS  <= I_VID_RAM_RD or I_VID_RAM_WR;
+	W_VID_RAM_DI  <= I_BD when I_VID_RAM_WR = '1' else (others => '0');
+	W_VID_RAM_AA  <= (not ( W_2M_Q(7) and W_2M_Q(6) and W_2M_Q(5) and W_2M_Q(4))) & (not W_VID_RAM_CS) & "0000000000"; -- I_A(9:0)
+	W_VID_RAM_AB  <= "00" & W_2M_Q(7 downto 4) & W_1M(3) & W_HF_CNT(7 downto 3);
+	W_VID_RAM_A   <= W_VID_RAM_AB when I_C_BLn = '1' else W_VID_RAM_AA;
+	W_VID_RAM_D   <= W_VID_RAM_DOA when I_VID_RAM_RD = '1' else (others => '0');
+
+----  VIDEO DATA OUTPUT  --------------
+
+	O_BD          <= W_OBJ_RAM_D or W_VID_RAM_D;
+	W_SRLD        <= not (W_LDn or W_VID_RAM_A(11));
+	W_OBJ_ROM_AB  <= W_OBJ_D(5 downto 0) & W_1M(3) & (W_OBJ_D(6) xor I_H_CNT(3));
+	W_OBJ_ROM_A   <= W_OBJ_ROM_AB when I_H_CNT(8) = '1' else W_VID_RAM_DOB;
+	W_O_OBJ_ROM_A <= W_OBJ_ROM_A & W_1M(2 downto 0);
+
+-----------------------------------------------------------------------------------
+
+	W_3L_A  <= reg_2HJ(7) & reg_2KL(7) & "1"    & W_SRLD;
+	W_3L_B  <= reg_2HJ(0) & reg_2KL(0) & W_SRLD & "1";
+	W_3L_Y  <= W_3L_B when W_H_FLIP2X = '1' else W_3L_A;   --  (3)=RAW1,(2)=RAW0
+	C_2HJ   <= W_3L_Y(1 downto 0);
+	C_2KL   <= W_3L_Y(1 downto 0);
+	W_RAW0  <= W_3L_Y(2);
+	W_RAW1  <= W_3L_Y(3);
+
+--------  PARTS 2KL  ---------------------------------------------- 
+
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			case(C_2KL) is
+				when "00" => reg_2KL <= reg_2KL;
+				when "10" => reg_2KL <= reg_2KL(6 downto 0) & "0";
+				when "01" => reg_2KL <= "0" & reg_2KL(7 downto 1);
+				when "11" => reg_2KL <= W_1K_D;
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+--------  PARTS 2HJ  ---------------------------------------------- 
+
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			case(C_2HJ) is
+				when "00" => reg_2HJ <= reg_2HJ;
+				when "10" => reg_2HJ <= reg_2HJ(6 downto 0) & "0";
+				when "01" => reg_2HJ <= "0" & reg_2HJ(7 downto 1);
+				when "11" => reg_2HJ <= W_1H_D;
+				when others => null;
+			end case;
+		end if;
+	end process;
+
+-------  SHT2 -----------------------------------------------------
+
+--  Parts 6K
+	process(W_COLLn)
+	begin
+		if rising_edge(W_COLLn) then
+			W_6K_Q <= W_H_POSI(2 downto 0);
+		end if;
+	end process;
+
+--  Parts 6P
+	process(I_CLK_6M)
+	begin
+		if rising_edge(I_CLK_6M) then
+			if (W_LDn = '0') then
+				W_6P_Q <= W_H_FLIP2 & W_H_FLIP1 & I_C_BLn & (not I_H_CNT(8)) & W_6K_Q(2 downto 0);
+			else
+				W_6P_Q <= W_6P_Q;
+			end if;
+		end if;
+	end process;
+
+	W_H_FLIP2X <= W_6P_Q(6);
+	W_H_FLIP1X <= W_6P_Q(5);
+	W_C_BLnX   <= W_6P_Q(4);
+	W_256HnX   <= W_6P_Q(3);
+	W_CD       <= W_6P_Q(2 downto 0);
+	O_256HnX   <= W_256HnX;
+	O_C_BLnX   <= W_C_BLnX;
+	W_45T_CLR  <= W_CNTRCLRn or W_256HnX ;
+
+	process(I_CLK_6M, W_45T_CLR)
+	begin
+		if (W_45T_CLR = '0') then
+			W_45T_Q <= (others => '0');
+		elsif rising_edge(I_CLK_6M) then
+			if (W_CNTRLDn = '0') then
+				W_45T_Q <= W_H_POSI;
+			else
+				W_45T_Q <= W_45T_Q + 1;
+			end if;
+		end if;
+	end process;
+
+	W_LRAM_A <= (not W_45T_Q) when W_H_FLIP1X = '1' else W_45T_Q;
+
+	process(I_CLK_6M)
+	begin
+		if falling_edge(I_CLK_6M) then
+			W_RV <= W_LRAM_DO(1 downto 0);
+			W_RC <= W_LRAM_DO(4 downto 2);
+		end if;
+	end process;
+
+	W_LRAM_AND <= not (not ((W_LRAM_A(4) or W_LRAM_A(5)) or (W_LRAM_A(6) or W_LRAM_A(7))) or W_256HnX );
+
+	SPRITE2 : work.mc_sprite
+	port map(
+		I_CLK_12M    => I_CLK_12M,
+		I_CLK_6M     => I_CLK_6M,
+		I_H_CNT      => I_H_CNT,
+		I_V_CNT      => I_V_CNT,
+		I_H_FLIP     => I_H_FLIP,
+		I_V_FLIP     => I_V_FLIP,
+		I_V_BLn      => I_V_BLn,
+		I_C_BLn      => I_C_BLn,
+		I_A          => I_A xor x"20",
+		I_BD         => I_BD,
+		I_OBJ_RAM_RQ => I_OBJ_RAM_RQ,
+		I_OBJ_RAM_WR => I_OBJ_RAM_WR,
+		O_RAW        => W_RAW2,
+		O_CD         => W_CD2
+	);
+
+	W_VIDS <= W_RV when W_RV /= "00" else W_RAW2;
+	W_COLS <= W_RC when W_RV /= "00" else W_CD2;
+
+	W_RV2 <= W_RV when W_LRAM_AND = '1' else W_VIDS;
+	W_RC2 <= W_RC when W_LRAM_AND = '1' else W_COLS;
+
+	W_VID <= W_RV2 when W_RV2 /= "00" else W_RAW1 & W_RAW0;
+	W_COL <= W_RC2 when W_RV2 /= "00" else W_CD;
+	W_LRAM_DI <= W_COL & W_VID when W_LRAM_AND = '1' else (others => '0');
+
+	O_VID <= W_VID;
+	O_COL <= W_COL;
+
+end RTL;
+
--- a/Hardware/ZigZag_MiST/rtl/mist_io.v
+++ b/Hardware/ZigZag_MiST/rtl/mist_io.v
@@ -0,0 +1,491 @@
+//
+// mist_io.v
+//
+// mist_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
+//                                                           (Sorgelig)
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = clk_sys/(PS2DIV*2)
+//
+
+module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
+(
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+
+	input             CONF_DATA0,
+	input             SPI_SS2,
+	output            SPI_DO,
+	input             SPI_DI,
+
+	output reg  [7:0] joystick_0,
+	output reg  [7:0] joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output      [1:0] buttons,
+	output      [1:0] switches,
+	output            scandoubler_disable,
+	output            ypbpr,
+
+	output reg [31:0] status,
+
+	// SD config
+	input             sd_conf,
+	input             sd_sdhc,
+	output            img_mounted, // signaling that new image has been mounted
+	output reg [31:0] img_size,    // size of image in bytes
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input             sd_rd,
+	input             sd_wr,
+	output reg        sd_ack,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg  [8:0] sd_buff_addr,
+	output reg  [7:0] sd_buff_dout,
+	input       [7:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk,
+	output reg        ps2_kbd_data,
+	output            ps2_mouse_clk,
+	output reg        ps2_mouse_data,
+	input             ps2_caps_led,
+
+	// ARM -> FPGA download
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output            ioctl_wr,
+	output reg [24:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+reg [7:0] b_data;
+reg [6:0] sbuf;
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
+reg [7:0] but_sw;
+reg [2:0] stick_idx;
+
+reg    mount_strobe = 0;
+assign img_mounted  = mount_strobe;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+wire [7:0] spi_dout = { sbuf, SPI_DI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+reg spi_do;
+assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
+
+wire [7:0] kbd_led = { 2'b01, 4'b0000, ps2_caps_led, 1'b1};
+
+// drive MISO only when transmitting core id
+always@(negedge SPI_SCK) begin
+	if(!CONF_DATA0) begin
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  spi_do <= core_type[~bit_cnt];
+
+		end else begin
+			case(cmd)
+				// reading config string
+				8'h14: begin
+					// returning a byte from string
+						if(byte_cnt < STRLEN + 1) spi_do <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+							else spi_do <= 0;
+					end
+
+				// reading sd card status
+				8'h16: begin
+						if(byte_cnt == 1) spi_do <= sd_cmd[~bit_cnt];
+						else if((byte_cnt >= 2) && (byte_cnt < 6)) spi_do <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+						else spi_do <= 0;
+					end
+
+				// reading sd card write data
+				8'h18:
+						spi_do <= b_data[~bit_cnt];
+
+				// reading keyboard LED status
+				8'h1f:
+						spi_do <= kbd_led[~bit_cnt];
+
+				default:
+						spi_do <= 0;
+			endcase
+		end
+   end
+end
+
+reg b_wr2,b_wr3;
+always @(negedge clk_sys) begin
+	b_wr3      <= b_wr2;
+	sd_buff_wr <= b_wr3;
+end
+
+// SPI receiver
+always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+
+	if(CONF_DATA0) begin
+		b_wr2 <= 0;
+	   bit_cnt <= 0;
+	   byte_cnt <= 0;
+		sd_ack <= 0;
+		sd_ack_conf <= 0;
+	end else begin
+		b_wr2 <= 0;
+
+		sbuf <= spi_dout[6:0];
+		bit_cnt <= bit_cnt + 1'd1;
+		if(bit_cnt == 5) begin
+			if (byte_cnt == 0) sd_buff_addr <= 0;
+			if((byte_cnt != 0) & (sd_buff_addr != 511)) sd_buff_addr <= sd_buff_addr + 1'b1;
+			if((byte_cnt == 1) & ((cmd == 8'h17) | (cmd == 8'h19))) sd_buff_addr <= 0;
+		end
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
+			if(byte_cnt == 0) begin
+				cmd <= spi_dout;
+
+				if(spi_dout == 8'h19) begin
+					sd_ack_conf  <= 1;
+					sd_buff_addr <= 0;
+				end
+				if((spi_dout == 8'h17) || (spi_dout == 8'h18)) begin
+					sd_ack       <= 1;
+					sd_buff_addr <= 0;
+				end
+				if(spi_dout == 8'h18) b_data <= sd_buff_din;
+
+				mount_strobe <= 0;
+
+			end else begin
+			
+				case(cmd)
+					// buttons and switches
+					8'h01: but_sw <= spi_dout; 
+					8'h02: joystick_0 <= spi_dout;
+					8'h03: joystick_1 <= spi_dout;
+
+					// store incoming ps2 mouse bytes 
+					8'h04: begin
+							ps2_mouse_fifo[ps2_mouse_wptr] <= spi_dout; 
+							ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+						end
+
+					// store incoming ps2 keyboard bytes 
+					8'h05: begin
+							ps2_kbd_fifo[ps2_kbd_wptr] <= spi_dout; 
+							ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+						end
+				
+					8'h15: status[7:0] <= spi_dout;
+				
+					// send SD config IO -> FPGA
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					8'h19,
+					// send sector IO -> FPGA
+					// flag that download begins
+					8'h17: begin
+							sd_buff_dout <= spi_dout;
+							b_wr2 <= 1;
+						end
+
+					8'h18: b_data <= sd_buff_din;
+
+					// joystick analog
+					8'h1a: begin
+							// first byte is joystick index
+							if(byte_cnt == 1) stick_idx <= spi_dout[2:0];
+							else if(byte_cnt == 2) begin
+								// second byte is x axis
+								if(stick_idx == 0) joystick_analog_0[15:8] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_dout;
+							end else if(byte_cnt == 3) begin
+								// third byte is y axis
+								if(stick_idx == 0) joystick_analog_0[7:0] <= spi_dout;
+									else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_dout;
+							end
+						end
+
+					// notify image selection
+					8'h1c: mount_strobe <= 1;
+
+					// send image info
+					8'h1d: if(byte_cnt<5) img_size[(byte_cnt-1)<<3 +:8] <= spi_dout;
+
+					// status, 32bit version
+					8'h1e: if(byte_cnt<5) status[(byte_cnt-1)<<3 +:8] <= spi_dout;
+					default: ;
+				endcase
+			end
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+// keyboard
+reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_kbd_r_inc <= 0;
+
+		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1;
+
+				// reset parity
+				ps2_kbd_parity <= 1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
+			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
+
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
+				else ps2_kbd_tx_state <= 0;
+		end
+	end
+end
+
+// mouse
+reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_mouse_r_inc <= 0;
+
+		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1;
+
+				// reset parity
+				ps2_mouse_parity <= 1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
+				else ps2_mouse_tx_state <= 0;
+		end
+	end
+end
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+reg  [7:0] data_w;
+reg [24:0] addr_w;
+reg        rclk   = 0;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [24:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		rclk <= 0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// increase target address after write
+		if(rclk) addr <= addr + 1'd1;
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+      if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+				addr <= 0;
+				ioctl_download <= 1; 
+			end else begin
+				addr_w <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			addr_w <= addr;
+			data_w <= {sbuf, SPI_DI};
+			rclk <= 1;
+		end
+
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+assign ioctl_wr = |ioctl_wrd;
+reg [1:0] ioctl_wrd;
+
+always@(negedge clk_sys) begin
+	reg        rclkD, rclkD2;
+
+	rclkD    <= rclk;
+	rclkD2   <= rclkD;
+	ioctl_wrd<= {ioctl_wrd[0],1'b0};
+
+	if(rclkD & ~rclkD2) begin
+		ioctl_dout <= data_w;
+		ioctl_addr <= addr_w;
+		ioctl_wrd  <= 2'b11;
+	end
+end
+
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/osd.v
+++ b/Hardware/ZigZag_MiST/rtl/osd.v
@@ -0,0 +1,179 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+	
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+      
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350); 
+
+reg ce_pix;
+always @(negedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin	
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin	
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin	
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin	
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+
+wire osd_de = osd_enable && 
+              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+reg  [7:0] osd_byte; 
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/pll.qip
+++ b/Hardware/ZigZag_MiST/rtl/pll.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
--- a/Hardware/ZigZag_MiST/rtl/pll.vhd
+++ b/Hardware/ZigZag_MiST/rtl/pll.vhd
@@ -0,0 +1,451 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2013 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		c3		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		clk3_divide_by		: NATURAL;
+		clk3_duty_cycle		: NATURAL;
+		clk3_multiply_by		: NATURAL;
+		clk3_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire2    <= sub_wire0(3);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c3    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 9,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 8,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 3,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 2,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 9,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 4,
+		clk2_phase_shift => "0",
+		clk3_divide_by => 9,
+		clk3_duty_cycle => 50,
+		clk3_multiply_by => 2,
+		clk3_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_USED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		areset => areset,
+		inclk => sub_wire6,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
+-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "9"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "12.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "4"
+-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "2"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "12.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "4"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9"
+-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
--- a/Hardware/ZigZag_MiST/rtl/scandoubler.v
+++ b/Hardware/ZigZag_MiST/rtl/scandoubler.v
@@ -0,0 +1,194 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	input             ce_pix_actual,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             line_start,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+assign vs_out = vs_in;
+
+reg  [2:0] phase;
+reg  [2:0] ce_div;
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4;
+reg req_line_reset;
+wire ls_in = hs_in | line_start;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		phase <= phase + 1'd1;
+		ce_x4 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+		phase <= phase + 1'd1;
+
+		ce_cnt <= ce_cnt + 1'd1;
+		if(ce_pix_actual) begin
+			phase <= 0;
+			ce_div <= ce_cnt + 1'd1;
+			ce_cnt <= 0;
+			req_line_reset <= 0;
+		end
+
+		if(ls_in) req_line_reset <= 1;
+	end
+end
+
+reg ce_sd;
+always @(*) begin
+	case(ce_div)
+		2: ce_sd = !phase[0];
+		4: ce_sd = !phase[1:0];
+		default: ce_sd <= 1;
+	endcase
+end
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4 & ce_sd),
+	.inputpixel({b_in,g_in,r_in}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.read_x(sd_h_actual),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [10:0] sd_h_actual;
+always @(*) begin
+	case(ce_div)
+		2: sd_h_actual = sd_h[10:1];
+		4: sd_h_actual = sd_h[10:2];
+		default: sd_h_actual = sd_h;
+	endcase
+end
+
+reg [10:0] sd_h;
+reg  [1:0] sd_line;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise,hs_ls;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+
+	reg hs, hs2, vs, ls;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		ls <= ls_in;
+
+		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+		sd_h    <= sd_h    + 1'd1;
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+
+		if(sd_hcnt == hs_ls)   sd_h    <= 0;
+		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
+	end
+end
+
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/spram.vhd
+++ b/Hardware/ZigZag_MiST/rtl/spram.vhd
@@ -0,0 +1,55 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY spram IS
+	generic (
+		 addr_width_g : integer := 8;
+		 data_width_g : integer := 8
+	); 
+	PORT
+	(
+		address	: IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
+		clken		: IN STD_LOGIC  := '1';
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q			: OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+BEGIN
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "NORMAL",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone V",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**addr_width_g,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => addr_width_g,
+		width_a => data_width_g,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		clocken0 => clken,
+		data_a => data,
+		wren_a => wren,
+		q_a => q
+	);
+
+
+
+END SYN;
--- a/Hardware/ZigZag_MiST/rtl/sprom.vhd
+++ b/Hardware/ZigZag_MiST/rtl/sprom.vhd
@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
--- a/Hardware/ZigZag_MiST/rtl/video_mixer.sv
+++ b/Hardware/ZigZag_MiST/rtl/video_mixer.sv
@@ -0,0 +1,243 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 3 bits per component
+//              For half depth 6 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0,
+
+	parameter OSD_COLOR    = 3'd4,
+	parameter OSD_X_OFFSET = 10'd0,
+	parameter OSD_Y_OFFSET = 10'd0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input        clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input        ce_pix,
+
+	// Some systems have multiple resolutions.
+	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
+	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
+	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
+	input        ce_pix_actual,
+
+	// OSD SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input  [1:0] scanlines,
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	input        scandoubler_disable,
+
+	// High quality 2x scaling
+	input        hq2x,
+
+	// YPbPr always uses composite sync
+	input        ypbpr,
+
+	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
+	input        ypbpr_full,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// interlace sync. Positive pulses.
+	input        HSync,
+	input        VSync,
+
+	// Falling of this signal means start of informative part of line.
+	// It can be horizontal blank signal.
+	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
+	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
+	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
+	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
+	// before first informative pixel.
+	input        line_start,
+
+	// MiST video output signals
+	output [5:0] VGA_R,
+	output [5:0] VGA_G,
+	output [5:0] VGA_B,
+	output       VGA_VS,
+	output       VGA_HS
+);
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd;
+reg [DWIDTH:0] Rd,Gd,Bd;
+always @(posedge clk_sys) {Rd,Gd,Bd} <= {R,G,B};
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.r_in(Rd),
+	.g_in(Gd),
+	.b_in(Bd),
+
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [5:0] r  = rt;
+		wire [5:0] g  = gt;
+		wire [5:0] b  = bt;
+	end
+endgenerate
+
+wire       hs = (scandoubler_disable ? HSync : hs_sd);
+wire       vs = (scandoubler_disable ? VSync : vs_sd);
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [5:0] r_out, g_out, b_out;
+always @(*) begin
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
+			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
+			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			r_out = {1'b0, r[5:1]};
+			g_out = {1'b0, g[5:1]};
+			b_out = {1'b0, b[5:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			r_out = {2'b00, r[5:2]};
+			g_out = {2'b00, g[5:2]};
+			b_out = {2'b00, b[5:2]};
+		end
+
+		default: begin
+			r_out = r;
+			g_out = g;
+			b_out = b;
+		end
+	endcase
+end
+
+wire [5:0] red, green, blue;
+osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
+(
+	.*,
+
+	.R_in(r_out),
+	.G_in(g_out),
+	.B_in(b_out),
+	.HSync(hs),
+	.VSync(vs),
+
+	.R_out(red),
+	.G_out(green),
+	.B_out(blue)
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
+assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
+assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
+assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+
+endmodule
--- a/Hardware/ZigZag_MiST/rtl/ym2149.sv
+++ b/Hardware/ZigZag_MiST/rtl/ym2149.sv
@@ -0,0 +1,331 @@
+//
+// Copyright (c) MikeJ - Jan 2005
+// Copyright (c) 2016-2018 Sorgelig
+//
+// All rights reserved
+//
+// Redistribution and use in source and synthezised forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in synthesized form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// Neither the name of the author nor the names of other contributors may
+// be used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+
+// BDIR  BC  MODE
+//   0   0   inactive
+//   0   1   read value
+//   1   0   write value
+//   1   1   set address
+//
+
+module ym2149
+(
+	input        CLK,       // Global clock
+	input        CE,        // PSG Clock enable
+	input        RESET,     // Chip RESET (set all Registers to '0', active hi)
+	input        BDIR,      // Bus Direction (0 - read , 1 - write)
+	input        BC,        // Bus control
+	input  [7:0] DI,        // Data In
+	output [7:0] DO,        // Data Out
+	output [7:0] CHANNEL_A, // PSG Output channel A
+	output [7:0] CHANNEL_B, // PSG Output channel B
+	output [7:0] CHANNEL_C, // PSG Output channel C
+
+	input        SEL,
+	input        MODE,
+	
+	output [5:0] ACTIVE,
+
+	input  [7:0] IOA_in,
+	output [7:0] IOA_out,
+
+	input  [7:0] IOB_in,
+	output [7:0] IOB_out
+);
+
+assign ACTIVE  = ~ymreg[7][5:0];
+assign IOA_out = ymreg[14];
+assign IOB_out = ymreg[15];
+
+reg [7:0] addr;
+reg [7:0] ymreg[16];
+
+// Write to PSG
+reg env_reset;
+always @(posedge CLK) begin
+	if(RESET) begin
+		ymreg     <= '{default:0};
+		ymreg[7]  <= '1;
+		addr      <= '0;
+		env_reset <= 0;
+	end else begin
+		env_reset <= 0;
+		if(BDIR) begin
+			if(BC) addr <= DI;
+			else if(!addr[7:4]) begin
+				ymreg[addr[3:0]] <= DI;
+				env_reset <= (addr == 13);
+			end
+		end
+	end
+end
+
+// Read from PSG
+assign DO = dout;
+reg [7:0] dout;
+always_comb begin
+	dout = 8'hFF;
+	if(~BDIR & BC & !addr[7:4]) begin
+		case(addr[3:0])
+			 0: dout = ymreg[0];
+			 1: dout = ymreg[1][3:0];
+			 2: dout = ymreg[2];
+			 3: dout = ymreg[3][3:0];
+			 4: dout = ymreg[4];
+			 5: dout = ymreg[5][3:0];
+			 6: dout = ymreg[6][4:0];
+			 7: dout = ymreg[7];
+			 8: dout = ymreg[8][4:0];
+			 9: dout = ymreg[9][4:0];
+			10: dout = ymreg[10][4:0];
+			11: dout = ymreg[11];
+			12: dout = ymreg[12];
+			13: dout = ymreg[13][3:0];
+			14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
+			15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
+		endcase
+	end
+end
+
+reg ena_div;
+reg ena_div_noise;
+
+//  p_divider
+always @(posedge CLK) begin
+	reg [3:0]  cnt_div;
+	reg        noise_div;
+
+	if(CE) begin
+		ena_div <= 0;
+		ena_div_noise <= 0;
+		if(!cnt_div) begin
+			cnt_div <= {SEL, 3'b111};
+			ena_div <= 1;
+            
+			noise_div <= (~noise_div);
+			if (noise_div) ena_div_noise <= 1;
+		end else begin
+			cnt_div <= cnt_div - 1'b1;
+		end
+	end
+end
+
+
+reg [2:0] noise_gen_op;
+
+//  p_noise_gen
+always @(posedge CLK) begin
+	reg [16:0] poly17;
+	reg [4:0]  noise_gen_cnt;
+
+	if(CE) begin
+		if (ena_div_noise) begin
+			if(ymreg[6][4:0]) begin
+				if (noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
+					noise_gen_cnt <= 0;
+					poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
+				end else begin
+					noise_gen_cnt <= noise_gen_cnt + 1'd1;
+				end
+				noise_gen_op <= {3{poly17[0]}};
+			end else begin
+				noise_gen_op <= ymreg[7][5:3];
+				noise_gen_cnt <= 0;
+			end
+		end
+	end
+end
+
+wire [11:0] tone_gen_freq[1:3];
+assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
+assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
+assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
+
+reg [3:1] tone_gen_op;
+
+//p_tone_gens
+always @(posedge CLK) begin
+	integer i;
+	reg [11:0] tone_gen_cnt[1:3];
+
+	if(CE) begin
+		// looks like real chips count up - we need to get the Exact behaviour ..
+	
+		for (i = 1; i <= 3; i = i + 1) begin
+			if(ena_div) begin
+				if (tone_gen_freq[i]) begin
+					if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
+						tone_gen_cnt[i] <= 0;
+						tone_gen_op[i]  <= ~tone_gen_op[i];
+					end else begin
+						tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
+					end
+				end else begin
+					tone_gen_op[i] <= ymreg[7][i];
+					tone_gen_cnt[i] <= 0;
+				end
+			end
+		end
+	end
+end
+
+reg env_ena;
+wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
+
+//p_envelope_freq
+always @(posedge CLK) begin
+	reg [15:0] env_gen_cnt;
+
+	if(CE) begin
+		env_ena <= 0;
+		if(ena_div) begin
+			if (env_gen_cnt >= env_gen_comp) begin
+				env_gen_cnt <= 0;
+				env_ena <= 1;
+			end else begin
+				env_gen_cnt <= (env_gen_cnt + 1'd1);
+			end
+		end
+	end
+end
+
+reg [4:0] env_vol;
+
+wire is_bot    = (env_vol == 5'b00000);
+wire is_bot_p1 = (env_vol == 5'b00001);
+wire is_top_m1 = (env_vol == 5'b11110);
+wire is_top    = (env_vol == 5'b11111);
+
+always @(posedge CLK) begin
+	reg env_hold;
+	reg env_inc;
+
+	// envelope shapes
+	// C AtAlH
+	// 0 0 x x  \___
+	//
+	// 0 1 x x  /___
+	//
+	// 1 0 0 0  \\\\
+	//
+	// 1 0 0 1  \___
+	//
+	// 1 0 1 0  \/\/
+	//           ___
+	// 1 0 1 1  \
+	//
+	// 1 1 0 0  ////
+	//           ___
+	// 1 1 0 1  /
+	//
+	// 1 1 1 0  /\/\
+	//
+	// 1 1 1 1  /___
+
+	if(env_reset | RESET) begin
+		// load initial state
+		if(!ymreg[13][2]) begin		// attack
+			env_vol <= 5'b11111;
+			env_inc <= 0;		// -1
+		end else begin
+			env_vol <= 5'b00000;
+			env_inc <= 1;		// +1
+		end
+		env_hold <= 0;
+	end
+	else if(CE) begin
+		if (env_ena) begin
+			if (!env_hold) begin
+				if (env_inc) env_vol <= (env_vol + 5'b00001);
+					else env_vol <= (env_vol + 5'b11111);
+			end
+
+			// envelope shape control.
+			if(!ymreg[13][3]) begin
+				if(!env_inc) begin	// down
+					if(is_bot_p1) env_hold <= 1;
+				end else if (is_top) env_hold <= 1;
+			end else if(ymreg[13][0]) begin		// hold = 1
+				if(!env_inc) begin	// down
+					if(ymreg[13][1]) begin		// alt
+						if(is_bot) env_hold <= 1;
+					end else if(is_bot_p1) env_hold <= 1;
+				end else if(ymreg[13][1]) begin	// alt
+					if(is_top) env_hold <= 1;
+				end else if(is_top_m1) env_hold <= 1;
+			end else if(ymreg[13][1]) begin		// alternate
+				if(env_inc == 1'b0) begin		// down
+					if(is_bot_p1) env_hold <= 1;
+					if(is_bot) begin
+						env_hold <= 0;
+						env_inc  <= 1;
+					end
+				end else begin
+					if(is_top_m1) env_hold <= 1;
+					if(is_top) begin
+						env_hold <= 0;
+						env_inc  <= 0;
+					end
+				end
+			end
+		end
+	end
+end
+
+reg [5:0] A,B,C;
+always @(posedge CLK) begin
+	A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4]  ? env_vol[4:0] : { ymreg[8][3:0],  ymreg[8][3]}};
+	B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4]  ? env_vol[4:0] : { ymreg[9][3:0],  ymreg[9][3]}};
+	C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
+end
+
+wire [7:0] volTable[64] = '{
+	//YM2149
+	8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04, 
+	8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13, 
+	8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47, 
+	8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
+
+	//AY8910
+	8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06, 
+	8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22, 
+	8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72, 
+	8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff 
+};
+
+assign CHANNEL_A = volTable[A];
+assign CHANNEL_B = volTable[B];
+assign CHANNEL_C = volTable[C];
+
+endmodule