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Add rotated OSD

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This commit is contained in:
Marcel 2019-03-03 18:28:55 +01:00
parent 1118dc9dd8
commit a453cc39f3
9 changed files with 83 additions and 52 deletions
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30
Arcade_MiST/Custom Hardware/Galaga_MIST/galaga_mist.qsf
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@ -102,29 +102,18 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE rtl/mb88.vhd
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd
set_global_assignment -name VHDL_FILE rtl/galaga_mist.vhd
set_global_assignment -name VHDL_FILE rtl/galaga.vhd
set_global_assignment -name VHDL_FILE rtl/stars.vhd
set_global_assignment -name VHDL_FILE rtl/sp_palette.vhd
set_global_assignment -name VHDL_FILE rtl/sp_graphx.vhd
set_global_assignment -name VHDL_FILE rtl/sound_seq.vhd
set_global_assignment -name VHDL_FILE rtl/sound_samples.vhd
set_global_assignment -name VHDL_FILE rtl/sound_machine.vhd
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/rgb.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VHDL_FILE rtl/galaga_mist.vhd
set_global_assignment -name VHDL_FILE rtl/galaga_cpu3.vhd
set_global_assignment -name VHDL_FILE rtl/galaga_cpu2.vhd
set_global_assignment -name VHDL_FILE rtl/galaga_cpu1.vhd
set_global_assignment -name VHDL_FILE rtl/galaga.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/stars_machine.vhd
set_global_assignment -name VHDL_FILE rtl/cs54xx_prog.vhd
set_global_assignment -name VHDL_FILE rtl/bg_palette.vhd
set_global_assignment -name VHDL_FILE rtl/bg_graphx.vhd
@ -135,4 +124,17 @@ set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/mb88.vhd
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VHDL_FILE rtl/rgb.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

4
Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/galaga_mist.vhd
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@ -100,7 +100,7 @@ architecture struct of galaga_mist is
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
rotate : in std_logic_vector(1 downto 0);
R, G, B : in std_logic_vector(2 downto 0);
HSync, VSync, line_start, mono : in std_logic;
@ -150,7 +150,7 @@ vmixer : video_mixer
hq2x => hq2x,
ypbpr => ypbpr,
ypbpr_full => '1',
rotate => '1' & not status(4),
R => VGA_R_O,
G => VGA_G_O,
B => VGA_B_O,

39
Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/osd.v
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@ -11,13 +11,15 @@ module osd (
input SPI_SS3,
input SPI_DI,
input [1:0] rotate, //[0] - rotate [1] - left or right
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
@ -59,7 +61,7 @@ always@(posedge SPI_SCK, posedge SPI_SS3) begin
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
@ -91,7 +93,7 @@ reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
@ -124,13 +126,13 @@ always @(posedge clk_sys) begin
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
@ -142,13 +144,13 @@ always @(posedge clk_sys) begin
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
@ -160,17 +162,30 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
wire osd_de = osd_enable &&
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
reg [10:0] osd_buffer_addr;
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
reg osd_pixel;
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
always @(posedge clk_sys) begin
if(ce_pix) begin
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
end
end
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};

3
Arcade_MiST/Custom Hardware/Galaga_MIST/rtl/video_mixer.sv
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@ -60,7 +60,7 @@ module video_mixer
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
input [1:0] rotate, //[0] - rotate [1] - left or right
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
@ -182,6 +182,7 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.rotate(rotate),
.R_out(red),
.G_out(green),

2
Arcade_MiST/Custom Hardware/Phoenix_MIST/README.txt
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@ -8,7 +8,7 @@
-- https://sourceforge.net/projects/darfpga/files/Software%20VHDL/phoenix/
---------------------------------------------------------------------------------
--
-- Only controls are rotated on VGA output.
-- Only controls and OSD are rotated on VGA output.
--
--
-- Keyboard inputs :

BIN
Arcade_MiST/Custom Hardware/Phoenix_MIST/Release/phoenix_mist.rbf
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Binary file not shown.

46
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/osd.v
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@ -11,19 +11,19 @@ module osd (
input SPI_SS3,
input SPI_DI,
input [1:0] rotate, //[0] - rotate [1] - left or right
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out,
output reg osd_enabled
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
@ -39,6 +39,7 @@ localparam OSD_HEIGHT = 10'd128;
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
@ -60,12 +61,12 @@ always@(posedge SPI_SCK, posedge SPI_SS3) begin
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enabled <= SPI_DI;
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
@ -92,7 +93,7 @@ reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
@ -125,13 +126,13 @@ always @(posedge clk_sys) begin
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
@ -143,13 +144,13 @@ always @(posedge clk_sys) begin
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
@ -161,17 +162,30 @@ wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_hcnt = h_cnt - h_osd_start;
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire [9:0] osd_hcnt_next = osd_hcnt + 2'd1; // one pixel offset for osd pixel
wire [9:0] osd_hcnt_next2 = osd_hcnt + 2'd2; // two pixel offset for osd byte address register
wire osd_de = osd_enabled &&
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
reg [10:0] osd_buffer_addr;
wire [7:0] osd_byte = osd_buffer[osd_buffer_addr];
reg osd_pixel;
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
always @(posedge clk_sys) begin
if(ce_pix) begin
osd_buffer_addr <= rotate[0] ? {rotate[1] ? osd_hcnt_next2[7:5] : ~osd_hcnt_next2[7:5],
rotate[1] ? (doublescan ? ~osd_vcnt[7:0] : ~{osd_vcnt[6:0], 1'b0}) :
(doublescan ? osd_vcnt[7:0] : {osd_vcnt[6:0], 1'b0})} :
{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt_next2[7:0]};
osd_pixel <= rotate[0] ? osd_byte[rotate[1] ? osd_hcnt_next[4:2] : ~osd_hcnt_next[4:2]] :
osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
end
end
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};

6
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/phoenix_mist.vhd
View File

@ -86,7 +86,7 @@ architecture struct of phoenix_mist is
signal upjoyR : std_logic;
signal upjoyB : std_logic;
-- config string used by the io controller to fill the OSD
constant CONF_STR : string := "PHOENIX;;O4,Screen Direction,Upright,Normal;O67,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.0;";
constant CONF_STR : string := "PHOENIX;;O4,Screen Direction,Upright,Normal;O67,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;T5,Reset;V,v1.1;";
function to_slv(s: string) return std_logic_vector is
constant ss: string(1 to s'length) := s;
@ -126,7 +126,7 @@ architecture struct of phoenix_mist is
SPI_SCK, SPI_SS3, SPI_DI : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic;
rotate : in std_logic_vector(1 downto 0);
R, G, B : in std_logic_vector(2 downto 0);
HSync, VSync, line_start, mono : in std_logic;
@ -282,7 +282,7 @@ begin
SPI_SCK => SPI_SCK,
SPI_SS3 => SPI_SS3,
SPI_DI => SPI_DI,
rotate => '1' & not status(4),
scanlines => scanlines,
scandoubler_disable => scandoubler_disable,
hq2x => hq2x,

5
Arcade_MiST/Custom Hardware/Phoenix_MIST/rtl/video_mixer.sv
View File

@ -60,7 +60,7 @@ module video_mixer
// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
input ypbpr_full,
input [1:0] rotate, //[0] - rotate [1] - left or right
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
@ -82,8 +82,6 @@ module video_mixer
// before first informative pixel.
input line_start,
output osd_enabled,
// MiST video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
@ -184,6 +182,7 @@ osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
.B_in(b_out),
.HSync(hs),
.VSync(vs),
.rotate(rotate),
.R_out(red),
.G_out(green),