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Some Work on Sg1000
This commit is contained in:
Gehstock
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@@ -43,7 +43,7 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:14:01 APRIL 10, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION 13.1
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set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
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1
Console_MiST/Sega - SG1000/ReadMe.txt
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1
Console_MiST/Sega - SG1000/ReadMe.txt
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@@ -0,0 +1 @@
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WIP not Working
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BIN
Console_MiST/Sega - SG1000/Schematic/card.png
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BIN
Console_MiST/Sega - SG1000/Schematic/card.png
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@@ -1,3 +0,0 @@
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set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
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set_global_assignment -name IP_TOOL_VERSION "13.0"
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "RAM2K.v"]
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@@ -1,177 +0,0 @@
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// megafunction wizard: %RAM: 1-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: altsyncram
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// ============================================================
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// File Name: RAM2K.v
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// Megafunction Name(s):
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// altsyncram
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors. Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module RAM2K (
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address,
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clken,
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clock,
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data,
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wren,
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q);
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input [10:0] address;
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input clken;
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input clock;
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input [7:0] data;
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input wren;
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output [7:0] q;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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tri1 clken;
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tri1 clock;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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wire [7:0] sub_wire0;
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wire [7:0] q = sub_wire0[7:0];
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altsyncram altsyncram_component (
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.address_a (address),
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.clock0 (clock),
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.data_a (data),
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.wren_a (wren),
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.clocken0 (clken),
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.q_a (sub_wire0),
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.aclr0 (1'b0),
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.aclr1 (1'b0),
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.address_b (1'b1),
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.addressstall_a (1'b0),
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.addressstall_b (1'b0),
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.byteena_a (1'b1),
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.byteena_b (1'b1),
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.clock1 (1'b1),
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.clocken1 (1'b1),
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.clocken2 (1'b1),
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.clocken3 (1'b1),
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.data_b (1'b1),
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.eccstatus (),
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.q_b (),
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.rden_a (1'b1),
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.rden_b (1'b1),
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.wren_b (1'b0));
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defparam
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altsyncram_component.clock_enable_input_a = "NORMAL",
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altsyncram_component.clock_enable_output_a = "NORMAL",
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altsyncram_component.intended_device_family = "Cyclone III",
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altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
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altsyncram_component.lpm_type = "altsyncram",
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altsyncram_component.numwords_a = 2048,
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altsyncram_component.operation_mode = "SINGLE_PORT",
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altsyncram_component.outdata_aclr_a = "NONE",
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altsyncram_component.outdata_reg_a = "CLOCK0",
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altsyncram_component.power_up_uninitialized = "FALSE",
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altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
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altsyncram_component.widthad_a = 11,
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altsyncram_component.width_a = 8,
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altsyncram_component.width_byteena_a = 1;
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
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// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
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// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
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// Retrieval info: PRIVATE: AclrData NUMERIC "0"
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// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
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// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
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// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
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// Retrieval info: PRIVATE: Clken NUMERIC "1"
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// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
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// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
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// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
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// Retrieval info: PRIVATE: RegData NUMERIC "1"
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// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
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// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
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// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
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// Retrieval info: PRIVATE: WidthData NUMERIC "8"
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// Retrieval info: PRIVATE: rden NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
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// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
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// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
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// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
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// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
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// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
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// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
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// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
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// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
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// Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
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// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
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// Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
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// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
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// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
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// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL RAM2K_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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@@ -23,6 +23,7 @@ localparam CONF_STR =
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{
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"SG1000;BINSG ;",
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"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
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"O4,Video,NTSC,PAL;",
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"O5,Pause,Off,On;",
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"T6,Reset;",
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"V,v1.0.",`BUILD_DATE
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@@ -70,8 +71,8 @@ user_io (
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.switches(switches),
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.ps2_kbd_clk(ps2_kbd_clk),
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.ps2_kbd_data(ps2_kbd_data),
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.joystick_0(joystick_0[5:0]),
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.joystick_1(joystick_1[5:0]),
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.joystick_0(joystick_0),
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.joystick_1(joystick_1),
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.ioctl_ce(1'b1),
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.ioctl_wr(ioctl_wr),
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.ioctl_index(ioctl_index),
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@@ -113,13 +114,16 @@ video_mixer (
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sg1000_top sg1000_top (
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.RESET_n(~(status[0] | status[6] | buttons[1])),
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.sys_clk(clk_8),
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.clk_vdp(clk_16),
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.vdp_clk(clk_16),
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.vid_clk(clk_64),
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.pal(status[4]),
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.pause(status[5]),
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.ps2_kbd_clk(ps2_kbd_clk),
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.ps2_kbd_data(ps2_kbd_data),
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//.Cart_In(Cart_In),
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//.Cart_Out(Cart_Out),
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//.Cart_Addr(Cart_Addr),
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// .Cart_In(Cart_In),
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// .Cart_Out(Cart_Out),
|
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// .Cart_Addr(Cart_Addr),
|
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// .Cart_We(Cart_We),
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.audio(audio),
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.vblank(vb),
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.hblank(hb),
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@@ -128,25 +132,14 @@ sg1000_top sg1000_top (
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.vga_r(r),
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.vga_g(g),
|
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.vga_b(b),
|
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.Joy_A(),
|
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.Joy_B()
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// .rgb_r(r),
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// .rgb_g(g),
|
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// .rgb_b(b),
|
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// .csync(vs),
|
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.Joy_A(joystick_0[5:0]),
|
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.Joy_B(joystick_1[5:0])
|
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);
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wire [7:0] Cart_Out;
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wire [7:0] Cart_In;
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wire [14:0] Cart_Addr;
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spram #(
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.init_file("roms/32.hex"),//Test
|
||||
.widthad_a(15),
|
||||
.width_a(8))
|
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CART (
|
||||
.address(ioctl_download ? ioctl_addr[14:0] : Cart_Addr),
|
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.clock(clk_64),
|
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.data(ioctl_dout),
|
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.wren(ioctl_wr),
|
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.q(Cart_Out)
|
||||
);
|
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//assign hs= 1'b1;
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|
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dac #(
|
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.msbi_g(5))
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|
||||
@@ -1,2 +1,2 @@
|
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`define BUILD_DATE "181108"
|
||||
`define BUILD_TIME "102032"
|
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`define BUILD_DATE "181109"
|
||||
`define BUILD_TIME "113105"
|
||||
|
||||
@@ -9,24 +9,50 @@ input clk_cpu,
|
||||
output CON,
|
||||
input EXM2_n,
|
||||
input M1_n,
|
||||
input [14:0] Addr,
|
||||
output [7:0] Cart_Out,
|
||||
input [14:0] Cart_Addr,
|
||||
input [7:0] Cart_In,
|
||||
input [7:0] Cart_Ram_In,
|
||||
output [7:0] Cart_Ram_Out,
|
||||
input [7:0] Cart_In
|
||||
output [7:0] Cart_Rom_Out,
|
||||
input Cart_We
|
||||
);
|
||||
|
||||
/*
|
||||
wire [5:0]bank0;
|
||||
wire [5:0]bank1;
|
||||
wire [5:0]bank2;
|
||||
|
||||
always @(clk_cpu) begin
|
||||
if (~WR_n & Addr[14:2] == "1111111111111")
|
||||
case (Addr[1:0])
|
||||
always @(clk_cpu, WR_n) begin
|
||||
if (~WR_n & Cart_Addr[14:2] == "1111111111111")
|
||||
case (Cart_Addr[1:0])
|
||||
2'b01 : bank0 = Cart_In[5:0];
|
||||
2'b10 : bank1 = Cart_In[5:0];
|
||||
2'b11 : bank2 = Cart_In[5:0];
|
||||
default : ;
|
||||
endcase;
|
||||
end
|
||||
end*/
|
||||
|
||||
spram #(
|
||||
.init_file("/roms/[BIOS]OthelloMultivision.hex"),
|
||||
.widthad_a(14),//16k for test
|
||||
.width_a(8))
|
||||
ROM (
|
||||
.address(Cart_Addr),
|
||||
.clock(clk_cpu),
|
||||
.data(Cart_In),
|
||||
.wren(~WR_n),
|
||||
.q(Cart_Rom_Out)
|
||||
);
|
||||
/*
|
||||
spram #(
|
||||
.init_file(""),
|
||||
.widthad_a(11),//2k for test
|
||||
.width_a(8))
|
||||
RAM (
|
||||
.address(Cart_Addr),
|
||||
.clock(clk_cpu),
|
||||
.data(Cart_Ram_In),
|
||||
.wren(~WR_n),
|
||||
.q(Cart_Ram_Out)
|
||||
);*/
|
||||
|
||||
endmodule
|
||||
136
Console_MiST/Sega - SG1000/rtl/color_encoder.vhd
Normal file
136
Console_MiST/Sega - SG1000/rtl/color_encoder.vhd
Normal file
@@ -0,0 +1,136 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- clk must be a 64Mhz clock
|
||||
-- sync is the sync signal (0 for 0V, 1 for 0.3V)
|
||||
-- line_visible is 1 for lines that are displayed (only sync when 0)
|
||||
-- line_even should be toggled every line
|
||||
-- color: 222 RGB (b1b0g1g0r1r0)
|
||||
-- output: 6 bit linear output, "000000" is 0v, "111111" is 1.3V (step is 0.02V)
|
||||
entity color_encoder is
|
||||
Port (
|
||||
clk: in STD_LOGIC;
|
||||
pal: in STD_LOGIC;
|
||||
sync: in STD_LOGIC;
|
||||
line_visible: in STD_LOGIC;
|
||||
line_even: in STD_LOGIC;
|
||||
color: in STD_LOGIC_VECTOR (5 downto 0);
|
||||
outputs: out STD_LOGIC_VECTOR (5 downto 0));
|
||||
end color_encoder;
|
||||
|
||||
architecture Behavioral of color_encoder is
|
||||
|
||||
component yuv_table
|
||||
port (color : in std_logic_vector(5 downto 0);
|
||||
y : out std_logic_vector(5 downto 0);
|
||||
u : out std_logic_vector(5 downto 0);
|
||||
v : out std_logic_vector(5 downto 0));
|
||||
end component;
|
||||
|
||||
signal counter : integer range 0 to 4096;
|
||||
signal phase : unsigned (20 downto 0) := (others=>'0');
|
||||
|
||||
signal y1: std_logic_vector (5 downto 0);
|
||||
signal u1: std_logic_vector (5 downto 0);
|
||||
signal v1: std_logic_vector (5 downto 0);
|
||||
signal y : unsigned (5 downto 0);
|
||||
signal u : unsigned (5 downto 0);
|
||||
signal v : unsigned (5 downto 0);
|
||||
|
||||
signal uv : unsigned (5 downto 0);
|
||||
|
||||
begin
|
||||
yuv_table_inst : yuv_table
|
||||
port map (
|
||||
color => color,
|
||||
y => y1,
|
||||
u => u1,
|
||||
v => v1);
|
||||
|
||||
process (clk, sync, line_visible)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
if sync='0' then
|
||||
counter <= 0;
|
||||
--phase <= (others=>'0');
|
||||
else
|
||||
if line_visible='1' then
|
||||
counter <= counter+1;
|
||||
end if;
|
||||
end if;
|
||||
if pal='1' then
|
||||
phase <= phase+145281;
|
||||
else
|
||||
phase <= phase+117295;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk,counter,color)
|
||||
--variable yuv : unsigned(17 downto 0);
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
-- color burst
|
||||
if counter>=2*29 and counter<2*(29+72) then
|
||||
-- black
|
||||
y <= "000000";
|
||||
-- reference phase
|
||||
if pal='1' then
|
||||
u <= "111100";
|
||||
v <= "000100";
|
||||
else
|
||||
u <= "111000";
|
||||
v <= "000000";
|
||||
end if;
|
||||
|
||||
-- visible pixels
|
||||
elsif counter>=2*(29+72+85) and counter<2*(29+72+85+1664) then
|
||||
--yuv := yuv_table(to_integer(unsigned(color)));
|
||||
y <= unsigned(y1);
|
||||
u <= unsigned(u1);
|
||||
v <= unsigned(v1);
|
||||
|
||||
-- front porch, sync and back porch
|
||||
else
|
||||
y <= (others=>'0');
|
||||
u <= (others=>'0');
|
||||
v <= (others=>'0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (phase, line_even, u, v)
|
||||
begin
|
||||
if pal='1' then
|
||||
case line_even&phase(20 downto 19) is
|
||||
when "000" => uv <= u;
|
||||
when "001" => uv <= v;
|
||||
when "010" => uv <= 0-u;
|
||||
when "011" => uv <= 0-v;
|
||||
when "100" => uv <= u;
|
||||
when "101" => uv <= 0-v;
|
||||
when "110" => uv <= 0-u;
|
||||
when "111" => uv <= v;
|
||||
when others => uv <= (others=>'0');
|
||||
end case;
|
||||
else
|
||||
case phase(20 downto 19) is
|
||||
when "00" => uv <= u;
|
||||
when "01" => uv <= 0-v;
|
||||
when "10" => uv <= 0-u;
|
||||
when "11" => uv <= v;
|
||||
when others => uv <= (others=>'0');
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (clk,sync,y,uv)
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
outputs <= std_logic_vector(("0"&sync&"0000")+y+uv);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
CLOCK_ENABLE_INPUT_A=NORMAL
|
||||
CLOCK_ENABLE_OUTPUT_A=NORMAL
|
||||
INTENDED_DEVICE_FAMILY="Cyclone III"
|
||||
NUMWORDS_A=2048
|
||||
OPERATION_MODE=SINGLE_PORT
|
||||
OUTDATA_ACLR_A=NONE
|
||||
OUTDATA_REG_A=CLOCK0
|
||||
POWER_UP_UNINITIALIZED=FALSE
|
||||
READ_DURING_WRITE_MODE_PORT_A=NEW_DATA_NO_NBE_READ
|
||||
WIDTHAD_A=11
|
||||
WIDTH_A=8
|
||||
WIDTH_BYTEENA_A=1
|
||||
DEVICE_FAMILY="Cyclone III"
|
||||
address_a
|
||||
clock0
|
||||
clocken0
|
||||
q_a
|
||||
@@ -5,6 +5,7 @@ use IEEE.NUMERIC_STD.ALL;
|
||||
entity psg is
|
||||
port (clk : in STD_LOGIC;
|
||||
WR_n : in STD_LOGIC;
|
||||
CS_n : in STD_LOGIC;
|
||||
D_in : in STD_LOGIC_VECTOR (7 downto 0);
|
||||
outputs: out STD_LOGIC_VECTOR (5 downto 0)
|
||||
);
|
||||
@@ -91,9 +92,9 @@ begin
|
||||
end process;
|
||||
clk32 <= std_logic(clk_divide(5));
|
||||
|
||||
process (clk, WR_n)
|
||||
process (clk, WR_n, CS_n)
|
||||
begin
|
||||
if rising_edge(clk) and WR_n='0' then
|
||||
if rising_edge(clk) and WR_n='0' and CS_n='0' then
|
||||
if D_in(7)='1' then
|
||||
case D_in(6 downto 4) is
|
||||
when "000" => tone0(3 downto 0) <= D_in(3 downto 0);
|
||||
|
||||
BIN
Console_MiST/Sega - SG1000/rtl/roms/[BIOS]OthelloMultivision.bin
Normal file
BIN
Console_MiST/Sega - SG1000/rtl/roms/[BIOS]OthelloMultivision.bin
Normal file
Binary file not shown.
1025
Console_MiST/Sega - SG1000/rtl/roms/[BIOS]OthelloMultivision.hex
Normal file
1025
Console_MiST/Sega - SG1000/rtl/roms/[BIOS]OthelloMultivision.hex
Normal file
File diff suppressed because it is too large
Load Diff
@@ -1,13 +1,15 @@
|
||||
module sg1000_top(
|
||||
input RESET_n,
|
||||
input sys_clk,//8
|
||||
input clk_vdp,//16
|
||||
input vdp_clk,//16
|
||||
input vid_clk,//64
|
||||
input pal,
|
||||
input pause,
|
||||
input ps2_kbd_clk,
|
||||
input ps2_kbd_data,
|
||||
//input [7:0] Cart_Out,
|
||||
//output [7:0] Cart_In,
|
||||
//output [14:0] Cart_Addr,
|
||||
input [7:0] Cart_In,
|
||||
output [14:0] Cart_Addr,
|
||||
output Cart_We,
|
||||
output [5:0] audio,
|
||||
output vblank,
|
||||
output hblank,
|
||||
@@ -16,6 +18,10 @@ output vga_vs,
|
||||
output [1:0] vga_r,
|
||||
output [1:0] vga_g,
|
||||
output [1:0] vga_b,
|
||||
output [1:0] rgb_r,
|
||||
output [1:0] rgb_g,
|
||||
output [1:0] rgb_b,
|
||||
output csync,
|
||||
input [5:0] Joy_A,
|
||||
input [5:0] Joy_B
|
||||
);
|
||||
@@ -61,7 +67,7 @@ CPU (
|
||||
);
|
||||
|
||||
wire [7:0]RAM_D_out;
|
||||
/*
|
||||
|
||||
spram #(
|
||||
.widthad_a(11),//2k
|
||||
.width_a(8))
|
||||
@@ -71,20 +77,12 @@ MRAM (
|
||||
.data(D_out),
|
||||
.wren(~WR_n),
|
||||
.q(RAM_D_out)
|
||||
);*/
|
||||
|
||||
RAM2K RAM2K(
|
||||
.address(Addr[10:0]),
|
||||
.clock(sys_clk),
|
||||
.clken(~CS_WRAM_n),
|
||||
.data(D_out),
|
||||
.wren(~WR_n),
|
||||
.q(RAM_D_out)
|
||||
);
|
||||
|
||||
wire CS_PSG_n = (~IORQ_n) & (Addr[7:6] == "01") ? 1'b0 : 1'b1;
|
||||
psg PSG (
|
||||
.clk(sys_clk),
|
||||
.CS_n(CS_PSG_n),
|
||||
.WR_n(WR_n),
|
||||
.D_in(D_out),
|
||||
.outputs(audio)
|
||||
@@ -94,12 +92,12 @@ wire [7:0]vdp_D_out;
|
||||
wire [8:0]x;
|
||||
wire [7:0]y;
|
||||
wire [5:0] color;
|
||||
wire VDP_RD_n = (~IORQ_n & Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1;
|
||||
wire VDP_WR_n = (~IORQ_n & Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1;
|
||||
wire VDP_RD_n = (~IORQ_n) & (Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1;
|
||||
wire VDP_WR_n = (~IORQ_n) & (Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1;
|
||||
|
||||
vdp vdp (
|
||||
.cpu_clk(sys_clk),
|
||||
.vdp_clk(clk_vdp),
|
||||
.vdp_clk(vdp_clk),
|
||||
.RD_n(VDP_RD_n),
|
||||
.WR_n(VDP_WR_n),
|
||||
.IRQ_n(IORQ_n),
|
||||
@@ -112,9 +110,9 @@ vdp vdp (
|
||||
.hblank(hblank),
|
||||
.color(color)
|
||||
);
|
||||
|
||||
|
||||
vga_video vga_video (
|
||||
.clk16(clk_vdp),
|
||||
.clk16(vdp_clk),
|
||||
.x(x),
|
||||
.y(y),
|
||||
.vblank(vblank),
|
||||
@@ -126,9 +124,23 @@ vga_video vga_video (
|
||||
.green(vga_g),
|
||||
.blue(vga_b)
|
||||
);
|
||||
/*
|
||||
tv_video tv_video (
|
||||
.clk8(sys_clk),
|
||||
.clk64(vid_clk),
|
||||
.pal(pal),
|
||||
.x(x),
|
||||
.y(y),
|
||||
.vblank(vblank),
|
||||
.hblank(hblank),
|
||||
.csync(csync),
|
||||
.color(color),
|
||||
.video({rgb_b,rgb_g,rgb_r})
|
||||
);*/
|
||||
|
||||
|
||||
wire [7:0]Joy_Out;
|
||||
wire JOY_SEL_n = (~IORQ_n & Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1;
|
||||
wire JOY_SEL_n = (~IORQ_n) & (Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1;
|
||||
wire CON;
|
||||
TTL74_257 IC18(
|
||||
.GN(JOY_SEL_n),
|
||||
@@ -164,7 +176,7 @@ TTL74_257 IC21(
|
||||
.Y1(Joy_Out[4])
|
||||
);
|
||||
|
||||
wire KB_SEL_n = (~IORQ_n & Addr[7:6] == "11") ? 1'b0 : 1'b1;
|
||||
wire KB_SEL_n = (~IORQ_n) & (Addr[7:6] == "11") ? 1'b0 : 1'b1;
|
||||
wire [7:0]Kb_Out;
|
||||
|
||||
keyboard keyboard(
|
||||
@@ -180,9 +192,9 @@ keyboard keyboard(
|
||||
.ps2_kbd_data(ps2_kbd_data)
|
||||
);
|
||||
|
||||
wire EXM1_n = (~MREQ_n & Addr[15:14] == "10") ? 1'b0 : 1'b1;
|
||||
wire EXM2_n = (~MREQ_n | Addr[15]) ? 1'b0 : 1'b1;
|
||||
wire [7:0]Cart_Out;
|
||||
wire EXM1_n = (~MREQ_n) & (Addr[15:14] == "10") ? 1'b0 : 1'b1;
|
||||
wire EXM2_n = (~MREQ_n) | (Addr[15]) ? 1'b0 : 1'b1;
|
||||
wire [7:0]Cart_Rom_Out, Cart_Ram_Out;
|
||||
|
||||
cart cart(
|
||||
.DSRAM_n(DSRAM_n),
|
||||
@@ -194,17 +206,18 @@ cart cart(
|
||||
.CON(CON),
|
||||
.EXM2_n(EXM2_n),
|
||||
.M1_n,
|
||||
.Addr(Addr[14:0]),
|
||||
.Cart_Out(Cart_Out),
|
||||
.Cart_Addr(Addr[14:0]),
|
||||
.Cart_Rom_Out(Cart_Rom_Out),
|
||||
.Cart_Ram_Out(Cart_Ram_Out),
|
||||
.Cart_In(D_out)
|
||||
.Cart_In(Cart_In),
|
||||
.Cart_We(Cart_We)
|
||||
);
|
||||
|
||||
//todo
|
||||
always @(sys_clk) begin
|
||||
|
||||
D_in <= ~CS_WRAM_n ? RAM_D_out :
|
||||
D_in = ~CS_WRAM_n ? RAM_D_out :
|
||||
~VDP_RD_n ? vdp_D_out :
|
||||
~EXM1_n ? Cart_Out :
|
||||
~EXM1_n ? Cart_Rom_Out :
|
||||
~EXM2_n ? Cart_Ram_Out :
|
||||
~JOY_SEL_n ? Joy_Out :
|
||||
~KB_SEL_n ? Kb_Out :
|
||||
|
||||
121
Console_MiST/Sega - SG1000/rtl/tv_video.vhd
Normal file
121
Console_MiST/Sega - SG1000/rtl/tv_video.vhd
Normal file
@@ -0,0 +1,121 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
entity tv_video is
|
||||
Port (
|
||||
clk8: in STD_LOGIC;
|
||||
clk64: in STD_LOGIC;
|
||||
pal: in STD_LOGIC;
|
||||
x: out unsigned(8 downto 0);
|
||||
y: out unsigned(7 downto 0);
|
||||
vblank: out STD_LOGIC;
|
||||
hblank: out STD_LOGIC;
|
||||
color: in STD_LOGIC_VECTOR(5 downto 0);
|
||||
csync: out STD_LOGIC;
|
||||
video: out STD_LOGIC_VECTOR(6 downto 1));
|
||||
end tv_video;
|
||||
|
||||
architecture Behavioral of tv_video is
|
||||
|
||||
component color_encoder is
|
||||
Port (
|
||||
clk: in STD_LOGIC;
|
||||
pal: in STD_LOGIC;
|
||||
sync: in STD_LOGIC;
|
||||
line_visible: in STD_LOGIC;
|
||||
line_even: in STD_LOGIC;
|
||||
color: in STD_LOGIC_VECTOR (5 downto 0);
|
||||
outputs: out STD_LOGIC_VECTOR (5 downto 0));
|
||||
end component;
|
||||
|
||||
signal hcount: unsigned(8 downto 0) := (others => '0');
|
||||
signal vcount: unsigned(8 downto 0) := (others => '0');
|
||||
signal y9: unsigned(8 downto 0);
|
||||
|
||||
signal in_vbl: std_logic;
|
||||
signal screen_sync: std_logic;
|
||||
signal vbl_sync: std_logic;
|
||||
|
||||
signal sync: std_logic;
|
||||
signal line_visible: std_logic;
|
||||
signal line_even: std_logic;
|
||||
|
||||
begin
|
||||
csync <= sync;
|
||||
|
||||
process (clk8)
|
||||
begin
|
||||
if rising_edge(clk8) then
|
||||
if hcount=507 then
|
||||
hcount <= (others => '0');
|
||||
if vcount=261 then
|
||||
vcount <= (others=>'0');
|
||||
else
|
||||
vcount <= vcount + 1;
|
||||
end if;
|
||||
else
|
||||
hcount <= hcount + 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (hcount)
|
||||
begin
|
||||
if hcount<38 then
|
||||
screen_sync <= '0';
|
||||
else
|
||||
screen_sync <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
in_vbl <= '1' when vcount<9 else '0';
|
||||
|
||||
x <= hcount-166;
|
||||
y9 <= vcount-40;
|
||||
y <= y9(7 downto 0);
|
||||
vblank <= '1' when hcount=0 and vcount=0 else '0';
|
||||
hblank <= '1' when hcount=0 else '0';
|
||||
line_visible <= not in_vbl;
|
||||
line_even <= not vcount(0);
|
||||
|
||||
process (vcount,hcount)
|
||||
begin
|
||||
if vcount<3 or (vcount>=6 and vcount<9) then
|
||||
-- _^^^^^_^^^^^ : low pulse = 2.35us
|
||||
if hcount<19 or (hcount>=254 and hcount<254+19) then
|
||||
vbl_sync <= '0';
|
||||
else
|
||||
vbl_sync <= '1';
|
||||
end if;
|
||||
else
|
||||
-- ____^^ : high pulse = 4.7us
|
||||
if hcount<(254-38) or (hcount>=254 and hcount<508-38) then
|
||||
vbl_sync <= '0';
|
||||
else
|
||||
vbl_sync <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (in_vbl,screen_sync,vbl_sync)
|
||||
begin
|
||||
if in_vbl='1' then
|
||||
sync <= vbl_sync;
|
||||
else
|
||||
sync <= screen_sync;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
encode_inst: color_encoder
|
||||
port map (
|
||||
clk => clk64,
|
||||
pal => pal,
|
||||
sync => sync,
|
||||
line_visible => line_visible,
|
||||
line_even => line_even,
|
||||
color => color,
|
||||
outputs => video);
|
||||
|
||||
end Behavioral;
|
||||
|
||||
229
Console_MiST/Sega - SG1000/rtl/yuv_table.vhd
Normal file
229
Console_MiST/Sega - SG1000/rtl/yuv_table.vhd
Normal file
@@ -0,0 +1,229 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity yuv_table is
|
||||
Port (color : in std_logic_vector (5 downto 0);
|
||||
y : out std_logic_vector (5 downto 0);
|
||||
u : out std_logic_vector (5 downto 0);
|
||||
v : out std_logic_vector (5 downto 0));
|
||||
end yuv_table;
|
||||
|
||||
architecture Behavioral of yuv_table is
|
||||
begin
|
||||
|
||||
process (color)
|
||||
begin
|
||||
case color is
|
||||
when "000000" => y <= "000000";
|
||||
when "000001" => y <= "000011";
|
||||
when "000010" => y <= "000110";
|
||||
when "000011" => y <= "001001";
|
||||
when "000100" => y <= "000110";
|
||||
when "000101" => y <= "001001";
|
||||
when "000110" => y <= "001100";
|
||||
when "000111" => y <= "001111";
|
||||
when "001000" => y <= "001100";
|
||||
when "001001" => y <= "001111";
|
||||
when "001010" => y <= "010010";
|
||||
when "001011" => y <= "010101";
|
||||
when "001100" => y <= "010010";
|
||||
when "001101" => y <= "010101";
|
||||
when "001110" => y <= "011000";
|
||||
when "001111" => y <= "011011";
|
||||
when "010000" => y <= "000001";
|
||||
when "010001" => y <= "000100";
|
||||
when "010010" => y <= "000111";
|
||||
when "010011" => y <= "001010";
|
||||
when "010100" => y <= "000111";
|
||||
when "010101" => y <= "001010";
|
||||
when "010110" => y <= "001101";
|
||||
when "010111" => y <= "010000";
|
||||
when "011000" => y <= "001101";
|
||||
when "011001" => y <= "010000";
|
||||
when "011010" => y <= "010011";
|
||||
when "011011" => y <= "010110";
|
||||
when "011100" => y <= "010011";
|
||||
when "011101" => y <= "010110";
|
||||
when "011110" => y <= "011001";
|
||||
when "011111" => y <= "011100";
|
||||
when "100000" => y <= "000010";
|
||||
when "100001" => y <= "000101";
|
||||
when "100010" => y <= "001000";
|
||||
when "100011" => y <= "001011";
|
||||
when "100100" => y <= "001000";
|
||||
when "100101" => y <= "001011";
|
||||
when "100110" => y <= "001110";
|
||||
when "100111" => y <= "010001";
|
||||
when "101000" => y <= "001110";
|
||||
when "101001" => y <= "010001";
|
||||
when "101010" => y <= "010100";
|
||||
when "101011" => y <= "010111";
|
||||
when "101100" => y <= "010100";
|
||||
when "101101" => y <= "010111";
|
||||
when "101110" => y <= "011010";
|
||||
when "101111" => y <= "011101";
|
||||
when "110000" => y <= "000011";
|
||||
when "110001" => y <= "000110";
|
||||
when "110010" => y <= "001001";
|
||||
when "110011" => y <= "001100";
|
||||
when "110100" => y <= "001001";
|
||||
when "110101" => y <= "001100";
|
||||
when "110110" => y <= "001111";
|
||||
when "110111" => y <= "010010";
|
||||
when "111000" => y <= "001111";
|
||||
when "111001" => y <= "010010";
|
||||
when "111010" => y <= "010101";
|
||||
when "111011" => y <= "011000";
|
||||
when "111100" => y <= "010101";
|
||||
when "111101" => y <= "011000";
|
||||
when "111110" => y <= "011011";
|
||||
when "111111" => y <= "011110";
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process (color)
|
||||
begin
|
||||
case color is
|
||||
when "000000" => u <= "000000";
|
||||
when "000001" => u <= "111111";
|
||||
when "000010" => u <= "111101";
|
||||
when "000011" => u <= "111100";
|
||||
when "000100" => u <= "111101";
|
||||
when "000101" => u <= "111100";
|
||||
when "000110" => u <= "111010";
|
||||
when "000111" => u <= "111001";
|
||||
when "001000" => u <= "111010";
|
||||
when "001001" => u <= "111001";
|
||||
when "001010" => u <= "110111";
|
||||
when "001011" => u <= "110110";
|
||||
when "001100" => u <= "110111";
|
||||
when "001101" => u <= "110110";
|
||||
when "001110" => u <= "110100";
|
||||
when "001111" => u <= "110011";
|
||||
when "010000" => u <= "000100";
|
||||
when "010001" => u <= "000011";
|
||||
when "010010" => u <= "000001";
|
||||
when "010011" => u <= "000000";
|
||||
when "010100" => u <= "000001";
|
||||
when "010101" => u <= "000000";
|
||||
when "010110" => u <= "111111";
|
||||
when "010111" => u <= "111101";
|
||||
when "011000" => u <= "111111";
|
||||
when "011001" => u <= "111101";
|
||||
when "011010" => u <= "111100";
|
||||
when "011011" => u <= "111010";
|
||||
when "011100" => u <= "111100";
|
||||
when "011101" => u <= "111010";
|
||||
when "011110" => u <= "111001";
|
||||
when "011111" => u <= "110111";
|
||||
when "100000" => u <= "001001";
|
||||
when "100001" => u <= "000111";
|
||||
when "100010" => u <= "000110";
|
||||
when "100011" => u <= "000100";
|
||||
when "100100" => u <= "000110";
|
||||
when "100101" => u <= "000100";
|
||||
when "100110" => u <= "000011";
|
||||
when "100111" => u <= "000001";
|
||||
when "101000" => u <= "000011";
|
||||
when "101001" => u <= "000001";
|
||||
when "101010" => u <= "000000";
|
||||
when "101011" => u <= "111111";
|
||||
when "101100" => u <= "000000";
|
||||
when "101101" => u <= "111111";
|
||||
when "101110" => u <= "111101";
|
||||
when "101111" => u <= "111100";
|
||||
when "110000" => u <= "001101";
|
||||
when "110001" => u <= "001100";
|
||||
when "110010" => u <= "001010";
|
||||
when "110011" => u <= "001001";
|
||||
when "110100" => u <= "001010";
|
||||
when "110101" => u <= "001001";
|
||||
when "110110" => u <= "000111";
|
||||
when "110111" => u <= "000110";
|
||||
when "111000" => u <= "000111";
|
||||
when "111001" => u <= "000110";
|
||||
when "111010" => u <= "000100";
|
||||
when "111011" => u <= "000011";
|
||||
when "111100" => u <= "000100";
|
||||
when "111101" => u <= "000011";
|
||||
when "111110" => u <= "000001";
|
||||
when "111111" => u <= "000000";
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process (color)
|
||||
begin
|
||||
case color is
|
||||
when "000000" => v <= "000000";
|
||||
when "000001" => v <= "000110";
|
||||
when "000010" => v <= "001100";
|
||||
when "000011" => v <= "010010";
|
||||
when "000100" => v <= "111011";
|
||||
when "000101" => v <= "000001";
|
||||
when "000110" => v <= "000111";
|
||||
when "000111" => v <= "001101";
|
||||
when "001000" => v <= "110110";
|
||||
when "001001" => v <= "111100";
|
||||
when "001010" => v <= "000010";
|
||||
when "001011" => v <= "001000";
|
||||
when "001100" => v <= "110001";
|
||||
when "001101" => v <= "110111";
|
||||
when "001110" => v <= "111101";
|
||||
when "001111" => v <= "000011";
|
||||
when "010000" => v <= "111111";
|
||||
when "010001" => v <= "000101";
|
||||
when "010010" => v <= "001011";
|
||||
when "010011" => v <= "010001";
|
||||
when "010100" => v <= "111010";
|
||||
when "010101" => v <= "000000";
|
||||
when "010110" => v <= "000110";
|
||||
when "010111" => v <= "001100";
|
||||
when "011000" => v <= "110101";
|
||||
when "011001" => v <= "111011";
|
||||
when "011010" => v <= "000001";
|
||||
when "011011" => v <= "000111";
|
||||
when "011100" => v <= "110000";
|
||||
when "011101" => v <= "110110";
|
||||
when "011110" => v <= "111100";
|
||||
when "011111" => v <= "000010";
|
||||
when "100000" => v <= "111110";
|
||||
when "100001" => v <= "000100";
|
||||
when "100010" => v <= "001010";
|
||||
when "100011" => v <= "010000";
|
||||
when "100100" => v <= "111001";
|
||||
when "100101" => v <= "111111";
|
||||
when "100110" => v <= "000101";
|
||||
when "100111" => v <= "001011";
|
||||
when "101000" => v <= "110100";
|
||||
when "101001" => v <= "111010";
|
||||
when "101010" => v <= "000000";
|
||||
when "101011" => v <= "000110";
|
||||
when "101100" => v <= "101111";
|
||||
when "101101" => v <= "110101";
|
||||
when "101110" => v <= "111011";
|
||||
when "101111" => v <= "000001";
|
||||
when "110000" => v <= "111101";
|
||||
when "110001" => v <= "000011";
|
||||
when "110010" => v <= "001001";
|
||||
when "110011" => v <= "001111";
|
||||
when "110100" => v <= "111000";
|
||||
when "110101" => v <= "111110";
|
||||
when "110110" => v <= "000100";
|
||||
when "110111" => v <= "001010";
|
||||
when "111000" => v <= "110011";
|
||||
when "111001" => v <= "111001";
|
||||
when "111010" => v <= "111111";
|
||||
when "111011" => v <= "000101";
|
||||
when "111100" => v <= "101110";
|
||||
when "111101" => v <= "110100";
|
||||
when "111110" => v <= "111010";
|
||||
when "111111" => v <= "000000";
|
||||
when others =>
|
||||
end case;
|
||||
end process;
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
@@ -166,8 +166,10 @@ set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/TTL74_257.v
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cart.sv
|
||||
set_global_assignment -name VHDL_FILE rtl/tv_video.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/color_encoder.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/yuv_table.vhd
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
set_global_assignment -name QIP_FILE rtl/RAM2K.qip
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -5,3 +5,4 @@
|
||||
{ "" "" "" "Net \"Cart_ram_Out\" at sg1000_top.sv(25) has no driver or initial value, using a default initial value '0'" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "VHDL Process Statement warning at vdp_main.vhd(117): signal \"mask_column0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" { } { } 0 10492 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 14284 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10235 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
|
||||
Reference in New Issue
Block a user