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Marcel 2019-07-22 02:46:16 +02:00
parent c1ddb0f66c
commit ab8496669a
18 changed files with 118 additions and 3444 deletions
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56
Computer_MiST/OricInFPGA_MiST/Oric_MiST.qsf
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@ -18,7 +18,7 @@
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 21:22:50 May 18, 2019
# Date created = 02:08:17 July 22, 2019
#
# -------------------------------------------------------------------------- #
#
@ -44,6 +44,27 @@ set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53 MARCH 09, 2017
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/OricAtmos_MiST.sv
set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
set_global_assignment -name VHDL_FILE rtl/ula.vhd
set_global_assignment -name VHDL_FILE rtl/ay8912.vhd
set_global_assignment -name VHDL_FILE rtl/m6522.vhd
set_global_assignment -name VHDL_FILE rtl/rom/BASIC.vhd
set_global_assignment -name VHDL_FILE rtl/ram48k.vhd
set_global_assignment -name VHDL_FILE rtl/video.vhd
set_global_assignment -name VHDL_FILE rtl/T65/t65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/t65_alu.vhd
set_global_assignment -name VHDL_FILE rtl/T65/t65.vhd
set_global_assignment -name VHDL_FILE rtl/T65/pack_t65.vhd
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
set_global_assignment -name VHDL_FILE rtl/dac.vhd
# Pin & Location Assignments
# ==========================
@ -190,40 +211,13 @@ set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(OricAtmos_MiST)
# --------------------------
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name SYSTEMVERILOG_FILE rtl/OricAtmos_MiST.sv
set_global_assignment -name VHDL_FILE rtl/oricatmos.vhd
set_global_assignment -name VHDL_FILE rtl/ula.vhd
set_global_assignment -name VHDL_FILE rtl/rom/BASIC.vhd
set_global_assignment -name VHDL_FILE rtl/m6522.vhd
set_global_assignment -name VHDL_FILE rtl/rom_oa.vhd
set_global_assignment -name VHDL_FILE rtl/vag.vhd
set_global_assignment -name VHDL_FILE rtl/video.vhd
set_global_assignment -name VHDL_FILE rtl/gen_clk.vhd
set_global_assignment -name VHDL_FILE rtl/ram48k.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VHDL_FILE rtl/T65/t65_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T65/t65_alu.vhd
set_global_assignment -name VHDL_FILE rtl/T65/t65.vhd
set_global_assignment -name VHDL_FILE rtl/T65/pack_t65.vhd
set_global_assignment -name VHDL_FILE rtl/gen_env.vhd
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/dac2.vhd
set_global_assignment -name VHDL_FILE "Neuer Ordner/YM2149_linmix.vhd"
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/keyboard.sv
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

BIN
Computer_MiST/OricInFPGA_MiST/Release/Oric_MiST.rbf
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Binary file not shown.

24
Computer_MiST/OricInFPGA_MiST/rtl/OricAtmos_MiST.sv
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@ -34,9 +34,7 @@ wire ypbpr;
wire scandoublerD;
wire [31:0] status;
wire [15:0] audiol, audior;
wire [7:0] PSG_OUT;
assign LED = 1'b1;
assign AUDIO_R = AUDIO_L;
pll pll (
.inclk0 ( CLOCK_27 ),
@ -92,7 +90,8 @@ video_mixer video_mixer (
oricatmos oricatmos(
.RESET(status[0] | status[9] | buttons[1]),
.ps2_key(ps2_key),
.PSG_OUT(PSG_OUT),
.PSG_LEFT(audiol),
.PSG_RIGHT(audior),
.VIDEO_R(r),
.VIDEO_G(g),
.VIDEO_B(b),
@ -102,14 +101,25 @@ oricatmos oricatmos(
.K7_TAPEOUT(UART_TXD),
.clk_in(clk_24)
);
dac2 #(
.msbi_g(8))
dac #(
.msbi_g(15))
dacl (
.clk_i(clk_24),
.res_n_i(1'b1),
.dac_i(PSG_OUT),
.dac_i(audiol),
.dac_o(AUDIO_L)
);
dac #(
.msbi_g(15))
dacr (
.clk_i(clk_24),
.res_n_i(1'b1),
.dac_i(audior),
.dac_o(AUDIO_R)
);
endmodule

435
Computer_MiST/OricInFPGA_MiST/rtl/ay3819x.vhd
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@ -1,435 +0,0 @@
--
-- A simulation model of PSG hardware
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- You are responsible for any legal issues arising from your use of this code.
--
-- The latest version of this file can be found at: passionoric.free.fr
--
-- Email seilebost@free.fr
--
--
-- Revision list
--
-- v0.42 2002/01/03 : It seems ok
-- v0.43 2009/01/21 : bus bidirectionnel => bus unidirectionnel
-- v0.44 2009/10/11 : Reset asynchrone pour le process U_TRAIT
-- v0.45 2010/01/03 : Ajout d'une horloge pour le DAC
-- v0.46 2010/01/06 : Modification du générateur de fréquence
-- pour ajouter la division par 16 et par 256
-- v0.50 2010/01/19 : Reorganisation du code
--
-- AY3819X.vhd
--
-- Top entity of AY3819X.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: AY3819.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
-- TODO :
-- Many verification !!
-- Remark :
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--use UNISIM.Vcomponents.ALL; -- for IOBUF and OBUF
entity AY3819X is
Port ( DATA_IN : in std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
O_DATA_OE_L : out std_logic;
RESET : in std_logic;
CLOCK : in std_logic;
CLOCK_DAC : in std_logic; -- 24 MHz pour le DAC
BDIR : in std_logic;
BC1 : in std_logic;
BC2 : in std_logic;
IOA : inout std_logic_vector(7 downto 0);
IOB : inout std_logic_vector(7 downto 0);
AnalogA : out std_logic;
AnalogB : out std_logic;
AnalogC : out std_logic );
end AY3819X;
architecture Behavioral of AY3819X is
SIGNAL BUS_CS : std_logic_vector(15 downto 0); -- Select the different module when Read / Write Register
-- Create register
SIGNAL R0 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel A
SIGNAL R1 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel A
SIGNAL R2 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel B
SIGNAL R3 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
SIGNAL R4 : std_logic_vector(7 downto 0); -- Tone generator frequency Fine Tune channel C
SIGNAL R5 : std_logic_vector(7 downto 0); -- Tone generator frequency Coarse Tune channel B
SIGNAL R6 : std_logic_vector(7 downto 0); -- Noise generator frequency
SIGNAL R7 : std_logic_vector(7 downto 0); -- Mixer Control I/O Enable
SIGNAL R8 : std_logic_vector(7 downto 0); -- Amplitude control channel A
SIGNAL R9 : std_logic_vector(7 downto 0); -- Amplitude control channel B
SIGNAL R10 : std_logic_vector(7 downto 0); -- Amplitude control channel C
SIGNAL R11 : std_logic_vector(7 downto 0); -- Envelope period control fine tune
SIGNAL R12 : std_logic_vector(7 downto 0); -- Envelope period control coarse tune
SIGNAL R13 : std_logic_vector(7 downto 0); -- Envelope shape/cycle control
SIGNAL REG_ADDR : std_logic_vector(3 downto 0); -- Keep the number of register addressed
SIGNAL WR : std_logic; -- WRITE (FLAG)
SIGNAL CLK_A : std_logic; -- CLOCK TONE VOICE A
SIGNAL CLK_B : std_logic; -- CLOCK TONE VOICE B
SIGNAL CLK_C : std_logic; -- CLOCK TONE VOICE C
SIGNAL CLK_TONE_A : std_logic; -- CLOCK TONE VOICE A +/- CLOCK NOISE
SIGNAL CLK_TONE_B : std_logic; -- CLOCK TONE VOICE B +/- CLOCK NOISE
SIGNAL CLK_TONE_C : std_logic; -- CLOCK TONE VOICE C +/- CLOCK NOISE
SIGNAL CLK_E : std_logic; -- CLOCK Envelope Generator
SIGNAL CLK_N : std_logic; -- CLOCK FROM NOISE GENERATOR
SIGNAL CLK_16 : std_logic; -- CLOCK (=1 MHz) / 16 pour le "tone"
SIGNAL CLK_256 : std_logic; -- CLOCK (=1 MHz) / 256 pour l'enveloppe
SIGNAL OUT_AMPL_E : std_logic_vector(3 downto 0); -- Amplitude of signal from Envelope generator
SIGNAL IAnalogA : std_logic; -- FOR IOPAD, exit from DAC VOICE A
SIGNAL IAnalogB : std_logic; -- FOR IOPAD, exit from DAC VOICE B
SIGNAL IAnalogC : std_logic; -- FOR IOPAD, exit from DAC VOICE C
SIGNAL RST_ENV : std_logic; -- FOR RESET THE VALUE OF ENVELOPPE
COMPONENT TONE_GENERATOR PORT ( CLK : in std_logic;
--CLK_TONE : in std_logic;
RST : in std_logic;
WR : in std_logic;
--CS_COARSE : in std_logic;
--CS_FINE : in std_logic;
DATA_COARSE : in std_logic_vector(7 downto 0);
DATA_FINE : in std_logic_vector(7 downto 0);
OUT_TONE : inout std_logic );
END COMPONENT;
COMPONENT NOISE_GENERATOR PORT ( CLK : in std_logic;
RST : in std_logic;
--WR : in std_logic;
--CS : in std_logic;
DATA : in std_logic_vector(4 downto 0);
CLK_N : out std_logic );
END COMPONENT;
COMPONENT GEN_CLK PORT ( CLK : in std_logic;
RST : in std_logic;
CLK_16 : out std_logic;
CLK_256 : out std_logic);
END COMPONENT;
-- COMPONENT MIXER PORT ( CLK : in std_logic;
-- CS : in std_logic;
-- RST : in std_logic;
-- WR : in std_logic;
-- IN_A : in std_logic;
-- IN_B : in std_logic;
-- IN_C : in std_logic;
-- IN_NOISE : in std_logic;
-- DATA : in std_logic_vector(5 downto 0);
-- OUT_A : out std_logic;
-- OUT_B : out std_logic;
-- OUT_C : out std_logic );
--END COMPONENT;
COMPONENT GEN_ENV PORT ( CLK_ENV : in std_logic;
DATA : in std_logic_vector(3 downto 0);
RST_ENV : in std_logic;
WR : in std_logic;
--CS : in std_logic;
OUT_DATA : inout std_logic_vector(3 downto 0));
END COMPONENT;
COMPONENT MANAGE_AMPLITUDE PORT ( CLK : in std_logic;
CLK_DAC : in std_logic;
CLK_TONE : in std_logic;
CLK_NOISE : in std_logic;
RST : in std_logic;
CLK_TONE_ENA : in std_logic;
CLK_NOISE_ENA : in std_logic;
AMPLITUDE : in std_logic_vector(4 downto 0);
AMPLITUDE_E : in std_logic_vector(3 downto 0);
OUT_DAC : out std_logic );
END COMPONENT;
--COMPONENT IOBUF_F_12 port ( O : out std_logic;
-- IO : inout std_logic;
-- I : in std_logic;
-- T : in std_logic );
--END COMPONENT;
--COMPONENT OBUF_F_12 port ( O : out std_logic;
-- IO : inout std_logic;
-- I : in std_logic;
-- T : in std_logic );
--END COMPONENT;
--component OBUF_F_24
--port (
-- I : in std_logic;
-- O : out std_logic );
--end component;
BEGIN
U_TRAIT : PROCESS(CLOCK, RESET, BC1, BC2, BDIR, REG_ADDR, DATA_IN)
BEGIN
if (RESET = '1') then
WR <= '0';
R0 <= "00000000";
R1 <= "00000000";
R2 <= "00000000";
R3 <= "00000000";
R4 <= "00000000";
R5 <= "00000000";
R6 <= "00000000";
R7 <= "00000000";
R8 <= "00000000";
R9 <= "00000000";
R10 <= "00000000";
R11 <= "00000000";
R12 <= "00000000";
R13 <= "00000000";
IOA <= "00000000";
IOB <= "00000000";
DATA_OUT <= "00000000";
RST_ENV <= '1';
else
if rising_edge(CLOCK) then -- edge clock
-- READ FROM REGISTER
RST_ENV <= '0';
if ((BDIR = '0') and (BC2 = '1') and (BC1 = '1')) then
CASE REG_ADDR is
WHEN "0000" => DATA_OUT <= R0;
WHEN "0001" => DATA_OUT <= R1;
WHEN "0010" => DATA_OUT <= R2;
WHEN "0011" => DATA_OUT <= R3;
WHEN "0100" => DATA_OUT <= R4;
WHEN "0101" => DATA_OUT <= R5;
WHEN "0110" => DATA_OUT <= R6;
WHEN "0111" => DATA_OUT <= R7;
WHEN "1000" => DATA_OUT <= R8;
WHEN "1001" => DATA_OUT <= R9;
WHEN "1010" => DATA_OUT <= R10;
WHEN "1011" => DATA_OUT <= R11;
WHEN "1100" => DATA_OUT <= R12;
WHEN "1101" => DATA_OUT <= R13;
WHEN "1110" => DATA_OUT <= IOA;
WHEN "1111" => DATA_OUT <= IOB;
WHEN OTHERS => NULL;
END CASE;
WR <= '0';
else
DATA_OUT <= "00000000";
WR <= '0';
end if;
end if;
end if;
-- LATCH WHAT REGISTER
if ((BDIR = '1') and (BC2 = '1') and (BC1 = '1')) then
REG_ADDR <= DATA_IN(3 downto 0);
WR <= '0';
end if;
-- WRITE TO REGISTER OR IOA/IOB
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0')) then WR <= '1'; end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0000") ) then R0 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0001") ) then R1 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0010") ) then R2 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0011") ) then R3 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0100") ) then R4 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0101") ) then R5 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0110") ) then R6 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "0111") ) then R7 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1000") ) then R8 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1001") ) then R9 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1010") ) then R10 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1011") ) then R11 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1100") ) then R12 <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1101") ) then R13 <= DATA_IN; RST_ENV <= '1'; end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1110") ) then IOA <= DATA_IN;end if;
if ( (BDIR = '1') and (BC2 = '1') and (BC1 = '0') and (REG_ADDR = "1111") ) then IOB <= DATA_IN;end if;
end PROCESS;
URA: PROCESS(REG_ADDR, RESET)
BEGIN
if (RESET = '1') then
BUS_CS <= "0000000000000000";
else
case REG_ADDR is
when "0000" => BUS_CS <= "0000000000000001";
when "0001" => BUS_CS <= "0000000000000010";
when "0010" => BUS_CS <= "0000000000000100";
when "0011" => BUS_CS <= "0000000000001000";
when "0100" => BUS_CS <= "0000000000010000";
when "0101" => BUS_CS <= "0000000000100000";
when "0110" => BUS_CS <= "0000000001000000";
when "0111" => BUS_CS <= "0000000010000000";
when "1000" => BUS_CS <= "0000000100000000";
when "1001" => BUS_CS <= "0000001000000000";
when "1010" => BUS_CS <= "0000010000000000";
when "1011" => BUS_CS <= "0000100000000000";
when "1100" => BUS_CS <= "0001000000000000";
when "1101" => BUS_CS <= "0010000000000000";
when "1110" => BUS_CS <= "0100000000000000";
when "1111" => BUS_CS <= "1000000000000000";
when others => NULL;
end case;
end if;
END PROCESS;
-- Instantiation of sub_level modules
UCLK : GEN_CLK PORT MAP( CLK => CLOCK,
RST => RESET,
CLK_16 => CLK_16,
CLK_256 => CLK_256
);
UTONE_A : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(1),
--CS_FINE => BUS_CS(0),
DATA_COARSE => R1,
DATA_FINE => R0,
OUT_TONE => CLK_A);
UTONE_B : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(3),
--CS_FINE => BUS_CS(2),
DATA_COARSE => R3,
DATA_FINE => R2,
OUT_TONE => CLK_B);
UTONE_C : TONE_GENERATOR PORT MAP( CLK => CLOCK,
--CLK_TONE => CLK_16,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(5),
--CS_FINE => BUS_CS(4),
DATA_COARSE => R5,
DATA_FINE => R4,
OUT_TONE => CLK_C);
UTONE_NOISE : NOISE_GENERATOR PORT MAP( CLK => CLK_16,
RST => RESET,
--WR => WR,
--CS => BUS_CS(6),
DATA => R6(4 downto 0),
CLK_N => CLK_N);
UTONE_ENV : TONE_GENERATOR PORT MAP( CLK => CLK_16,
--CLK => CLOCK,
--CLK_TONE => CLK_256,
RST => RESET,
WR => WR,
--CS_COARSE => BUS_CS(12),
--CS_FINE => BUS_CS(11),
DATA_COARSE => R12,
DATA_FINE => R11,
OUT_TONE => CLK_E);
--UMIXER : MIXER PORT MAP ( CLK => CLOCK,
-- CS => BUS_CS(7),
-- RST => RESET,
-- WR => WR,
-- IN_A => CLK_A,
-- IN_B => CLK_B,
-- IN_C => CLK_C,
-- IN_NOISE => CLK_N,
-- DATA => R7(5 downto 0),
-- OUT_A => CLK_TONE_A,
-- OUT_B => CLK_TONE_B,
-- OUT_C => CLK_TONE_C);
UGenEnv : GEN_ENV PORT MAP( CLK_ENV => CLK_E,
--CS => BUS_CS(13),
DATA => R13(3 downto 0),
RST_ENV => RST_ENV,
WR => WR,
OUT_DATA => OUT_AMPL_E);
UManAmpA : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_A, --CLK_TONE_A,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(0),
CLK_NOISE_ENA => R7(3),
AMPLITUDE => R8(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogA );
UManAmpB : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_B, --CLK_TONE_B,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(1),
CLK_NOISE_ENA => R7(4),
AMPLITUDE => R9(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogB );
UManAmpC : MANAGE_AMPLITUDE PORT MAP ( CLK => CLOCK,
CLK_DAC => CLOCK_DAC,
CLK_TONE => CLK_C, --CLK_TONE_C,
CLK_NOISE => CLK_N,
RST => RESET,
CLK_TONE_ENA => R7(2),
CLK_NOISE_ENA => R7(5),
AMPLITUDE => R10(4 downto 0),
AMPLITUDE_E => OUT_AMPL_E(3 downto 0),
OUT_DAC => IAnalogC );
--PAD_ANALOGA : OBUF_F_24 port map( I => IAnalogA, O => AnalogA);
--PAD_ANALOGB : OBUF_F_24 port map( I => IAnalogB, O => AnalogB);
--PAD_ANALOGC : OBUF_F_24 port map( I => IAnalogC, O => AnalogC);
AnalogA <= IAnalogA;
AnalogB <= IAnalogB;
AnalogC <= IAnalogC;
end Behavioral;

7
Computer_MiST/OricInFPGA_MiST/rtl/ay8912.vhd
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@ -32,7 +32,6 @@ entity ay8912 is
cs : in STD_LOGIC; --H-aktiv
bc0 : in STD_LOGIC; --
bdir : in STD_LOGIC;
PortAin : in STD_LOGIC_VECTOR (7 downto 0);
Data_in : in STD_LOGIC_VECTOR (7 downto 0);
oData : out STD_LOGIC_VECTOR (7 downto 0);
chanA : buffer STD_LOGIC_VECTOR (10 downto 0);
@ -114,7 +113,7 @@ END process;
-------------------------------------------------------------------------
--IO Regs
-------------------------------------------------------------------------
process (cpuclk, reset, PortA, PortAin, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0)
process (cpuclk, reset, PortA, PortB, Aperiode, Bperiode, Cperiode, Hperiode, AVol, BVol, CVol, Noise, HKurve, enable, Data_in, t_Data, PSGReg, bdir, bc0)
begin
IF reset='0' THEN
enable <= (others => '0');
@ -228,11 +227,7 @@ begin
WHEN "1101" =>
t_Data(3 downto 0) <= HKurve;
WHEN "1110" =>
IF enable(6)='0' THEN
t_Data <= PortA AND PortAin;
ELSE
t_Data <= PortA;
END IF;
WHEN "1111" =>
t_Data <= PortB;
END CASE;

106
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@ -1,65 +1,71 @@
-------------------------------------------------------------------------------
--
-- DAC.vhd
-- Delta-Sigma DAC
--
-- Digital to analog convertor.
-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
-- Refer to Xilinx Application Note XAPP154.
--
-- $Id: DAC.vhd, v0.2 2001/11/02 00:00:00 SEILEBOST $
-- This DAC requires an external RC low-pass filter:
--
-- from XAPP154.pdf & XAPP154.ZIP (XILINX APPLICATION)
--
-- DAC 8 Bits ( method : sigma delta)
-- 2^N clock to convert with N = width of input
-- Ex : Bus 8 bits => 256 CLOCK master to convert an value.
-- Theorem Shannon : 2 x Fmax x 256 =< 16 MHz => Fmax = 31250 Hz
-- band of sound : 0 -> 20000 Hz : Ok !!
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library ieee;
use ieee.std_logic_1164.all;
entity DAC is
Port ( CLK_DAC : in std_logic;
RST : in std_logic;
IN_DAC : in std_logic_vector(7 downto 0);
OUT_DAC : out std_logic );
end DAC;
entity dac is
architecture Behavioral of DAC is
generic (
msbi_g : integer := 7
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
signal DeltaAdder : std_logic_vector(9 downto 0);
signal SigmaAdder : std_logic_vector(9 downto 0);
signal SigmaLatch : std_logic_vector(9 downto 0);
signal DeltaB : std_logic_vector(9 downto 0);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
PROCESS(SigmaLatch, DeltaB)
BEGIN
DeltaB <= TRANSPORT ( SigmaLatch(9) & SigmaLatch(9) & "00000000");
END PROCESS;
PROCESS(IN_DAC, DeltaB, DeltaAdder)
BEGIN
DeltaAdder <= IN_DAC + DeltaB;
END PROCESS;
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
PROCESS(DeltaAdder, SigmaLatch)
BEGIN
SigmaAdder <= DeltaAdder + SigmaLatch;
END PROCESS;
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
PROCESS(CLK_DAC, RST)
BEGIN
if (RST = '1') then
SigmaLatch <= "0100000000";
OUT_DAC <= '1';
elsif (CLK_DAC'event and CLK_DAC = '1') then
SigmaLatch <= SigmaAdder;
OUT_DAC <= SigmaLatch(9);
end if;
END PROCESS;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
end Behavioral;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;

71
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@ -1,71 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dac2 is
generic (
msbi_g : integer := 7
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac2;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac2 is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;

44
Computer_MiST/OricInFPGA_MiST/rtl/gen_clk.vhd
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@ -1,44 +0,0 @@
--
-- GEN_CLK.vhd
--
-- GENERATOR of CLOCK.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: GEN_CLK.vhd, v0.42 2002/01/03 00:00:00 SEILEBOST $
--
-- Generate secondary CLK from CLK_MASTER
-- CLK : Clock Master, 16 MHz
-- CLK_16 : for the tone generator,
-- CLK_256 : for the envelope generator
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity GEN_CLK is
Port ( CLK : in std_logic;
RST : in std_logic;
CLK_16 : out std_logic;
CLK_256 : out std_logic
);
end GEN_CLK;
architecture Behavioral of GEN_CLK is
SIGNAL COUNT : std_logic_vector(7 downto 0);
begin
PROCESS(CLK, RST)
BEGIN
if (RST = '1') then
COUNT <= (OTHERS => '0');
elsif (CLK'event and CLK = '1') then
COUNT <= COUNT + 1;
CLK_16 <= COUNT(3);
CLK_256 <= COUNT(7);
end if;
END PROCESS;
end Behavioral;

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@ -1,111 +0,0 @@
--
-- GEN_ENV.vhd
--
-- GENERATOR of ENVELOPE.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: GEN_ENV.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
-- NO BUGS
-- NEARLY TESTED
--
-- Revision list
--
-- v0.4 2001/11/21 : Modification
-- v0.46 2010/01/06 : Modification du générateur d'enveloppe
-- et de fréquence
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity gen_env is
Port ( CLK_ENV : in std_logic;
DATA : in std_logic_vector(3 downto 0);
RST_ENV : in std_logic;
WR : in std_logic;
--CS : in std_logic;
OUT_DATA : inout std_logic_vector(3 downto 0) );
end gen_env;
architecture Behavioral of gen_env is
SIGNAL DIR : std_logic; -- direction
SIGNAL HOLD : std_logic; -- continue the sound
begin
PROCESS(CLK_ENV, RST_ENV, DATA, WR)
variable isMin : boolean;
variable isNearlyMin : boolean;
variable isNearlyMax : boolean;
variable isMax : boolean;
BEGIN
if (RST_ENV = '1') then -- Reset : to load the good value to generate enveloppe
if (DATA(2) = '0') then -- front initial : 0 = descendant et 1 = montant
OUT_DATA <= "1111";
DIR <= '0';
else
OUT_DATA <= "0000";
DIR <= '1';
end if;
HOLD <= '0';
elsif (CLK_ENV'event and CLK_ENV = '1') then -- edge clock
-- To simply the written code !
isMin := (OUT_DATA = "00000");
isNearlyMin := (OUT_DATA = "00001");
isNearlyMax := (OUT_DATA = "11110");
isMax := (OUT_DATA = "11111");
-- To manage the next value
if (HOLD = '0') then
if (DIR = '0') then
OUT_DATA <= OUT_DATA - 1;
else
OUT_DATA <= OUT_DATA + 1;
end if;
end if;
-- To generate the shape of envelope
if (DATA(3) = '0') then
if (DIR = '0') then
if (isNearlyMin) then
HOLD <= '1';
end if;
else
if (isMax) then
HOLD <= '1'; -- Astuce : il faut que OUT_DATE = "0000" au prochain tick donc comparaison de la sortie sur "1111" car incrementation automatique
end if;
end if;
else
if (DATA(0) = '1') then -- hold = 1
if (DIR = '0') then -- down
if (DATA(1) = '1') then -- alt
if isMin then HOLD <= '1'; end if;
else
if isNearlyMin then HOLD <= '1'; end if;
end if;
else
if (DATA(1) = '1') then -- alt
if isMax then HOLD <= '1'; end if;
else
if isNearlyMax then HOLD <= '1'; end if;
end if;
end if;
elsif (DATA(1) = '1') then -- alternate
if (DIR = '0') then -- down
if isNearlyMin then HOLD <= '1'; end if;
if isMin then HOLD <= '0'; DIR <= '1'; end if;
else
if isNearlyMax then HOLD <= '1'; end if;
if isMax then HOLD <= '0'; DIR <= '0'; end if;
end if;
end if;
end if;
end if; -- fin elsif
END PROCESS;
end Behavioral;

95
Computer_MiST/OricInFPGA_MiST/rtl/manage_amplitude.vhd
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@ -1,95 +0,0 @@
--
-- MANAGE_AMPLITUDE.vhd
--
-- Manage the amplitude for each tone.
--
-- Copyright (C)2001-2010 SEILEBOST
-- All rights reserved.
--
-- $Id: MANAGE_AMPLITUDE.vhd, v0.50 2010/01/19 00:00:00 SEILEBOST $
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MANAGE_AMPLITUDE is
Port ( CLK : in std_logic; -- the system clock
CLK_DAC : in std_logic; -- the clok of DAC
CLK_TONE : in std_logic; -- the frequency of sound
CLK_NOISE : in std_logic; -- the noise
RST : in std_logic; -- reset
CLK_TONE_ENA : in std_logic; -- enable tone
CLK_NOISE_ENA : in std_logic; -- enable noise
AMPLITUDE : in std_logic_vector(4 downto 0); -- value from register
AMPLITUDE_E : in std_logic_vector(3 downto 0); -- value from envelope
OUT_DAC : out std_logic );
end MANAGE_AMPLITUDE;
architecture Behavioral of MANAGE_AMPLITUDE is
signal AMPLITUDE_TMP : std_logic_vector(3 downto 0);
signal IN_DATA : std_logic_vector(7 downto 0);
COMPONENT DAC is Port ( CLK_DAC : in std_logic;
RST : in std_logic;
IN_DAC : in std_logic_vector(7 downto 0);
OUT_DAC : out std_logic );
END COMPONENT;
begin
-- Convertisseur numérique analogique : méthode sigma delta
U_DAC : DAC PORT MAP ( CLK_DAC => CLK_DAC,
RST => RST,
IN_DAC => IN_DATA,
OUT_DAC => OUT_DAC);
-- Calcule de l'amplitude à générer par le DAC
PROCESS(CLK, RST, AMPLITUDE_TMP, AMPLITUDE_E)
variable mix_tone_noise : std_logic;
BEGIN
if (RST = '1') then -- reset
AMPLITUDE_TMP <= "0000";
IN_DATA <= "00000000";
elsif (CLK'event and CLK = '1') then -- edge clock
-- Note that this means that if both tone and noise are disabled, the output */
-- is 1, not 0, and can be modulated changing the volume. */
mix_tone_noise := (CLK_TONE or CLK_TONE_ENA) AND (CLK_NOISE or CLK_NOISE_ENA);
if (mix_tone_noise = '1') then
if (AMPLITUDE(4) = '0') then -- Utilisation de la valeur du registre
AMPLITUDE_TMP <= AMPLITUDE(3 downto 0);
else -- Utilisation de la valeur de l'enveloppe
AMPLITUDE_TMP <= AMPLITUDE_E;
end if;
else
AMPLITUDE_TMP <= "0000";
end if;
-- Each amplitude has an 1.5 db step from previous amplitude
CASE AMPLITUDE_TMP IS
when "0000" => IN_DATA <= "00000000"; -- 0
when "0001" => IN_DATA <= "00010110"; -- 22
when "0010" => IN_DATA <= "00011010"; -- 26
when "0011" => IN_DATA <= "00011111"; -- 31
when "0100" => IN_DATA <= "00100101"; -- 37
when "0101" => IN_DATA <= "00101100"; -- 44
when "0110" => IN_DATA <= "00110100"; -- 52
when "0111" => IN_DATA <= "00111110"; -- 62
when "1000" => IN_DATA <= "01001010"; -- 74
when "1001" => IN_DATA <= "01011000"; -- 88
when "1010" => IN_DATA <= "01101001"; -- 105
when "1011" => IN_DATA <= "01110101"; -- 125
when "1100" => IN_DATA <= "10011001"; -- 149
when "1101" => IN_DATA <= "10110001"; -- 177
when "1110" => IN_DATA <= "11010010"; -- 210
when "1111" => IN_DATA <= "11111111"; -- 255
when OTHERS => NULL;
END CASE;
end if;
END PROCESS;
end Behavioral;

80
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@ -1,80 +0,0 @@
--
-- NOISE_GENERATOR.vhd
--
-- Generator a noise tone.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: NOISE_GENERATOR.vhd, v0.41 2002/01/03 00:00:00 SEILEBOST $
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity noise_generator is
Port ( CLK : in std_logic;
RST : in std_logic;
--WR : in std_logic;
--CS : in std_logic;
DATA : in std_logic_vector(4 downto 0);
CLK_N : out std_logic -- pseudo clock
);
end noise_generator;
architecture Behavioral of noise_generator is
SIGNAL COUNT : std_logic_vector(4 downto 0);
signal poly17 : std_logic_vector(16 downto 0) := (others => '0');
--SIGNAL ShiftEn : std_logic;
--SIGNAL FillSel : std_logic;
--SIGNAL DataIn : std_logic;
--SIGNAL lData : std_logic_vector(4 downto 0);
--COMPONENT i_pn_gen port (clk, ShiftEn, FillSel, DataIn_i, RESET : in std_logic;
-- pn_out_i : out std_logic);
--END COMPONENT;
begin
--U_IPNG : I_PN_GEN PORT MAP ( CLK => CLK,
-- ShiftEn => ShiftEn,
-- FillSel => FillSel,
-- RESET => RST,
-- DataIn_i => DataIn,
-- pn_out_i => CLK_N);
-- The noise generator
PROCESS(CLK,RST)
variable COUNT_MAX : std_logic_vector(4 downto 0);
variable poly17_zero : std_logic;
BEGIN
if (RST = '1') then
poly17 <= (others => '0');
elsif ( CLK'event and CLK = '1') then
if (DATA = "00000") then
COUNT_MAX := "00000";
else
COUNT_MAX := (DATA - "1");
end if;
-- Manage the polynome = 0 to regenerate another sequence
poly17_zero := '0';
if (poly17 = "00000000000000000") then poly17_zero := '1'; end if;
if (COUNT >= COUNT_MAX) then
COUNT <= "00000";
poly17 <= (poly17(0) xor poly17(2) xor poly17_zero)
& poly17(16 downto 1);
else
COUNT <= (COUNT + "1");
end if;
end if;
END PROCESS;
CLK_N <= poly17(0);
end Behavioral;

43
Computer_MiST/OricInFPGA_MiST/rtl/oricatmos.vhd
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@ -67,7 +67,8 @@ entity oricatmos is
K7_TAPEIN : in std_logic;
K7_TAPEOUT : out std_logic;
K7_REMOTE : out std_logic;
PSG_OUT : out std_logic_vector(7 downto 0);
PSG_RIGHT : out std_logic_vector(15 downto 0);
PSG_LEFT : out std_logic_vector(15 downto 0);
VIDEO_R : out std_logic;
VIDEO_G : out std_logic;
VIDEO_B : out std_logic;
@ -287,36 +288,30 @@ ad <= ula_AD_SRAM when ula_PHI2 = '0' else cpu_ad(15 downto 0);
ENA_4 => '1',
CLK => ula_CLK_4
);
inst_psg : entity work.YM2149
inst_psg : entity work.ay8912
port map (
I_DA => via_pa_out,
O_DA => via_pa_in,
O_DA_OE_L => open,
-- control
I_A9_L => '0',
I_A8 => '1',
I_BDIR => via_cb2_out,
I_BC2 => '1',
I_BC1 => psg_bdir,
I_SEL_L => '1',
O_AUDIO => PSG_OUT,
RESET_L => RESETn,
ENA => '1',
CLK => ula_PHI2
);
cpuclk => CLK_IN,
reset => RESETn,
cs => '1',
bc0 => psg_bdir,
bdir => via_cb2_out,
Data_in => via_pa_out,
oData => via_pa_in,
chanA => open,
chanB => open,
chanC => open,
Arechts => PSG_RIGHT,
Alinks => PSG_LEFT
);
inst_key : keyboard
port map(
clk_24 => CLK_IN,
clk => ula_phi2,
reset => not RESETn, -- active high reset
reset => not RESETn,
ps2_key => ps2_key,
row => via_pa_out,
row => via_pa_out,
col => via_out(2 downto 0),
ROWbit => KEY_ROW,
swrst => break

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@ -1,126 +0,0 @@
--
-- 16K RAM module using Xilinx RAMB blocks
--
-- (c) 2012 d18c7db(a)hotmail
--
-- This program is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License version 3 or, at your option,
-- any later version as published by the Free Software Foundation.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
--
-- For full details, see the GNU General Public License at www.gnu.org/licenses
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity ram16k is
port (
clk : in std_logic;
cs : in std_logic;
we : in std_logic;
addr : in std_logic_vector(13 downto 0);
di : in std_logic_vector( 7 downto 0);
do : out std_logic_vector( 7 downto 0)
);
end;
architecture RTL of ram16k is
begin
RAM_CPU_0 : RAMB16_S1
port map (
CLK => clk,
DI => di(0 downto 0),
DO => do(0 downto 0),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_1 : RAMB16_S1
port map (
CLK => clk,
DI => di(1 downto 1),
DO => do(1 downto 1),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_2 : RAMB16_S1
port map (
CLK => clk,
DI => di(2 downto 2),
DO => do(2 downto 2),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_3 : RAMB16_S1
port map (
CLK => clk,
DI => di(3 downto 3),
DO => do(3 downto 3),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_4 : RAMB16_S1
port map (
CLK => clk,
DI => di(4 downto 4),
DO => do(4 downto 4),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_5 : RAMB16_S1
port map (
CLK => clk,
DI => di(5 downto 5),
DO => do(5 downto 5),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_6 : RAMB16_S1
port map (
CLK => clk,
DI => di(6 downto 6),
DO => do(6 downto 6),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
RAM_CPU_7 : RAMB16_S1
port map (
CLK => clk,
DI => di(7 downto 7),
DO => do(7 downto 7),
ADDR => addr,
EN => cs,
SSR => '0',
WE => we
);
end RTL;

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Computer_MiST/OricInFPGA_MiST/rtl/rom_oa.vhd
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Computer_MiST/OricInFPGA_MiST/rtl/sprom.vhd
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@ -1,82 +0,0 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural := 8;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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@ -1,73 +0,0 @@
--
-- TONE_GENERATOR.vhd
--
-- Generator a tone.
--
-- Copyright (C)2001 SEILEBOST
-- All rights reserved.
--
-- $Id: TONE_GENERATOR.vhd, v0.56 2001/11/02 00:00:00 SEILEBOST $
--
-- Question : if WR is set To add one to count ?
--
-- Revision list
--
-- v0.2 2001/11/02 : Create
-- v0.46 2010/01/06 : Modification du générateur d'enveloppe
-- et de fréquence
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TONE_GENERATOR is
Port ( CLK : in std_logic;
--CLK_TONE : in std_logic;
RST : in std_logic;
WR : in std_logic;
--CS_COARSE : in std_logic;
--CS_FINE : in std_logic;
DATA_COARSE : in std_logic_vector(7 downto 0);
DATA_FINE : in std_logic_vector(7 downto 0);
OUT_TONE : inout std_logic );
end TONE_GENERATOR;
architecture Behavioral of TONE_GENERATOR is
SIGNAL COUNT : std_logic_vector(15 downto 0);
-- for debug : to clear ...
SIGNAL TMP_COUNT_MAX : std_logic_vector(15 downto 0);
SIGNAL TMP_COUNT_FREQ : std_logic_vector(15 downto 0);
begin
-- Génération de la fréquence de l'enveloppe
PROCESS(CLK, RST)
VARIABLE COUNT_FREQ : std_logic_vector(15 downto 0);
VARIABLE COUNT_MAX : std_logic_vector(15 downto 0);
BEGIN
if (RST = '1') then
COUNT <= "0000000000000000";
OUT_TONE <= '0';
elsif ( CLK'event and CLK = '1') then
COUNT_FREQ := DATA_COARSE & DATA_FINE;
if (COUNT_FREQ = x"0000") then
COUNT_MAX := x"0000";
else
COUNT_MAX := (COUNT_FREQ - "1");
end if;
if (COUNT >= COUNT_MAX) then
COUNT <= x"0000";
OUT_TONE <= not OUT_TONE;
else
COUNT <= (COUNT + "1");
end if;
-- for debug
TMP_COUNT_MAX <= COUNT_MAX;
TMP_COUNT_FREQ <= COUNT_FREQ;
end if;
end process;
end Behavioral;

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--
-- vag.vhd
--
-- Generate video signals
--
-- Copyright (C)2001 - 2005 SEILEBOST
-- All rights reserved.
--
-- $Id: vag.vhd, v0.01 2005/01/01 00:00:00 SEILEBOST $
--
-- TODO :
-- Remark :
library IEEE;
use IEEE.std_logic_1164.all;
--use IEEE.std_logic_arith.all;
--use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity vag is
port ( CLK_1 : in std_logic;
RESETn : in std_logic;
FREQ_SEL : in std_logic; -- Select 50/60 Hz frequency
CPT_H : out std_logic_vector(6 downto 0); -- Horizontal Counter
CPT_V : out std_logic_vector(8 downto 0); -- Vertical Counter
RELOAD_SEL : out std_logic; -- Reload registe SEL
FORCETXT : out std_logic; -- Force Mode Text
CLK_FLASH : out std_logic; -- Flash Clock
COMPSYNC : out std_logic; -- Composite Synchro signal
BLANKINGn : out std_logic -- Blanking signal
);
end entity vag;
architecture vag_arch of vag is
signal lCPT_H : std_logic_vector(6 downto 0);
signal lCPT_V : std_logic_vector(8 downto 0);
signal lCPT_FLASH : std_logic_vector(5 downto 0);
signal lVSYNCn : std_logic;
signal lVBLANKn : std_logic;
signal lVFRAME : std_logic;
signal lFORCETXT : std_logic;
signal lHSYNCn : std_logic;
signal lHBLANKn : std_logic;
signal lRELOAD_SEL : std_logic;
signal lCLK_V : std_logic;
begin
-- Horizontal Counter
u_CPT_H: PROCESS(CLK_1, RESETn)
BEGIN
IF (RESETn = '0') THEN
lCPT_H <= (OTHERS => '0');
ELSIF rising_edge(CLK_1) THEN
IF lCPT_H < 63 then
lCPT_H <= lCPT_H + "0000001";
ELSE
lCPT_H <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Horizontal Synchronisation
lHSYNCn <= '0' when (lCPT_H >= 49) AND (lCPT_H <= 53) ELSE '1';
-- Horizontal Blank
lHBLANKn <= '0' when (lCPT_H >= 40) AND (lCPT_H <= 63) ELSE '1';
-- Signal to Reload Register to reset attribut
lRELOAD_SEL <= '1' WHEN (lCPT_H >= 56) AND (lCPT_H <= 63) ELSE '0';
-- Clock for Vertical counter
lCLK_V <= '1' WHEN (lCPT_H = 63) ELSE '0';
-- Vertical Counter
u_CPT_V: PROCESS(lCLK_V, RESETn)
BEGIN
IF (RESETn = '0') THEN
lCPT_V <= (OTHERS => '0');
ELSIF rising_edge(lCLK_V) THEN
IF (lCPT_V < 311) THEN
lCPT_V <= lCPT_V + "000000001";
ELSE
lCPT_V <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Vertical Synchronisation
lVSYNCn <= '0' when(lCPT_V >= 258) AND (lCPT_V <= 259) ELSE '1';
-- Vertical Blank
lVBLANKn <= '0' when(lCPT_V >= 224) AND (lCPT_V <= 311) ELSE '1';
-- Clock to Flach Counter
lVFRAME <= '1' WHEN (lCPT_V = 311) ELSE '0';
-- Signal To Force TEXT MODE
lFORCETXT <= '1' WHEN (lCPT_V > 199) ELSE '0';
-- Flash Counter
u_FLASH : PROCESS( lVSYNCn, RESETn )
BEGIN
IF (RESETn = '0') THEN
lCPT_FLASH <= (OTHERS => '0');
ELSIF rising_edge(lVSYNCn) THEN
lCPT_FLASH <= lCPT_FLASH + "000001";
END IF;
END PROCESS;
-- Assign signals
FORCETXT <= '1' WHEN ((lFORCETXT = '1') OR (lVFRAME = '1') ) ELSE '0';
CLK_FLASH <= lCPT_FLASH(5);
RELOAD_SEL <= lRELOAD_SEL;
COMPSYNC <= NOT(lHSYNCn XOR lVSYNCn);
-- Assign counters
CPT_H <= lCPT_H;
CPT_V <= lCPT_V;
-- Assign blanking signal
BLANKINGn <= lVBLANKn AND lHBLANKn;
end architecture vag_arch;