mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-02-03 15:12:39 +00:00
Update T80
This commit is contained in:
Gyorgy Szombathelyi
@@ -167,11 +167,14 @@ begin
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if TState = "001" or (TState = "010" and Wait_n = '0') then
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RD_n <= not IntCycle_n;
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MREQ_n <= not IntCycle_n;
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IORQ_n <= IntCycle_n;
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end if;
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if TState = "011" then
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MREQ_n <= '0';
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end if;
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elsif MCycle = "011" and IntCycle_n = '0' then
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if TState = "001" then
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IORQ_n <= '0'; -- Acknowledge IRQ
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end if;
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else
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if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
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RD_n <= '0';
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@@ -118,7 +118,6 @@ entity T80 is
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TS : out std_logic_vector(2 downto 0);
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IntCycle_n : out std_logic;
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IntE : out std_logic;
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RETI_n : out std_logic;
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Stop : out std_logic;
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R800_mode : in std_logic := '0';
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out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
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@@ -259,13 +258,9 @@ architecture rtl of T80 is
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signal IMode : std_logic_vector(1 downto 0);
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signal Halt : std_logic;
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signal XYbit_undoc : std_logic;
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signal No_PC : std_logic;
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signal DOR : std_logic_vector(127 downto 0);
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signal ABus : std_logic_vector(15 downto 0);
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signal ABus_last : std_logic_vector(15 downto 0);
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signal NoRead_int : std_logic;
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signal Write_int : std_logic;
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begin
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REG <= IntE_FF2 & IntE_FF1 & IStatus & DOR & std_logic_vector(PC) & std_logic_vector(SP) & std_logic_vector(R) & I & Fp & Ap & F & ACC when Alternate = '0'
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@@ -341,10 +336,11 @@ begin
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SetEI => SetEI,
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IMode => IMode,
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Halt => Halt,
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NoRead => NoRead_int,
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Write => Write_int,
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XYbit_undoc => XYbit_undoc,
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R800_mode => R800_mode);
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NoRead => NoRead,
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Write => Write,
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R800_mode => R800_mode,
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No_PC => No_PC,
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XYbit_undoc => XYbit_undoc);
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alu : T80_ALU
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generic map(
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@@ -393,7 +389,7 @@ begin
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begin
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if RESET_n = '0' then
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PC <= (others => '0'); -- Program Counter
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ABus <= (others => '0');
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A <= (others => '0');
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WZ <= (others => '0');
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IR <= "00000000";
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ISet <= "00";
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@@ -425,11 +421,8 @@ begin
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PreserveC_r <= '0';
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XY_Ind <= '0';
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I_RXDD <= '0';
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RETI_n <= '1';
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elsif rising_edge(CLK_n) then
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RETI_n <= not I_RETN;
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if DIRSet = '1' then
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ACC <= DIR( 7 downto 0);
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@@ -440,7 +433,7 @@ begin
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R <= unsigned(DIR(47 downto 40));
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SP <= unsigned(DIR(63 downto 48));
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PC <= unsigned(DIR(79 downto 64));
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ABus <= DIR(79 downto 64);
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A <= DIR(79 downto 64);
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IStatus <= DIR(209 downto 208);
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elsif ClkEn = '1' then
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@@ -487,8 +480,8 @@ begin
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if TState = 2 and Wait_n = '1' then
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if Mode < 2 then
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ABus(7 downto 0) <= std_logic_vector(R);
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ABus(15 downto 8) <= I;
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A(7 downto 0) <= std_logic_vector(R);
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A(15 downto 8) <= I;
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R(6 downto 0) <= R(6 downto 0) + 1;
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end if;
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@@ -538,57 +531,58 @@ begin
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if T_Res = '1' then
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BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
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if Jump = '1' then
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ABus(15 downto 8) <= DI_Reg;
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ABus(7 downto 0) <= WZ(7 downto 0);
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A(15 downto 8) <= DI_Reg;
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A(7 downto 0) <= WZ(7 downto 0);
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PC(15 downto 8) <= unsigned(DI_Reg);
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PC(7 downto 0) <= unsigned(WZ(7 downto 0));
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elsif JumpXY = '1' then
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ABus <= RegBusC;
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A <= RegBusC;
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PC <= unsigned(RegBusC);
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elsif Call = '1' or RstP = '1' then
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ABus <= WZ;
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A <= WZ;
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PC <= unsigned(WZ);
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elsif MCycle = MCycles and NMICycle = '1' then
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ABus <= "0000000001100110";
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A <= "0000000001100110";
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PC <= "0000000001100110";
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elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
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ABus(15 downto 8) <= I;
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ABus(7 downto 0) <= WZ(7 downto 0);
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elsif ((Mode /= 3 and MCycle = "011") or (Mode = 3 and MCycle = "100"))
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and IntCycle = '1' and IStatus = "10" then
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A(15 downto 8) <= I;
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A(7 downto 0) <= WZ(7 downto 0);
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PC(15 downto 8) <= unsigned(I);
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PC(7 downto 0) <= unsigned(WZ(7 downto 0));
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else
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case Set_Addr_To is
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when aXY =>
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if XY_State = "00" then
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ABus <= RegBusC;
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A <= RegBusC;
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else
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if NextIs_XY_Fetch = '1' then
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ABus <= std_logic_vector(PC);
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A <= std_logic_vector(PC);
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else
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ABus <= WZ;
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A <= WZ;
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end if;
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end if;
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when aIOA =>
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if Mode = 3 then
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-- Memory map I/O on GBZ80
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ABus(15 downto 8) <= (others => '1');
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A(15 downto 8) <= (others => '1');
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elsif Mode = 2 then
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-- Duplicate I/O address on 8080
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ABus(15 downto 8) <= DI_Reg;
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A(15 downto 8) <= DI_Reg;
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else
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ABus(15 downto 8) <= ACC;
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A(15 downto 8) <= ACC;
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end if;
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ABus(7 downto 0) <= DI_Reg;
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A(7 downto 0) <= DI_Reg;
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WZ <= (ACC & DI_Reg) + "1";
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when aSP =>
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ABus <= std_logic_vector(SP);
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A <= std_logic_vector(SP);
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when aBC =>
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if Mode = 3 and IORQ_i = '1' then
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-- Memory map I/O on GBZ80
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ABus(15 downto 8) <= (others => '1');
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ABus(7 downto 0) <= RegBusC(7 downto 0);
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A(15 downto 8) <= (others => '1');
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A(7 downto 0) <= RegBusC(7 downto 0);
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else
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ABus <= RegBusC;
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A <= RegBusC;
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if SetWZ = "01" then
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WZ <= RegBusC + "1";
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end if;
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@@ -598,24 +592,29 @@ begin
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end if;
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end if;
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when aDE =>
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ABus <= RegBusC;
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A <= RegBusC;
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if SetWZ = "10" then
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WZ(7 downto 0) <= RegBusC(7 downto 0) + "1";
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WZ(15 downto 8) <= ACC;
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end if;
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when aZI =>
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if Inc_WZ = '1' then
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ABus <= std_logic_vector(unsigned(WZ) + 1);
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A <= std_logic_vector(unsigned(WZ) + 1);
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else
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ABus(15 downto 8) <= DI_Reg;
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ABus(7 downto 0) <= WZ(7 downto 0);
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A(15 downto 8) <= DI_Reg;
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A(7 downto 0) <= WZ(7 downto 0);
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if SetWZ = "10" then
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WZ(7 downto 0) <= WZ(7 downto 0) + "1";
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WZ(15 downto 8) <= ACC;
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end if;
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end if;
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when others =>
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ABus <= std_logic_vector(PC);
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if ISet = "10" and IR(7 downto 4) = x"B" and IR(2 downto 1) = "01" and MCycle = 3 and No_BTR = '0' then
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-- INIR, INDR, OTIR, OTDR
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A <= RegBusA_r;
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elsif No_PC = '0' or No_BTR = '1' or (I_DJNZ = '1' and IncDecZ = '1') or Mode > 1 then
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A <= std_logic_vector(PC);
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end if;
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end case;
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end if;
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@@ -673,7 +672,7 @@ begin
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end if;
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end if;
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if (TState = 2 and I_BTR = '1' and IR(0) = '1' and Wait_n = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
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if (TState = 2 and I_BTR = '1' and IR(0) = '1') or (TState = 1 and I_BTR = '1' and IR(0) = '0') then
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ioq := ('0' & DI_Reg) + ('0' & std_logic_vector(ID16(7 downto 0)));
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F(Flag_N) <= DI_Reg(7);
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F(Flag_C) <= ioq(8);
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@@ -720,7 +719,7 @@ begin
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end if;
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end if;
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if ADDSPdd = '1' and TState = 2 and Wait_n = '1' then
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if ADDSPdd = '1' and TState = 2 then
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WZ <= std_logic_vector(SP);
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SP <= unsigned(signed(SP)+signed(Save_Mux));
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end if;
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@@ -958,7 +957,7 @@ begin
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if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
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IncDecZ <= F_Out(Flag_Z);
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end if;
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if ((TState = 2 and Wait_n = '1') or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
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if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
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if ID16 = 0 then
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IncDecZ <= '0';
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else
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@@ -1066,7 +1065,7 @@ begin
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RegDIL <= RegBusA_r(7 downto 0);
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end if;
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if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001" and Wait_n = '1') or (TState = 3 and MCycle = "001")) then
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if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
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RegDIH <= std_logic_vector(ID16(15 downto 8));
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RegDIL <= std_logic_vector(ID16(7 downto 0));
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end if;
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@@ -1179,9 +1178,6 @@ begin
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else
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RFSH_n <= '1';
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end if;
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if (TState = 1 and (NoRead_int = '0' and IORQ_i = '0')) or (TState = 3 and MCycle = "001") then
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ABus_last <= ABus;
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end if;
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end if;
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end if;
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end process;
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@@ -1195,11 +1191,6 @@ begin
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IntE <= IntE_FF1;
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IORQ <= IORQ_i;
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Stop <= I_DJNZ;
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NoRead <= NoRead_int;
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Write <= Write_int;
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A <= ABus when (Mode > 1) or (NoRead_int = '0' or Write_int = '1') else ABus_last;
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-------------------------------------------------------------------------
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--
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-- Main state machine
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@@ -1225,7 +1216,6 @@ begin
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--BusReq_s <= '0';
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NMI_s <= '0';
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elsif rising_edge(CLK_n) then
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if DIRSet = '1' then
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IntE_FF2 <= DIR(211);
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IntE_FF1 <= DIR(210);
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@@ -1247,7 +1237,7 @@ begin
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No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
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(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
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(I_BTR and (not IR(4) or F(Flag_Z)));
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if TState = 2 and Wait_n = '1' then
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if TState = 2 then
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if SetEI = '1' then
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IntE_FF1 <= '1';
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IntE_FF2 <= '1';
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@@ -1280,6 +1270,13 @@ begin
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BusAck <= '1';
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else
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TState <= "001";
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if (IntCycle = '1' and Mode = 3) then -- GB: read interrupt at MCycle 3
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if (MCycle = "010") then
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M1_n <= '0';
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else
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M1_n <= '1';
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end if;
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end if;
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if NextIs_XY_Fetch = '1' then
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MCycle <= "110";
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Pre_XY_F_M <= MCycle;
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@@ -150,8 +150,9 @@ entity T80_MCode is
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Halt : out std_logic;
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NoRead : out std_logic;
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Write : out std_logic;
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XYbit_undoc : out std_logic;
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R800_mode : in std_logic
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R800_mode : in std_logic;
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No_PC : out std_logic;
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XYbit_undoc : out std_logic
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);
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end T80_MCode;
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@@ -255,6 +256,7 @@ begin
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Halt <= '0';
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NoRead <= '0';
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Write <= '0';
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No_PC <= '0';
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XYbit_undoc <= '0';
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SetWZ <= "00";
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@@ -859,21 +861,22 @@ begin
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end case;
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elsif IntCycle = '1' then
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-- INT (IM 2)
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if mode = 3 then
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if Mode = 3 then
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MCycles <= "100";
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case to_integer(unsigned(MCycle)) is
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when 1 =>
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LDZ <= '1';
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TStates <= "110";
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IncDec_16 <= "1111";
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Set_Addr_To <= aSP;
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Set_BusB_To <= "1101";
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when 2 =>
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Write <= '1';
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when 3 => -- GB: interrupt is acknowledged on MCycle 3
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LDZ <= '1';
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IncDec_16 <= "1111";
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Set_Addr_To <= aSP;
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Set_BusB_To <= "1100";
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when 3 =>
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when 4 =>
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Write <= '1';
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when others => null;
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end case;
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@@ -956,6 +959,8 @@ begin
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else
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MCycles <= "011";
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case to_integer(unsigned(MCycle)) is
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when 1 =>
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No_PC <= '1';
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when 2 =>
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NoRead <= '1';
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ALU_Op <= "0000";
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@@ -972,6 +977,7 @@ begin
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TStates <= "100";
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Arith16 <= '1';
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SetWZ <= "11";
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No_PC <= '1';
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when 3 =>
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NoRead <= '1';
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Read_To_Reg <= '1';
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@@ -1141,6 +1147,7 @@ begin
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case to_integer(unsigned(MCycle)) is
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when 2 =>
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Inc_PC <= '1';
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No_PC <= '1';
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when 3 =>
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NoRead <= '1';
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JumpE <= '1';
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@@ -1157,6 +1164,8 @@ begin
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Inc_PC <= '1';
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if F(Flag_C) = '0' then
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MCycles <= "010";
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else
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No_PC <= '1';
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end if;
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when 3 =>
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NoRead <= '1';
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@@ -1174,6 +1183,8 @@ begin
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Inc_PC <= '1';
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if F(Flag_C) = '1' then
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MCycles <= "010";
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else
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No_PC <= '1';
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end if;
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when 3 =>
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NoRead <= '1';
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@@ -1191,6 +1202,8 @@ begin
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Inc_PC <= '1';
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if F(Flag_Z) = '0' then
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MCycles <= "010";
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else
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No_PC <= '1';
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end if;
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when 3 =>
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NoRead <= '1';
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@@ -1208,6 +1221,8 @@ begin
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Inc_PC <= '1';
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if F(Flag_Z) = '1' then
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MCycles <= "010";
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else
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No_PC <= '1';
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end if;
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when 3 =>
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NoRead <= '1';
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@@ -1243,6 +1258,7 @@ begin
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when 2 =>
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I_DJNZ <= '1';
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Inc_PC <= '1';
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No_PC <= '1';
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when 3 =>
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NoRead <= '1';
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JumpE <= '1';
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@@ -1895,6 +1911,7 @@ begin
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else
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IncDec_16 <= "1101";
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end if;
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No_PC <= '1';
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when 4 =>
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NoRead <= '1';
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TStates <= "101";
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@@ -1918,10 +1935,12 @@ begin
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else
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IncDec_16 <= "1110";
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end if;
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No_PC <= '1';
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when 3 =>
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NoRead <= '1';
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I_BC <= '1';
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TStates <= "101";
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No_PC <= '1';
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when 4 =>
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NoRead <= '1';
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TStates <= "101";
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@@ -1948,6 +1967,8 @@ begin
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-- ADC HL,ss
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MCycles <= "011";
|
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case to_integer(unsigned(MCycle)) is
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when 1 =>
|
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No_PC <= '1';
|
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when 2 =>
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NoRead <= '1';
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ALU_Op <= "0001";
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@@ -1963,6 +1984,7 @@ begin
|
||||
end case;
|
||||
TStates <= "100";
|
||||
SetWZ <= "11";
|
||||
No_PC <= '1';
|
||||
when 3 =>
|
||||
NoRead <= '1';
|
||||
Read_To_Reg <= '1';
|
||||
@@ -1982,6 +2004,8 @@ begin
|
||||
-- SBC HL,ss
|
||||
MCycles <= "011";
|
||||
case to_integer(unsigned(MCycle)) is
|
||||
when 1 =>
|
||||
No_PC <= '1';
|
||||
when 2 =>
|
||||
NoRead <= '1';
|
||||
ALU_Op <= "0011";
|
||||
@@ -1997,6 +2021,7 @@ begin
|
||||
end case;
|
||||
TStates <= "100";
|
||||
SetWZ <= "11";
|
||||
No_PC <= '1';
|
||||
when 3 =>
|
||||
NoRead <= '1';
|
||||
ALU_Op <= "0011";
|
||||
@@ -2023,6 +2048,7 @@ begin
|
||||
Set_BusA_To(2 downto 0) <= "111";
|
||||
ALU_Op <= "1101";
|
||||
Save_ALU <= '1';
|
||||
No_PC <= '1';
|
||||
when 3 =>
|
||||
TStates <= "100";
|
||||
I_RLD <= '1';
|
||||
@@ -2044,6 +2070,7 @@ begin
|
||||
Set_BusA_To(2 downto 0) <= "111";
|
||||
ALU_Op <= "1110";
|
||||
Save_ALU <= '1';
|
||||
No_PC <= '1';
|
||||
when 3 =>
|
||||
TStates <= "100";
|
||||
I_RRD <= '1';
|
||||
@@ -2237,6 +2264,9 @@ begin
|
||||
if IRB = "00110110" or IRB = "11001011" then
|
||||
Set_Addr_To <= aNone;
|
||||
end if;
|
||||
if not (IRB = "00110110" or ISet = "01") then
|
||||
No_PC <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if MCycle = "111" then
|
||||
if Mode = 0 then
|
||||
|
||||
@@ -104,7 +104,6 @@ package T80_Pack is
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
RETI_n : out std_logic;
|
||||
Stop : out std_logic;
|
||||
R800_mode : in std_logic := '0';
|
||||
out0 : in std_logic := '0'; -- 0 => OUT(C),0, 1 => OUT(C),255
|
||||
@@ -210,8 +209,9 @@ package T80_Pack is
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
XYbit_undoc : out std_logic;
|
||||
R800_mode : in std_logic
|
||||
R800_mode : in std_logic;
|
||||
No_PC : out std_logic;
|
||||
XYbit_undoc : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
|
||||
@@ -96,9 +96,7 @@ entity T80se is
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
IntE : out std_logic;
|
||||
RETI_n : out std_logic
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80se;
|
||||
|
||||
@@ -139,9 +137,7 @@ begin
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n,
|
||||
IntE => IntE,
|
||||
RETI_n => RETI_n);
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
|
||||
Reference in New Issue
Block a user