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Code Issues Releases Wiki Activity

IremM92: update from upstream

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This commit is contained in:
Gyorgy Szombathelyi
2023-05-04 11:20:18 +02:00
parent 7f74954fbc
commit b4d6a95c8f
8 changed files with 47 additions and 26 deletions
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20
Arcade_MiST/IremM92 Hardware/rtl/IremM92_MiST.sv
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@@ -52,7 +52,9 @@ localparam CONF_STR = {
`endif
//"OD,Audio Filters,On,Off;",
"DIP;",
`ifndef NO_EEPROM
"R8192,Save EEPROM;",
`endif
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
@@ -66,7 +68,7 @@ wire [2:0] dbg_en_layers = ~status[11:9];
wire dbg_fm_en = ~status[12];
wire dbg_sprite_freeze = 0;
wire filters = 0;//~status[13];
wire [1:0] orientation = {1'b0, core_mod[0]};
wire [1:0] orientation = {flipped, core_mod[0]};
reg oneplayer = 0;
wire [15:0] dip_sw = status[31:16];
@@ -323,13 +325,13 @@ rom_loader rom_loader(
wire [15:0] ch_left, ch_right;
wire [7:0] R, G, B;
wire HBlank, VBlank, HSync, VSync;
wire blankn = !(HBlank | VBlank);
wire ce_pix;
wire flipped;
m92 m92(
.clk_sys(CLK_40M),
.ce_pix(ce_pix),
.flipped(flipped),
.reset_n(~reset),
.HBlank(HBlank),
.VBlank(VBlank),
@@ -420,14 +422,16 @@ m92 m92(
.en_audio_filters(filters)
);
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10)) mist_video(
mist_video #(.COLOR_DEPTH(6), .SD_HCNT_WIDTH(10), .USE_BLANKS(1)) mist_video(
.clk_sys ( CLK_40M ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? R[7:2] : 0 ),
.G ( blankn ? G[7:2] : 0 ),
.B ( blankn ? B[7:2] : 0 ),
.R ( R[7:2] ),
.G ( G[7:2] ),
.B ( B[7:2] ),
.HBlank ( HBlank ),
.VBlank ( VBlank ),
.HSync ( HSync ),
.VSync ( VSync ),
.VGA_R ( VGA_R ),
@@ -469,7 +473,7 @@ wire m_up4, m_down4, m_left4, m_right4, m_up4B, m_down4B, m_left4B, m_right4B;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
wire [11:0] m_fire1, m_fire2, m_fire3, m_fire4;
arcade_inputs inputs (
arcade_inputs #(.START1(10), .START2(12), .COIN1(11)) inputs (
.clk ( CLK_40M ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),

2
Arcade_MiST/IremM92 Hardware/rtl/ga21.sv
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@@ -221,7 +221,7 @@ end
assign dout = buf_cs ? (direct_access_obj ? obj_din : (direct_access_pal ? pal_din : buffer_din)) : 16'd0;
assign busy = copy_state != IDLE;
assign buffer_we = ~busy & buf_cs & wr & ~direct_access_obj & ~direct_access_pal;
assign buffer_we = ~busy & buf_cs & wr;
assign buffer_addr = busy ? buffer_src_addr : addr;
assign buffer_dout = din;

8
Arcade_MiST/IremM92 Hardware/rtl/ga22.sv
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@@ -53,7 +53,7 @@ reg linebuf_write;
reg linebuf_flip;
reg scan_toggle = 0;
reg [9:0] scan_pos = 0;
wire [9:0] scan_pos_nl = scan_pos ^ {10{NL}};
wire [9:0] scan_pos_nl = scan_pos ^ {1'b0, {9{NL}}};
wire [11:0] scan_out;
double_linebuf line_buffer(
@@ -87,11 +87,13 @@ wire obj_flipx = obj_data[40];
wire obj_flipy = obj_data[41];
wire [9:0] obj_org_x = obj_data[57:48];
reg [8:0] V;
wire [8:0] VE = V ^ {9{NL}};
always_ff @(posedge clk) begin
reg visible;
reg [3:0] span;
reg [3:0] end_span;
reg [8:0] V;
reg [15:0] code;
reg [8:0] height_px;
@@ -144,7 +146,7 @@ always_ff @(posedge clk) begin
end_span <= ( 4'd1 << obj_width ) - 1'd1;
height_px = 9'd16 << obj_height;
width = 4'd1 << obj_width;
rel_y = V + obj_org_y + ( 9'd16 << obj_height );
rel_y = VE + obj_org_y + ( 9'd16 << obj_height );
row_y = obj_flipy ? (height_px - rel_y - 9'd1) : rel_y;
if (rel_y < height_px) begin

20
Arcade_MiST/IremM92 Hardware/rtl/ga23.sv
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@@ -33,6 +33,8 @@ module GA23(
output reg vram_req,
input [31:0] vram_din,
input NL,
input large_tileset,
input [31:0] sdr_data_a,
@@ -77,7 +79,11 @@ assign vblank = vcnt > 10'd113 && vcnt < 10'd136;
assign vsync = vcnt > 10'd119 && vcnt < 10'd125;
assign hpulse = hcnt == 10'd48;
assign vpulse = (vcnt == 10'd124 && hcnt > 10'd260) || (vcnt == 10'd125 && hcnt < 10'd260);
assign hint = vcnt == hint_line && hcnt > 10'd422 && ~paused;
wire [9:0] VE = vcnt ^ {1'b0, {9{NL}}};
assign hint = VE == hint_line && hcnt > 10'd422 && ~paused;
always_ff @(posedge clk) begin
if (ce) begin
@@ -149,19 +155,19 @@ always_ff @(posedge clk, posedge reset) begin
case(rs_cyc)
0: vram_addr <= 'h7800;
4: begin
rs_y = y_ofs[0] + vcnt;
rs_y = y_ofs[0] + VE;
vram_addr <= 'h7a00 + rs_y[8:0];
vram_req <= ~vram_req;
end
7: rowscroll[0] <= vram_din[9:0];
8: begin
rs_y = y_ofs[1] + vcnt;
rs_y = y_ofs[1] + VE;
vram_addr <= 'h7c00 + rs_y[8:0];
vram_req <= ~vram_req;
end
10: rowscroll[1] <= vram_din[9:0];
12: begin
rs_y = y_ofs[2] + vcnt;
rs_y = y_ofs[2] + VE;
vram_addr <= 'h7e00 + rs_y[8:0];
vram_req <= ~vram_req;
end
@@ -280,15 +286,15 @@ generate
.clk(clk),
.ce_pix(ce),
.NL(0),
.NL(NL),
.large_tileset(large_tileset),
.x_ofs(_x_ofs),
.y_ofs(_y_ofs),
.control(_control),
.x_base({hcnt[9:3], 3'd0}),
.y(_y_ofs + vcnt),
.x_base({hcnt[9:3] ^ {7{NL}}, 3'd0}),
.y(_y_ofs + VE),
.rowscroll(_rowscroll),
.vram_addr(layer_vram_addr[i]),

8
Arcade_MiST/IremM92 Hardware/rtl/ga23_layer.sv
View File

@@ -58,10 +58,10 @@ wire wide = control[2];
wire enabled = ~control[4] & dbg_enabled;
wire en_rowscroll = control[6];
wire [9:0] x = x_base + ( en_rowscroll ? rowscroll : x_ofs );
wire [6:0] tile_x = x[9:3] + ( wide ? 7'd32 : 7'd0);
wire [6:0] tile_x = NL ? ( x[9:3] - ( wide ? 7'd32 : 7'd0) ) : ( x[9:3] + ( wide ? 7'd32 : 7'd0) );
wire [5:0] tile_y = y[8:3];
assign vram_addr = vram_base + (wide ? {1'b0, tile_y, tile_x[6:0], 1'b0} : {2'b00, tile_y, tile_x[5:0], 1'b0});
assign vram_addr = wide ? {vram_base[14], tile_y, tile_x[6:0], 1'b0} : {vram_base[14:13], tile_y, tile_x[5:0], 1'b0};
reg [3:0] cnt;
@@ -81,8 +81,8 @@ always_ff @(posedge clk) begin
sdr_req <= ~sdr_req;
palette <= attrib[6:0];
prio <= attrib[8:7];
flip_x <= attrib[9];
offset <= x[2:0];
flip_x <= attrib[9] ^ NL;
offset <= x[2:0] ^ {3{NL}};
end
end
end

8
Arcade_MiST/IremM92 Hardware/rtl/m92.sv
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@@ -25,9 +25,9 @@ module m92 (
input reset_n,
output reg ce_pix,
output flipped,
input board_cfg_t board_cfg,
output [7:0] R,
output [7:0] G,
@@ -128,6 +128,7 @@ module m92 (
);
assign ioctl_upload_index = 8'd1;
assign flipped = NL;
wire [15:0] rgb_color;
assign R = { rgb_color[4:0], rgb_color[4:2] };
@@ -359,7 +360,7 @@ end
wire int_req, int_ack;
wire [8:0] int_vector;
v30 v30(
v30 #(.INTACK_DELAY(0)) v30(
.clk(clk_sys),
.ce(ce_cpu),
.ce_4x(ce_4x_cpu),
@@ -593,6 +594,7 @@ GA23 ga23(
.vram_din(sdr_vram_data),
.vram_req(sdr_vram_req),
.NL(NL),
.large_tileset(board_cfg.large_tileset),
.sdr_data_a(sdr_bg_data_a),
@@ -696,6 +698,7 @@ sound sound(
assign AUDIO_L = sound_sample;
assign AUDIO_R = sound_sample;
`ifndef NO_EEPROM
eeprom_28C64 eeprom(
.clk(clk_sys),
.reset(~reset_n),
@@ -720,5 +723,6 @@ eeprom_28C64 eeprom(
.ioctl_din(ioctl_din),
.ioctl_rd(ioctl_rd)
);
`endif
endmodule

1
Arcade_MiST/IremM92 Hardware/sidi/IremM92.qsf
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@@ -249,4 +249,5 @@ set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/v30/V30.qip
set_global_assignment -name QIP_FILE ../../../common/Sound/jt51/jt51.qip
set_global_assignment -name VERILOG_MACRO "JT51_ONLYTIMERS=1"
set_global_assignment -name VERILOG_MACRO "NO_EEPROM=1"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

6
common/CPU/v30/cpu.vhd
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@@ -33,6 +33,10 @@ use work.pReg_savestates.all;
use work.whatever.all;
entity v30 is
generic
(
INTACK_DELAY : integer := 22
);
port
(
clk : in std_logic;
@@ -698,7 +702,7 @@ begin
if (irqrequest = '1') then
irqrequest <= '0';
repeat <= '0';
delay <= 22;
delay <= INTACK_DELAY;
cpustage <= CPUSTAGE_IRQVECTOR_REQ;
pushlist <= REGPOS_f or REGPOS_cs or REGPOS_ip;
poplist <= (others => '0');