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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-19 17:27:59 +00:00

IremM62: add a PAL mode switch

This commit is contained in:
Gyorgy Szombathelyi 2020-03-13 16:42:59 +01:00
parent 82869e1332
commit b7b98ab13a
5 changed files with 15 additions and 2 deletions

View File

@ -16,6 +16,7 @@ entity Graphics is
(
hwsel : in HWSEL_t;
hires : in std_logic;
palmode : in std_logic;
sprite_prom : in prom_a(0 to 31);
bitmap_ctl_i : in to_BITMAP_CTL_a(1 to PACE_VIDEO_NUM_BITMAPS);
@ -78,6 +79,7 @@ begin
-- clocking etc
video_i => video_i,
hwsel => hwsel,
palmode => palmode,
hires => hires,
-- video data signals (in)

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@ -36,6 +36,7 @@ wire [6:0] core_mod;
localparam CONF_STR = {
`CORE_NAME,";;",
"O2,Rotate Controls,Off,On;",
"O1,Video Timings,Original,PAL 50Hz;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Service,Off,On;",
@ -43,6 +44,7 @@ localparam CONF_STR = {
"V,v1.0.",`BUILD_DATE
};
wire palmode = status[1];
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
@ -258,6 +260,7 @@ target_top target_top(
.clk_aud(clk_aud),//0.895MHz
.reset_in(reset),
.hwsel(core_mod),
.palmode(palmode),
.audio_out(audio),
.usr_coin1(m_coin1),
.usr_coin2(m_coin2),

View File

@ -12,6 +12,7 @@ entity iremm62_video_controller is
-- clocking etc
video_i : in from_VIDEO_t;
hwsel : in HWSEL_t;
palmode : in std_logic;
hires : in std_logic;
-- video input data
@ -59,8 +60,11 @@ begin
hcnt <= "00"&x"80";
vcnt <= vcnt + 1;
if vcnt = '1'&x"FF" then
-- vcnt <= '0'&x"E6"; -- from M52 schematics
vcnt <= '0'&x"C8"; -- 312 lines/PAL 50 Hz
if palmode = '1' then
vcnt <= '0'&x"C8"; -- 312 lines/PAL 50 Hz
else
vcnt <= '0'&x"E6"; -- from M52 schematics
end if;
end if;
end if;
end if;

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@ -20,6 +20,7 @@ entity PACE is
-- hardware variant
hwsel : in HWSEL_t;
palmode : in std_logic;
hires : in std_logic;
-- misc I/O
@ -163,6 +164,7 @@ begin
(
hwsel => hwsel,
hires => hires,
palmode => palmode,
sprite_prom => sprite_prom,
bitmap_ctl_i => to_bitmap_ctl,

View File

@ -15,6 +15,7 @@ entity target_top is port(
clk_aud : in std_logic;
reset_in : in std_logic;
hwsel : in HWSEL_t;
palmode : in std_logic;
audio_out : out std_logic_vector(11 downto 0);
usr_coin1 : in std_logic;
usr_coin2 : in std_logic;
@ -147,6 +148,7 @@ pace_inst : entity work.pace
clkrst_i => clkrst_i,
cpu_clk_en_i => cpu_clk_en,
hwsel => hwsel,
palmode => palmode,
hires => hires,
buttons_i => buttons_i,
switches_i => switches_i,