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Update JT modules

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This commit is contained in:
Gyorgy Szombathelyi
2022-12-21 00:44:37 +01:00
parent e34ee3cf26
commit b81529cebf
43 changed files with 385 additions and 322 deletions
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0
common/Sound/JT12/hdl/adpcm/gen_lingain.py Normal file → Executable file
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32
common/Sound/JT12/hdl/adpcm/jt10_adpcm.v
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@@ -31,11 +31,7 @@ module jt10_adpcm(
output signed [15:0] pcm
);
localparam sigw = 13; // 1 bit more than the actual signal width so
localparam shift = 3; //16-sigw;
// there is room for overflow
wire signed [sigw-1:0] max_pos = { 2'b00, {sigw-2{1'b1}} };
wire signed [sigw-1:0] max_neg = { 2'b11, {sigw-2{1'b0}} };
localparam sigw = 12;
reg signed [sigw-1:0] x1, x2, x3, x4, x5, x6;
reg signed [sigw-1:0] inc4;
@@ -44,13 +40,13 @@ reg [5:0] step_next, step_1p;
reg sign2, sign3, sign4, sign5, xsign5;
// All outputs from stage 1
assign pcm = { {16-sigw{x1[sigw-1]}}, x1 } <<< shift;
assign pcm = { {16-sigw{x1[sigw-1]}}, x1 };
// This could be decomposed in more steps as the pipeline
// has room for it
always @(*) begin
casez( data[2:0] )
3'b0??: step_next = step1==6'd0 ? 6'd0 : (step1-6'd1);
3'b0??: step_next = step1==6'd0 ? 6'd0 : (step1-1'd1);
3'b100: step_next = step1+6'd2;
3'b101: step_next = step1+6'd5;
3'b110: step_next = step1+6'd7;
@@ -93,9 +89,9 @@ always @( posedge clk or negedge rst_n )
end else if(cen) begin
// I
sign2 <= data[3];
x2 <= clr ? {sigw{1'b0}} : x1;
x2 <= clr ? {sigw-1{1'b0}} : x1;
step2 <= clr ? 6'd0 : (chon ? step_1p : step1);
chon2 <= chon;
chon2 <= ~clr && chon;
lut_addr2 <= { step1, data[2:0] };
// II 2's complement of inc2 if necessary
sign3 <= sign2;
@@ -103,30 +99,22 @@ always @( posedge clk or negedge rst_n )
step3 <= step2;
chon3 <= chon2;
// III
sign4 <= sign3;
inc4 <= sign3 ? ~inc3_long + 1 : inc3_long;
//sign4 <= sign3;
inc4 <= sign3 ? ~inc3_long + 1'd1 : inc3_long;
x4 <= x3;
step4 <= step3;
chon4 <= chon3;
// IV
sign5 <= sign4;
xsign5 <= x4[sigw-1];
//sign5 <= sign4;
//xsign5 <= x4[sigw-1];
x5 <= chon4 ? x4 + inc4 : x4;
step5 <= step4;
// V
// if( xsign5!=x5[sigw-1] && sign5!=x5[sigw-1] ) begin // enable limiter
// if( sign5 ) // it was negative
// x6 <= {1'b1, {sigw-1{1'b0}}};
// else // it was positive
// x6 <= {1'b0, {sigw-1{1'b1}}};
// end else
x6 <= x5;
if( x5 > max_pos) x6 <= max_pos;
if( x5 < max_neg) x6 <= max_neg;
step6 <= step5;
// VI: close the loop
x1 <= x6;
step1 <= step6;
end
endmodule // jt10_adpcm
endmodule // jt10_adpcm

4
common/Sound/JT12/hdl/adpcm/jt10_adpcm_acc.v
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@@ -33,7 +33,7 @@ module jt10_adpcm_acc(
input en_sum,
input signed [15:0] pcm_in, // 18.5 kHz
output signed [15:0] pcm_out // 55.5 kHz
output reg signed [15:0] pcm_out // 55.5 kHz
);
wire signed [17:0] pcm_in_long = en_sum ? { {2{pcm_in[15]}}, pcm_in } : 18'd0;
@@ -62,7 +62,7 @@ always @(posedge clk or negedge rst_n)
last <= 18'd0;
end else if(cen) begin
if( match )
acc <= en_ch[0] ? pcm_in_long : ( pcm_in_long + acc );
acc <= cur_ch[0] ? pcm_in_long : ( pcm_in_long + acc );
if( adv ) begin
// step = diff * (1/4+1/16+1/64+1/128)
step <= { {2{step_full[22]}}, step_full[22:7] }; // >>>7;

25
common/Sound/JT12/hdl/adpcm/jt10_adpcm_cnt.v
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@@ -60,6 +60,7 @@ reg [5:0] done_sr, zero;
reg roe_n1, decon1;
reg clr1, clr2, clr3, clr4, clr5, clr6;
reg skip1, skip2, skip3, skip4, skip5, skip6;
// All outputs from stage 1
assign addr_out = addr1[20:1];
@@ -69,7 +70,8 @@ assign roe_n = roe_n1;
assign clr = clr1;
assign decon = decon1;
wire active5 = { cur_ch[1:0], cur_ch[5:2] } == en_ch;
// Two cycles early: 0 0 1 1 2 2 3 3 4 4 5 5
wire active5 = (en_ch[1] && cur_ch[4]) || (en_ch[2] && cur_ch[5]) || (en_ch[2] && cur_ch[0]) || (en_ch[3] && cur_ch[1]) || (en_ch[4] && cur_ch[2]) || (en_ch[5] && cur_ch[3]);//{ cur_ch[3:0], cur_ch[5:4] } == en_ch;
wire sumup5 = on5 && !done5 && active5;
reg sumup6;
@@ -103,8 +105,7 @@ wire [11:0] addr1_cmp = addr1[20:9];
assign start_top = {bank1, start1};
assign end_top = {bank1, end1};
reg [5:0] cur_ch, addr_ch_dec;
reg [5:0] en_ch;
reg [5:0] addr_ch_dec;
always @(*)
case(addr_ch)
@@ -128,13 +129,16 @@ always @(posedge clk or negedge rst_n)
start4 <= 'd0; start5 <= 'd0; start6 <= 'd0;
end1 <= 'd0; end2 <= 'd0; end3 <= 'd0;
end4 <= 'd0; end5 <= 'd0; end6 <= 'd0;
skip1 <= 'd0; skip2 <= 'd0; skip3 <= 'd0;
skip4 <= 'd0; skip5 <= 'd0; skip6 <= 'd0;
end else if( cen ) begin
addr2 <= addr1;
on2 <= aoff ? 1'b0 : (aon | on1);
clr2 <= aoff || (aon && !on1); // Each time a A-ON is sent the address counter restarts
on2 <= aoff ? 1'b0 : (aon | (on1 && ~done1));
clr2 <= aoff || aon || done1; // Each time a A-ON is sent the address counter restarts
start2 <= (up_start && up1) ? addr_in[11:0] : start1;
end2 <= (up_end && up1) ? addr_in[11:0] : end1;
bank2 <= ((up_end | up_start) && up1) ? addr_in[15:12] : bank1;
bank2 <= (up_start && up1) ? addr_in[15:12] : bank1;
skip2 <= skip1;
addr3 <= addr2; // clr2 ? {start2,9'd0} : addr2;
on3 <= on2;
@@ -142,6 +146,7 @@ always @(posedge clk or negedge rst_n)
start3 <= start2;
end3 <= end2;
bank3 <= bank2;
skip3 <= skip2;
addr4 <= addr3;
on4 <= on3;
@@ -149,14 +154,16 @@ always @(posedge clk or negedge rst_n)
start4 <= start3;
end4 <= end3;
bank4 <= bank3;
skip4 <= skip3;
addr5 <= addr4;
on5 <= on4;
clr5 <= clr4;
done5 <= addr4[20:9] == end4; // && addr4[8:0]==~9'b0;
done5 <= addr4[20:9] == end4 && addr4[8:0]==~9'b0 && ~(clr4 && on4);
start5 <= start4;
end5 <= end4;
bank5 <= bank4;
skip5 <= skip4;
// V
addr6 <= addr5;
on6 <= on5;
@@ -166,8 +173,9 @@ always @(posedge clk or negedge rst_n)
end6 <= end5;
bank6 <= bank5;
sumup6 <= sumup5;
skip6 <= skip5;
addr1 <= clr6 ? {start6,9'd0} : (sumup6 ? addr6+21'd1 :addr6);
addr1 <= (clr6 && on6) ? {start6,9'd0} : (sumup6 && ~skip6 ? addr6+21'd1 :addr6);
on1 <= on6;
done1 <= done6;
start1 <= start6;
@@ -176,6 +184,7 @@ always @(posedge clk or negedge rst_n)
decon1 <= sumup6;
bank1 <= bank6;
clr1 <= clr6;
skip1 <= (clr6 && on6) ? 1'b1 : sumup6 ? 1'b0 : skip6;
end
endmodule // jt10_adpcm_cnt

2
common/Sound/JT12/hdl/adpcm/jt10_adpcm_dbrom.v
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@@ -24,7 +24,7 @@
module jt10_adpcm_dbrom(
input clk, // CPU clock
input [5:0] db,
output [8:0] lin
output reg [8:0] lin
);
reg [8:0] mem[0:63];

4
common/Sound/JT12/hdl/adpcm/jt10_adpcm_div.v
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@@ -44,8 +44,8 @@ always @(posedge clk or negedge rst_n)
cycle <= 'd0;
end else if(cen) begin
if( start ) begin
cycle <= {dw{1'd1}};
r <= 'd0;
cycle <= ~16'd0;
r <= 16'd0;
d <= a;
end else if(cycle[0]) begin
cycle <= { 1'b0, cycle[dw-1:1] };

13
common/Sound/JT12/hdl/adpcm/jt10_adpcm_drvA.v
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@@ -28,7 +28,7 @@ module jt10_adpcm_drvA(
output [19:0] addr, // real hardware has 10 pins multiplexed through RMPX pin
output [3:0] bank,
output reg roe_n, // ADPCM-A ROM output enable
output roe_n, // ADPCM-A ROM output enable
// Control Registers
input [5:0] atl, // ADPCM Total Level
@@ -49,8 +49,9 @@ module jt10_adpcm_drvA(
output [5:0] flags,
input [5:0] clr_flags,
output reg signed [15:0] pcm55_l,
output reg signed [15:0] pcm55_r
output signed [15:0] pcm55_l,
output signed [15:0] pcm55_r,
input [5:0] ch_enable
);
/* verilator tracing_on */
@@ -89,7 +90,7 @@ end
reg match; // high when cur_ch==en_ch, but calculated one clock cycle ahead
// so it can be latched
wire [5:0] cur_next = { cur_ch[4:0], cur_ch[5] };
wire [5:0] en_next = {en_ch[4:0], en_ch[5] };
wire [5:0] en_next = { en_ch[0], en_ch[5:1] };
always @(posedge clk or negedge rst_n)
if( !rst_n ) begin
@@ -190,7 +191,7 @@ jt10_adpcm_acc u_acc_left(
.en_ch ( en_ch ),
.match ( match ),
// left/right enable
.en_sum ( lr[1] ),
.en_sum ( lr[1] && (ch_enable & cur_ch) ),
.pcm_in ( pcm_att ), // 18.5 kHz
.pcm_out( pre_pcm55_l ) // 55.5 kHz
@@ -205,7 +206,7 @@ jt10_adpcm_acc u_acc_right(
.en_ch ( en_ch ),
.match ( match ),
// left/right enable
.en_sum ( lr[0] ),
.en_sum ( lr[0] && (ch_enable & cur_ch) ),
.pcm_in ( pcm_att ), // 18.5 kHz
.pcm_out( pre_pcm55_r ) // 55.5 kHz

17
common/Sound/JT12/hdl/adpcm/jt10_adpcm_drvB.v
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@@ -28,6 +28,7 @@ module jt10_adpcm_drvB(
input acmd_on_b, // Control - Process start, Key On
input acmd_rep_b, // Control - Repeat
input acmd_rst_b, // Control - Reset
input acmd_up_b, // Control - New command received
input [ 1:0] alr_b, // Left / Right
input [15:0] astart_b, // Start address
input [15:0] aend_b, // End address
@@ -38,7 +39,7 @@ module jt10_adpcm_drvB(
// memory
output [23:0] addr,
input [ 7:0] data,
output roe_n,
output reg roe_n,
output reg signed [15:0] pcm55_l,
output reg signed [15:0] pcm55_r
@@ -46,6 +47,8 @@ module jt10_adpcm_drvB(
wire nibble_sel;
wire adv; // advance to next reading
wire clr_dec;
wire chon;
// `ifdef SIMULATION
// real fsample;
@@ -57,13 +60,14 @@ wire adv; // advance to next reading
// end
// `endif
always @(posedge clk) roe_n <= ~adv;
always @(posedge clk) roe_n <= ~(adv & cen55);
jt10_adpcmb_cnt u_cnt(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen55 ),
.delta_n ( adeltan_b ),
.acmd_up_b ( acmd_up_b ),
.clr ( acmd_rst_b ),
.on ( acmd_on_b ),
.astart ( astart_b ),
@@ -72,8 +76,10 @@ jt10_adpcmb_cnt u_cnt(
.addr ( addr ),
.nibble_sel ( nibble_sel ),
// Flag control
.chon ( chon ),
.clr_flag ( clr_flag ),
.flag ( flag ),
.clr_dec ( clr_dec ),
.adv ( adv )
);
@@ -89,7 +95,8 @@ jt10_adpcmb u_decoder(
.cen ( cen ),
.adv ( adv & cen55 ),
.data ( din ),
.chon ( acmd_on_b ),
.chon ( chon ),
.clr ( clr_dec ),
.pcm ( pcmdec )
);
@@ -98,7 +105,7 @@ jt10_adpcmb_interpol u_interpol(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.cen55 ( cen55 ),
.cen55 ( cen55 && chon ),
.adv ( adv ),
.pcmdec ( pcmdec ),
.pcmout ( pcminter )
@@ -121,4 +128,4 @@ always @(posedge clk) if(cen55) begin
pcm55_r <= alr_b[0] ? pcmgain : 16'd0;
end
endmodule // jt10_adpcm_drvB
endmodule // jt10_adpcm_drvB

10
common/Sound/JT12/hdl/adpcm/jt10_adpcm_gain.v
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@@ -50,7 +50,7 @@ always @(*)
default: up_ch_dec = 6'd0;
endcase
wire [5:0] en_ch2 = { en_ch[4:0], en_ch[5] }; // shift the bits to fit in the pipeline slot correctly
//wire [5:0] en_ch2 = { en_ch[4:0], en_ch[5] }; // shift the bits to fit in the pipeline slot correctly
reg [6:0] db5;
always @(*)
@@ -91,7 +91,7 @@ always @(posedge clk or negedge rst_n)
lracl4 <= lracl3;
// IV: new data is accepted here
lracl5 <= lracl4;
db5 <= { 1'b0, ~lracl4[5:0] } + {1'b0, ~atl};
db5 <= { 2'b0, ~lracl4[4:0] } + {1'b0, ~atl};
// V
lracl6 <= lracl5;
lin6 <= lin_5b;
@@ -147,7 +147,7 @@ always @(posedge clk or negedge rst_n)
// III, shift by 0 or 1
if( shcnt_mod3 ) begin
pcm4 <= pcm3>>>1;
shcnt4 <= shcnt3-1;
shcnt4 <= shcnt3-1'd1;
end else begin
pcm4 <= pcm3;
shcnt4 <= shcnt3;
@@ -155,7 +155,7 @@ always @(posedge clk or negedge rst_n)
// IV, shift by 0 or 1
if( shcnt_mod4 ) begin
pcm5 <= pcm4>>>1;
shcnt5 <= shcnt4-1;
shcnt5 <= shcnt4-1'd1;
end else begin
pcm5 <= pcm4;
shcnt5 <= shcnt4;
@@ -163,7 +163,7 @@ always @(posedge clk or negedge rst_n)
// V, shift by 0 or 1
if( shcnt_mod5 ) begin
pcm6 <= pcm5>>>1;
shcnt6 <= shcnt5-1;
shcnt6 <= shcnt5-1'd1;
end else begin
pcm6 <= pcm5;
shcnt6 <= shcnt5;

202
common/Sound/JT12/hdl/adpcm/jt10_adpcma_lut.v
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@@ -1,6 +1,6 @@
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
@@ -19,6 +19,8 @@
Date: 21-03-2019
*/
//altera message_off 10030
// ADPCM-A uses a LUT because it is very sensitive to rounding
// it looks like the original algorithm also used a table
@@ -33,107 +35,107 @@ module jt10_adpcma_lut(
reg [11:0] lut[0:391];
initial begin
lut[9'o00_0] = 12'd0002; lut[9'o00_1] = 12'd0006; lut[9'o00_2] = 12'd0012; lut[9'o00_3] = 12'd0016;
lut[9'o00_4] = 12'd0022; lut[9'o00_5] = 12'd0026; lut[9'o00_6] = 12'd0032; lut[9'o00_7] = 12'd0036;
lut[9'o01_0] = 12'd0002; lut[9'o01_1] = 12'd0006; lut[9'o01_2] = 12'd0012; lut[9'o01_3] = 12'd0016;
lut[9'o01_4] = 12'd0023; lut[9'o01_5] = 12'd0027; lut[9'o01_6] = 12'd0033; lut[9'o01_7] = 12'd0037;
lut[9'o02_0] = 12'd0002; lut[9'o02_1] = 12'd0007; lut[9'o02_2] = 12'd0013; lut[9'o02_3] = 12'd0020;
lut[9'o02_4] = 12'd0025; lut[9'o02_5] = 12'd0032; lut[9'o02_6] = 12'd0036; lut[9'o02_7] = 12'd0043;
lut[9'o03_0] = 12'd0002; lut[9'o03_1] = 12'd0007; lut[9'o03_2] = 12'd0015; lut[9'o03_3] = 12'd0022;
lut[9'o03_4] = 12'd0027; lut[9'o03_5] = 12'd0034; lut[9'o03_6] = 12'd0042; lut[9'o03_7] = 12'd0047;
lut[9'o04_0] = 12'd0002; lut[9'o04_1] = 12'd0010; lut[9'o04_2] = 12'd0016; lut[9'o04_3] = 12'd0024;
lut[9'o04_4] = 12'd0031; lut[9'o04_5] = 12'd0037; lut[9'o04_6] = 12'd0045; lut[9'o04_7] = 12'd0053;
lut[9'o05_0] = 12'd0003; lut[9'o05_1] = 12'd0011; lut[9'o05_2] = 12'd0017; lut[9'o05_3] = 12'd0025;
lut[9'o05_4] = 12'd0034; lut[9'o05_5] = 12'd0042; lut[9'o05_6] = 12'd0050; lut[9'o05_7] = 12'd0056;
lut[9'o06_0] = 12'd0003; lut[9'o06_1] = 12'd0012; lut[9'o06_2] = 12'd0021; lut[9'o06_3] = 12'd0030;
lut[9'o06_4] = 12'd0037; lut[9'o06_5] = 12'd0046; lut[9'o06_6] = 12'd0055; lut[9'o06_7] = 12'd0064;
lut[9'o07_0] = 12'd0003; lut[9'o07_1] = 12'd0013; lut[9'o07_2] = 12'd0023; lut[9'o07_3] = 12'd0033;
lut[9'o07_4] = 12'd0042; lut[9'o07_5] = 12'd0052; lut[9'o07_6] = 12'd0062; lut[9'o07_7] = 12'd0072;
lut[9'o10_0] = 12'd0004; lut[9'o10_1] = 12'd0014; lut[9'o10_2] = 12'd0025; lut[9'o10_3] = 12'd0035;
lut[9'o10_4] = 12'd0046; lut[9'o10_5] = 12'd0056; lut[9'o10_6] = 12'd0067; lut[9'o10_7] = 12'd0077;
lut[9'o11_0] = 12'd0004; lut[9'o11_1] = 12'd0015; lut[9'o11_2] = 12'd0027; lut[9'o11_3] = 12'd0040;
lut[9'o11_4] = 12'd0051; lut[9'o11_5] = 12'd0062; lut[9'o11_6] = 12'd0074; lut[9'o11_7] = 12'd0105;
lut[9'o12_0] = 12'd0005; lut[9'o12_1] = 12'd0017; lut[9'o12_2] = 12'd0031; lut[9'o12_3] = 12'd0043;
lut[9'o12_4] = 12'd0056; lut[9'o12_5] = 12'd0070; lut[9'o12_6] = 12'd0102; lut[9'o12_7] = 12'd0114;
lut[9'o13_0] = 12'd0005; lut[9'o13_1] = 12'd0020; lut[9'o13_2] = 12'd0034; lut[9'o13_3] = 12'd0047;
lut[9'o13_4] = 12'd0062; lut[9'o13_5] = 12'd0075; lut[9'o13_6] = 12'd0111; lut[9'o13_7] = 12'd0124;
lut[9'o14_0] = 12'd0006; lut[9'o14_1] = 12'd0022; lut[9'o14_2] = 12'd0037; lut[9'o14_3] = 12'd0053;
lut[9'o14_4] = 12'd0070; lut[9'o14_5] = 12'd0104; lut[9'o14_6] = 12'd0121; lut[9'o14_7] = 12'd0135;
lut[9'o15_0] = 12'd0006; lut[9'o15_1] = 12'd0024; lut[9'o15_2] = 12'd0042; lut[9'o15_3] = 12'd0060;
lut[9'o15_4] = 12'd0075; lut[9'o15_5] = 12'd0113; lut[9'o15_6] = 12'd0131; lut[9'o15_7] = 12'd0147;
lut[9'o16_0] = 12'd0007; lut[9'o16_1] = 12'd0026; lut[9'o16_2] = 12'd0045; lut[9'o16_3] = 12'd0064;
lut[9'o16_4] = 12'd0103; lut[9'o16_5] = 12'd0122; lut[9'o16_6] = 12'd0141; lut[9'o16_7] = 12'd0160;
lut[9'o17_0] = 12'd0010; lut[9'o17_1] = 12'd0030; lut[9'o17_2] = 12'd0051; lut[9'o17_3] = 12'd0071;
lut[9'o17_4] = 12'd0112; lut[9'o17_5] = 12'd0132; lut[9'o17_6] = 12'd0153; lut[9'o17_7] = 12'd0173;
lut[9'o20_0] = 12'd0011; lut[9'o20_1] = 12'd0033; lut[9'o20_2] = 12'd0055; lut[9'o20_3] = 12'd0077;
lut[9'o20_4] = 12'd0122; lut[9'o20_5] = 12'd0144; lut[9'o20_6] = 12'd0166; lut[9'o20_7] = 12'd0210;
lut[9'o21_0] = 12'd0012; lut[9'o21_1] = 12'd0036; lut[9'o21_2] = 12'd0062; lut[9'o21_3] = 12'd0106;
lut[9'o21_4] = 12'd0132; lut[9'o21_5] = 12'd0156; lut[9'o21_6] = 12'd0202; lut[9'o21_7] = 12'd0226;
lut[9'o22_0] = 12'd0013; lut[9'o22_1] = 12'd0041; lut[9'o22_2] = 12'd0067; lut[9'o22_3] = 12'd0115;
lut[9'o22_4] = 12'd0143; lut[9'o22_5] = 12'd0171; lut[9'o22_6] = 12'd0217; lut[9'o22_7] = 12'd0245;
lut[9'o23_0] = 12'd0014; lut[9'o23_1] = 12'd0044; lut[9'o23_2] = 12'd0074; lut[9'o23_3] = 12'd0124;
lut[9'o23_4] = 12'd0155; lut[9'o23_5] = 12'd0205; lut[9'o23_6] = 12'd0235; lut[9'o23_7] = 12'd0265;
lut[9'o24_0] = 12'd0015; lut[9'o24_1] = 12'd0050; lut[9'o24_2] = 12'd0102; lut[9'o24_3] = 12'd0135;
lut[9'o24_4] = 12'd0170; lut[9'o24_5] = 12'd0223; lut[9'o24_6] = 12'd0255; lut[9'o24_7] = 12'd0310;
lut[9'o25_0] = 12'd0016; lut[9'o25_1] = 12'd0054; lut[9'o25_2] = 12'd0111; lut[9'o25_3] = 12'd0147;
lut[9'o25_4] = 12'd0204; lut[9'o25_5] = 12'd0242; lut[9'o25_6] = 12'd0277; lut[9'o25_7] = 12'd0335;
lut[9'o26_0] = 12'd0020; lut[9'o26_1] = 12'd0060; lut[9'o26_2] = 12'd0121; lut[9'o26_3] = 12'd0161;
lut[9'o26_4] = 12'd0222; lut[9'o26_5] = 12'd0262; lut[9'o26_6] = 12'd0323; lut[9'o26_7] = 12'd0363;
lut[9'o27_0] = 12'd0021; lut[9'o27_1] = 12'd0065; lut[9'o27_2] = 12'd0131; lut[9'o27_3] = 12'd0175;
lut[9'o27_4] = 12'd0240; lut[9'o27_5] = 12'd0304; lut[9'o27_6] = 12'd0350; lut[9'o27_7] = 12'd0414;
lut[9'o30_0] = 12'd0023; lut[9'o30_1] = 12'd0072; lut[9'o30_2] = 12'd0142; lut[9'o30_3] = 12'd0211;
lut[9'o30_4] = 12'd0260; lut[9'o30_5] = 12'd0327; lut[9'o30_6] = 12'd0377; lut[9'o30_7] = 12'd0446;
lut[9'o31_0] = 12'd0025; lut[9'o31_1] = 12'd0100; lut[9'o31_2] = 12'd0154; lut[9'o31_3] = 12'd0227;
lut[9'o31_4] = 12'd0302; lut[9'o31_5] = 12'd0355; lut[9'o31_6] = 12'd0431; lut[9'o31_7] = 12'd0504;
lut[9'o32_0] = 12'd0027; lut[9'o32_1] = 12'd0107; lut[9'o32_2] = 12'd0166; lut[9'o32_3] = 12'd0246;
lut[9'o32_4] = 12'd0325; lut[9'o32_5] = 12'd0405; lut[9'o32_6] = 12'd0464; lut[9'o32_7] = 12'd0544;
lut[9'o33_0] = 12'd0032; lut[9'o33_1] = 12'd0116; lut[9'o33_2] = 12'd0202; lut[9'o33_3] = 12'd0266;
lut[9'o33_4] = 12'd0353; lut[9'o33_5] = 12'd0437; lut[9'o33_6] = 12'd0523; lut[9'o33_7] = 12'd0607;
lut[9'o34_0] = 12'd0034; lut[9'o34_1] = 12'd0126; lut[9'o34_2] = 12'd0217; lut[9'o34_3] = 12'd0311;
lut[9'o34_4] = 12'd0402; lut[9'o34_5] = 12'd0474; lut[9'o34_6] = 12'd0565; lut[9'o34_7] = 12'd0657;
lut[9'o35_0] = 12'd0037; lut[9'o35_1] = 12'd0136; lut[9'o35_2] = 12'd0236; lut[9'o35_3] = 12'd0335;
lut[9'o35_4] = 12'd0434; lut[9'o35_5] = 12'd0533; lut[9'o35_6] = 12'd0633; lut[9'o35_7] = 12'd0732;
lut[9'o36_0] = 12'd0042; lut[9'o36_1] = 12'd0150; lut[9'o36_2] = 12'd0256; lut[9'o36_3] = 12'd0364;
lut[9'o36_4] = 12'd0471; lut[9'o36_5] = 12'd0577; lut[9'o36_6] = 12'd0705; lut[9'o36_7] = 12'd1013;
lut[9'o37_0] = 12'd0046; lut[9'o37_1] = 12'd0163; lut[9'o37_2] = 12'd0277; lut[9'o37_3] = 12'd0414;
lut[9'o37_4] = 12'd0531; lut[9'o37_5] = 12'd0646; lut[9'o37_6] = 12'd0762; lut[9'o37_7] = 12'd1077;
lut[9'o40_0] = 12'd0052; lut[9'o40_1] = 12'd0176; lut[9'o40_2] = 12'd0322; lut[9'o40_3] = 12'd0446;
lut[9'o40_4] = 12'd0573; lut[9'o40_5] = 12'd0717; lut[9'o40_6] = 12'd1043; lut[9'o40_7] = 12'd1167;
lut[9'o41_0] = 12'd0056; lut[9'o41_1] = 12'd0213; lut[9'o41_2] = 12'd0347; lut[9'o41_3] = 12'd0504;
lut[9'o41_4] = 12'd0641; lut[9'o41_5] = 12'd0776; lut[9'o41_6] = 12'd1132; lut[9'o41_7] = 12'd1267;
lut[9'o42_0] = 12'd0063; lut[9'o42_1] = 12'd0231; lut[9'o42_2] = 12'd0377; lut[9'o42_3] = 12'd0545;
lut[9'o42_4] = 12'd0713; lut[9'o42_5] = 12'd1061; lut[9'o42_6] = 12'd1227; lut[9'o42_7] = 12'd1375;
lut[9'o43_0] = 12'd0070; lut[9'o43_1] = 12'd0250; lut[9'o43_2] = 12'd0430; lut[9'o43_3] = 12'd0610;
lut[9'o43_4] = 12'd0771; lut[9'o43_5] = 12'd1151; lut[9'o43_6] = 12'd1331; lut[9'o43_7] = 12'd1511;
lut[9'o44_0] = 12'd0075; lut[9'o44_1] = 12'd0271; lut[9'o44_2] = 12'd0464; lut[9'o44_3] = 12'd0660;
lut[9'o44_4] = 12'd1053; lut[9'o44_5] = 12'd1247; lut[9'o44_6] = 12'd1442; lut[9'o44_7] = 12'd1636;
lut[9'o45_0] = 12'd0104; lut[9'o45_1] = 12'd0314; lut[9'o45_2] = 12'd0524; lut[9'o45_3] = 12'd0734;
lut[9'o45_4] = 12'd1144; lut[9'o45_5] = 12'd1354; lut[9'o45_6] = 12'd1564; lut[9'o45_7] = 12'd1774;
lut[9'o46_0] = 12'd0112; lut[9'o46_1] = 12'd0340; lut[9'o46_2] = 12'd0565; lut[9'o46_3] = 12'd1013;
lut[9'o46_4] = 12'd1240; lut[9'o46_5] = 12'd1466; lut[9'o46_6] = 12'd1713; lut[9'o46_7] = 12'd2141;
lut[9'o47_0] = 12'd0122; lut[9'o47_1] = 12'd0366; lut[9'o47_2] = 12'd0633; lut[9'o47_3] = 12'd1077;
lut[9'o47_4] = 12'd1344; lut[9'o47_5] = 12'd1610; lut[9'o47_6] = 12'd2055; lut[9'o47_7] = 12'd2321;
lut[9'o50_0] = 12'd0132; lut[9'o50_1] = 12'd0417; lut[9'o50_2] = 12'd0704; lut[9'o50_3] = 12'd1171;
lut[9'o50_4] = 12'd1456; lut[9'o50_5] = 12'd1743; lut[9'o50_6] = 12'd2230; lut[9'o50_7] = 12'd2515;
lut[9'o51_0] = 12'd0143; lut[9'o51_1] = 12'd0452; lut[9'o51_2] = 12'd0761; lut[9'o51_3] = 12'd1270;
lut[9'o51_4] = 12'd1577; lut[9'o51_5] = 12'd2106; lut[9'o51_6] = 12'd2415; lut[9'o51_7] = 12'd2724;
lut[9'o52_0] = 12'd0155; lut[9'o52_1] = 12'd0510; lut[9'o52_2] = 12'd1043; lut[9'o52_3] = 12'd1376;
lut[9'o52_4] = 12'd1731; lut[9'o52_5] = 12'd2264; lut[9'o52_6] = 12'd2617; lut[9'o52_7] = 12'd3152;
lut[9'o53_0] = 12'd0170; lut[9'o53_1] = 12'd0551; lut[9'o53_2] = 12'd1131; lut[9'o53_3] = 12'd1512;
lut[9'o53_4] = 12'd2073; lut[9'o53_5] = 12'd2454; lut[9'o53_6] = 12'd3034; lut[9'o53_7] = 12'd3415;
lut[9'o54_0] = 12'd0204; lut[9'o54_1] = 12'd0615; lut[9'o54_2] = 12'd1226; lut[9'o54_3] = 12'd1637;
lut[9'o54_4] = 12'd2250; lut[9'o54_5] = 12'd2661; lut[9'o54_6] = 12'd3272; lut[9'o54_7] = 12'd3703;
lut[9'o55_0] = 12'd0221; lut[9'o55_1] = 12'd0665; lut[9'o55_2] = 12'd1330; lut[9'o55_3] = 12'd1774;
lut[9'o55_4] = 12'd2437; lut[9'o55_5] = 12'd3103; lut[9'o55_6] = 12'd3546; lut[9'o55_7] = 12'd3777;
lut[9'o56_0] = 12'd0240; lut[9'o56_1] = 12'd0740; lut[9'o56_2] = 12'd1441; lut[9'o56_3] = 12'd2141;
lut[9'o56_4] = 12'd2642; lut[9'o56_5] = 12'd3342; lut[9'o56_6] = 12'd3777; lut[9'o56_7] = 12'd3777;
lut[9'o57_0] = 12'd0260; lut[9'o57_1] = 12'd1021; lut[9'o57_2] = 12'd1561; lut[9'o57_3] = 12'd2322;
lut[9'o57_4] = 12'd3063; lut[9'o57_5] = 12'd3624; lut[9'o57_6] = 12'd3777; lut[9'o57_7] = 12'd3777;
lut[9'o60_0] = 12'd0302; lut[9'o60_1] = 12'd1106; lut[9'o60_2] = 12'd1712; lut[9'o60_3] = 12'd2516;
lut[9'o60_4] = 12'd3322; lut[9'o60_5] = 12'd3777; lut[9'o60_6] = 12'd3777; lut[9'o60_7] = 12'd3777;
lut[9'o00_0] = 12'o0002; lut[9'o00_1] = 12'o0006; lut[9'o00_2] = 12'o0012; lut[9'o00_3] = 12'o0016;
lut[9'o00_4] = 12'o0022; lut[9'o00_5] = 12'o0026; lut[9'o00_6] = 12'o0032; lut[9'o00_7] = 12'o0036;
lut[9'o01_0] = 12'o0002; lut[9'o01_1] = 12'o0006; lut[9'o01_2] = 12'o0012; lut[9'o01_3] = 12'o0016;
lut[9'o01_4] = 12'o0023; lut[9'o01_5] = 12'o0027; lut[9'o01_6] = 12'o0033; lut[9'o01_7] = 12'o0037;
lut[9'o02_0] = 12'o0002; lut[9'o02_1] = 12'o0007; lut[9'o02_2] = 12'o0013; lut[9'o02_3] = 12'o0020;
lut[9'o02_4] = 12'o0025; lut[9'o02_5] = 12'o0032; lut[9'o02_6] = 12'o0036; lut[9'o02_7] = 12'o0043;
lut[9'o03_0] = 12'o0002; lut[9'o03_1] = 12'o0007; lut[9'o03_2] = 12'o0015; lut[9'o03_3] = 12'o0022;
lut[9'o03_4] = 12'o0027; lut[9'o03_5] = 12'o0034; lut[9'o03_6] = 12'o0042; lut[9'o03_7] = 12'o0047;
lut[9'o04_0] = 12'o0002; lut[9'o04_1] = 12'o0010; lut[9'o04_2] = 12'o0016; lut[9'o04_3] = 12'o0024;
lut[9'o04_4] = 12'o0031; lut[9'o04_5] = 12'o0037; lut[9'o04_6] = 12'o0045; lut[9'o04_7] = 12'o0053;
lut[9'o05_0] = 12'o0003; lut[9'o05_1] = 12'o0011; lut[9'o05_2] = 12'o0017; lut[9'o05_3] = 12'o0025;
lut[9'o05_4] = 12'o0034; lut[9'o05_5] = 12'o0042; lut[9'o05_6] = 12'o0050; lut[9'o05_7] = 12'o0056;
lut[9'o06_0] = 12'o0003; lut[9'o06_1] = 12'o0012; lut[9'o06_2] = 12'o0021; lut[9'o06_3] = 12'o0030;
lut[9'o06_4] = 12'o0037; lut[9'o06_5] = 12'o0046; lut[9'o06_6] = 12'o0055; lut[9'o06_7] = 12'o0064;
lut[9'o07_0] = 12'o0003; lut[9'o07_1] = 12'o0013; lut[9'o07_2] = 12'o0023; lut[9'o07_3] = 12'o0033;
lut[9'o07_4] = 12'o0042; lut[9'o07_5] = 12'o0052; lut[9'o07_6] = 12'o0062; lut[9'o07_7] = 12'o0072;
lut[9'o10_0] = 12'o0004; lut[9'o10_1] = 12'o0014; lut[9'o10_2] = 12'o0025; lut[9'o10_3] = 12'o0035;
lut[9'o10_4] = 12'o0046; lut[9'o10_5] = 12'o0056; lut[9'o10_6] = 12'o0067; lut[9'o10_7] = 12'o0077;
lut[9'o11_0] = 12'o0004; lut[9'o11_1] = 12'o0015; lut[9'o11_2] = 12'o0027; lut[9'o11_3] = 12'o0040;
lut[9'o11_4] = 12'o0051; lut[9'o11_5] = 12'o0062; lut[9'o11_6] = 12'o0074; lut[9'o11_7] = 12'o0105;
lut[9'o12_0] = 12'o0005; lut[9'o12_1] = 12'o0017; lut[9'o12_2] = 12'o0031; lut[9'o12_3] = 12'o0043;
lut[9'o12_4] = 12'o0056; lut[9'o12_5] = 12'o0070; lut[9'o12_6] = 12'o0102; lut[9'o12_7] = 12'o0114;
lut[9'o13_0] = 12'o0005; lut[9'o13_1] = 12'o0020; lut[9'o13_2] = 12'o0034; lut[9'o13_3] = 12'o0047;
lut[9'o13_4] = 12'o0062; lut[9'o13_5] = 12'o0075; lut[9'o13_6] = 12'o0111; lut[9'o13_7] = 12'o0124;
lut[9'o14_0] = 12'o0006; lut[9'o14_1] = 12'o0022; lut[9'o14_2] = 12'o0037; lut[9'o14_3] = 12'o0053;
lut[9'o14_4] = 12'o0070; lut[9'o14_5] = 12'o0104; lut[9'o14_6] = 12'o0121; lut[9'o14_7] = 12'o0135;
lut[9'o15_0] = 12'o0006; lut[9'o15_1] = 12'o0024; lut[9'o15_2] = 12'o0042; lut[9'o15_3] = 12'o0060;
lut[9'o15_4] = 12'o0075; lut[9'o15_5] = 12'o0113; lut[9'o15_6] = 12'o0131; lut[9'o15_7] = 12'o0147;
lut[9'o16_0] = 12'o0007; lut[9'o16_1] = 12'o0026; lut[9'o16_2] = 12'o0045; lut[9'o16_3] = 12'o0064;
lut[9'o16_4] = 12'o0103; lut[9'o16_5] = 12'o0122; lut[9'o16_6] = 12'o0141; lut[9'o16_7] = 12'o0160;
lut[9'o17_0] = 12'o0010; lut[9'o17_1] = 12'o0030; lut[9'o17_2] = 12'o0051; lut[9'o17_3] = 12'o0071;
lut[9'o17_4] = 12'o0112; lut[9'o17_5] = 12'o0132; lut[9'o17_6] = 12'o0153; lut[9'o17_7] = 12'o0173;
lut[9'o20_0] = 12'o0011; lut[9'o20_1] = 12'o0033; lut[9'o20_2] = 12'o0055; lut[9'o20_3] = 12'o0077;
lut[9'o20_4] = 12'o0122; lut[9'o20_5] = 12'o0144; lut[9'o20_6] = 12'o0166; lut[9'o20_7] = 12'o0210;
lut[9'o21_0] = 12'o0012; lut[9'o21_1] = 12'o0036; lut[9'o21_2] = 12'o0062; lut[9'o21_3] = 12'o0106;
lut[9'o21_4] = 12'o0132; lut[9'o21_5] = 12'o0156; lut[9'o21_6] = 12'o0202; lut[9'o21_7] = 12'o0226;
lut[9'o22_0] = 12'o0013; lut[9'o22_1] = 12'o0041; lut[9'o22_2] = 12'o0067; lut[9'o22_3] = 12'o0115;
lut[9'o22_4] = 12'o0143; lut[9'o22_5] = 12'o0171; lut[9'o22_6] = 12'o0217; lut[9'o22_7] = 12'o0245;
lut[9'o23_0] = 12'o0014; lut[9'o23_1] = 12'o0044; lut[9'o23_2] = 12'o0074; lut[9'o23_3] = 12'o0124;
lut[9'o23_4] = 12'o0155; lut[9'o23_5] = 12'o0205; lut[9'o23_6] = 12'o0235; lut[9'o23_7] = 12'o0265;
lut[9'o24_0] = 12'o0015; lut[9'o24_1] = 12'o0050; lut[9'o24_2] = 12'o0102; lut[9'o24_3] = 12'o0135;
lut[9'o24_4] = 12'o0170; lut[9'o24_5] = 12'o0223; lut[9'o24_6] = 12'o0255; lut[9'o24_7] = 12'o0310;
lut[9'o25_0] = 12'o0016; lut[9'o25_1] = 12'o0054; lut[9'o25_2] = 12'o0111; lut[9'o25_3] = 12'o0147;
lut[9'o25_4] = 12'o0204; lut[9'o25_5] = 12'o0242; lut[9'o25_6] = 12'o0277; lut[9'o25_7] = 12'o0335;
lut[9'o26_0] = 12'o0020; lut[9'o26_1] = 12'o0060; lut[9'o26_2] = 12'o0121; lut[9'o26_3] = 12'o0161;
lut[9'o26_4] = 12'o0222; lut[9'o26_5] = 12'o0262; lut[9'o26_6] = 12'o0323; lut[9'o26_7] = 12'o0363;
lut[9'o27_0] = 12'o0021; lut[9'o27_1] = 12'o0065; lut[9'o27_2] = 12'o0131; lut[9'o27_3] = 12'o0175;
lut[9'o27_4] = 12'o0240; lut[9'o27_5] = 12'o0304; lut[9'o27_6] = 12'o0350; lut[9'o27_7] = 12'o0414;
lut[9'o30_0] = 12'o0023; lut[9'o30_1] = 12'o0072; lut[9'o30_2] = 12'o0142; lut[9'o30_3] = 12'o0211;
lut[9'o30_4] = 12'o0260; lut[9'o30_5] = 12'o0327; lut[9'o30_6] = 12'o0377; lut[9'o30_7] = 12'o0446;
lut[9'o31_0] = 12'o0025; lut[9'o31_1] = 12'o0100; lut[9'o31_2] = 12'o0154; lut[9'o31_3] = 12'o0227;
lut[9'o31_4] = 12'o0302; lut[9'o31_5] = 12'o0355; lut[9'o31_6] = 12'o0431; lut[9'o31_7] = 12'o0504;
lut[9'o32_0] = 12'o0027; lut[9'o32_1] = 12'o0107; lut[9'o32_2] = 12'o0166; lut[9'o32_3] = 12'o0246;
lut[9'o32_4] = 12'o0325; lut[9'o32_5] = 12'o0405; lut[9'o32_6] = 12'o0464; lut[9'o32_7] = 12'o0544;
lut[9'o33_0] = 12'o0032; lut[9'o33_1] = 12'o0116; lut[9'o33_2] = 12'o0202; lut[9'o33_3] = 12'o0266;
lut[9'o33_4] = 12'o0353; lut[9'o33_5] = 12'o0437; lut[9'o33_6] = 12'o0523; lut[9'o33_7] = 12'o0607;
lut[9'o34_0] = 12'o0034; lut[9'o34_1] = 12'o0126; lut[9'o34_2] = 12'o0217; lut[9'o34_3] = 12'o0311;
lut[9'o34_4] = 12'o0402; lut[9'o34_5] = 12'o0474; lut[9'o34_6] = 12'o0565; lut[9'o34_7] = 12'o0657;
lut[9'o35_0] = 12'o0037; lut[9'o35_1] = 12'o0136; lut[9'o35_2] = 12'o0236; lut[9'o35_3] = 12'o0335;
lut[9'o35_4] = 12'o0434; lut[9'o35_5] = 12'o0533; lut[9'o35_6] = 12'o0633; lut[9'o35_7] = 12'o0732;
lut[9'o36_0] = 12'o0042; lut[9'o36_1] = 12'o0150; lut[9'o36_2] = 12'o0256; lut[9'o36_3] = 12'o0364;
lut[9'o36_4] = 12'o0471; lut[9'o36_5] = 12'o0577; lut[9'o36_6] = 12'o0705; lut[9'o36_7] = 12'o1013;
lut[9'o37_0] = 12'o0046; lut[9'o37_1] = 12'o0163; lut[9'o37_2] = 12'o0277; lut[9'o37_3] = 12'o0414;
lut[9'o37_4] = 12'o0531; lut[9'o37_5] = 12'o0646; lut[9'o37_6] = 12'o0762; lut[9'o37_7] = 12'o1077;
lut[9'o40_0] = 12'o0052; lut[9'o40_1] = 12'o0176; lut[9'o40_2] = 12'o0322; lut[9'o40_3] = 12'o0446;
lut[9'o40_4] = 12'o0573; lut[9'o40_5] = 12'o0717; lut[9'o40_6] = 12'o1043; lut[9'o40_7] = 12'o1167;
lut[9'o41_0] = 12'o0056; lut[9'o41_1] = 12'o0213; lut[9'o41_2] = 12'o0347; lut[9'o41_3] = 12'o0504;
lut[9'o41_4] = 12'o0641; lut[9'o41_5] = 12'o0776; lut[9'o41_6] = 12'o1132; lut[9'o41_7] = 12'o1267;
lut[9'o42_0] = 12'o0063; lut[9'o42_1] = 12'o0231; lut[9'o42_2] = 12'o0377; lut[9'o42_3] = 12'o0545;
lut[9'o42_4] = 12'o0713; lut[9'o42_5] = 12'o1061; lut[9'o42_6] = 12'o1227; lut[9'o42_7] = 12'o1375;
lut[9'o43_0] = 12'o0070; lut[9'o43_1] = 12'o0250; lut[9'o43_2] = 12'o0430; lut[9'o43_3] = 12'o0610;
lut[9'o43_4] = 12'o0771; lut[9'o43_5] = 12'o1151; lut[9'o43_6] = 12'o1331; lut[9'o43_7] = 12'o1511;
lut[9'o44_0] = 12'o0075; lut[9'o44_1] = 12'o0271; lut[9'o44_2] = 12'o0464; lut[9'o44_3] = 12'o0660;
lut[9'o44_4] = 12'o1053; lut[9'o44_5] = 12'o1247; lut[9'o44_6] = 12'o1442; lut[9'o44_7] = 12'o1636;
lut[9'o45_0] = 12'o0104; lut[9'o45_1] = 12'o0314; lut[9'o45_2] = 12'o0524; lut[9'o45_3] = 12'o0734;
lut[9'o45_4] = 12'o1144; lut[9'o45_5] = 12'o1354; lut[9'o45_6] = 12'o1564; lut[9'o45_7] = 12'o1774;
lut[9'o46_0] = 12'o0112; lut[9'o46_1] = 12'o0340; lut[9'o46_2] = 12'o0565; lut[9'o46_3] = 12'o1013;
lut[9'o46_4] = 12'o1240; lut[9'o46_5] = 12'o1466; lut[9'o46_6] = 12'o1713; lut[9'o46_7] = 12'o2141;
lut[9'o47_0] = 12'o0122; lut[9'o47_1] = 12'o0366; lut[9'o47_2] = 12'o0633; lut[9'o47_3] = 12'o1077;
lut[9'o47_4] = 12'o1344; lut[9'o47_5] = 12'o1610; lut[9'o47_6] = 12'o2055; lut[9'o47_7] = 12'o2321;
lut[9'o50_0] = 12'o0132; lut[9'o50_1] = 12'o0417; lut[9'o50_2] = 12'o0704; lut[9'o50_3] = 12'o1171;
lut[9'o50_4] = 12'o1456; lut[9'o50_5] = 12'o1743; lut[9'o50_6] = 12'o2230; lut[9'o50_7] = 12'o2515;
lut[9'o51_0] = 12'o0143; lut[9'o51_1] = 12'o0452; lut[9'o51_2] = 12'o0761; lut[9'o51_3] = 12'o1270;
lut[9'o51_4] = 12'o1577; lut[9'o51_5] = 12'o2106; lut[9'o51_6] = 12'o2415; lut[9'o51_7] = 12'o2724;
lut[9'o52_0] = 12'o0155; lut[9'o52_1] = 12'o0510; lut[9'o52_2] = 12'o1043; lut[9'o52_3] = 12'o1376;
lut[9'o52_4] = 12'o1731; lut[9'o52_5] = 12'o2264; lut[9'o52_6] = 12'o2617; lut[9'o52_7] = 12'o3152;
lut[9'o53_0] = 12'o0170; lut[9'o53_1] = 12'o0551; lut[9'o53_2] = 12'o1131; lut[9'o53_3] = 12'o1512;
lut[9'o53_4] = 12'o2073; lut[9'o53_5] = 12'o2454; lut[9'o53_6] = 12'o3034; lut[9'o53_7] = 12'o3415;
lut[9'o54_0] = 12'o0204; lut[9'o54_1] = 12'o0615; lut[9'o54_2] = 12'o1226; lut[9'o54_3] = 12'o1637;
lut[9'o54_4] = 12'o2250; lut[9'o54_5] = 12'o2661; lut[9'o54_6] = 12'o3272; lut[9'o54_7] = 12'o3703;
lut[9'o55_0] = 12'o0221; lut[9'o55_1] = 12'o0665; lut[9'o55_2] = 12'o1330; lut[9'o55_3] = 12'o1774;// Not sure if these should clip at 11 bits or not
lut[9'o55_4] = 12'o2437; lut[9'o55_5] = 12'o3103; lut[9'o55_6] = 12'o3546; lut[9'o55_7] = 12'o4212;//12'o3777;
lut[9'o56_0] = 12'o0240; lut[9'o56_1] = 12'o0740; lut[9'o56_2] = 12'o1441; lut[9'o56_3] = 12'o2141;
lut[9'o56_4] = 12'o2642; lut[9'o56_5] = 12'o3342; lut[9'o56_6] = 12'o4043; lut[9'o56_7] = 12'o4543;//12'o3777; lut[9'o56_7] = 12'o3777;
lut[9'o57_0] = 12'o0260; lut[9'o57_1] = 12'o1021; lut[9'o57_2] = 12'o1561; lut[9'o57_3] = 12'o2322;
lut[9'o57_4] = 12'o3063; lut[9'o57_5] = 12'o3624; lut[9'o57_6] = 12'o4364; lut[9'o57_7] = 12'o5125;//12'o3777; lut[9'o57_7] = 12'o3777;
lut[9'o60_0] = 12'o0302; lut[9'o60_1] = 12'o1106; lut[9'o60_2] = 12'o1712; lut[9'o60_3] = 12'o2516;
lut[9'o60_4] = 12'o3322; lut[9'o60_5] = 12'o4126; lut[9'o60_6] = 12'o4732; lut[9'o60_7] = 12'o5536;//12'o3777; lut[9'o60_6] = 12'o3777; lut[9'o60_7] = 12'o3777;
end
always @(posedge clk or negedge rst_n)
always @(posedge clk or negedge rst_n)
if(!rst_n)
inc <= 'd0;
else if(cen)

35
common/Sound/JT12/hdl/adpcm/jt10_adpcmb.v
View File

@@ -28,6 +28,7 @@ module jt10_adpcmb(
input [3:0] data,
input chon, // high if this channel is on
input adv,
input clr,
output signed [15:0] pcm
);
@@ -64,33 +65,43 @@ end
// 666 kHz -> 18.5 kHz = 55.5/3 kHz
reg [3:0] data2;
reg sign_data;
reg sign_data2, sign_data3, sign_data4, sign_data5;
reg [3:0] adv2;
reg need_clr;
wire [3:0] data_use = clr || ~chon ? 4'd0 : data;
always @( posedge clk or negedge rst_n )
if( ! rst_n ) begin
x1 <= 'd0; step1 <= 'd127;
d2 <= 'd0; d3 <= 'd0; d4 <= 'd0;
end else if(cen) begin
need_clr <= 0;
end else begin
if( clr )
need_clr <= 1'd1;
if(cen) begin
adv2 <= {1'b0,adv2[3:1]};
// I
if( adv ) begin
d2 <= {data[2:0],1'b1};
sign_data <= data[3];
if( adv ) begin
d2 <= {data_use[2:0],1'b1};
sign_data2 <= data_use[3];
adv2[3] <= 1'b1;
end
// II multiply and obtain the offset
d3 <= { {xw-16{1'b0}}, d2l[18:3] }; // xw bits
next_step3<= step2l[22:6];
sign_data3<=sign_data2;
// III 2's complement of d3 if necessary
d4 <= sign_data ? ~d3+1 : d3;
d4 <= sign_data3 ? ~d3+1'd1 : d3;
sign_data4<=sign_data3;
// IV Advance the waveform
next_x5 <= x1+d4;
sign_data5<=sign_data4;
// V: limit or reset outputs
if( chon ) begin // update values if needed
if( adv2[0] ) begin
if( sign_data == x1[xw-1] && (x1[xw-1]!=next_x5[xw-1]) )
if( sign_data5 == x1[xw-1] && (x1[xw-1]!=next_x5[xw-1]) )
x1 <= x1[xw-1] ? limneg : limpos;
else
x1 <= next_x5;
@@ -105,8 +116,16 @@ always @( posedge clk or negedge rst_n )
end else begin
x1 <= 'd0;
step1 <= 'd127;
end
if( need_clr ) begin
x1 <= 'd0;
step1 <= 'd127;
next_step3 <= 'd127;
d2 <= 'd0; d3 <= 'd0; d4 <= 'd0;
next_x5 <= 'd0;
need_clr <= 1'd0;
end
end
end
endmodule // jt10_adpcm

48
common/Sound/JT12/hdl/adpcm/jt10_adpcmb_cnt.v
View File

@@ -30,6 +30,7 @@ module jt10_adpcmb_cnt(
input [15:0] delta_n,
input clr,
input on,
input acmd_up_b,
// Address
input [15:0] astart,
input [15:0] aend,
@@ -37,8 +38,10 @@ module jt10_adpcmb_cnt(
output reg [23:0] addr,
output reg nibble_sel,
// Flag
output reg chon,
output reg flag,
input clr_flag,
output reg clr_dec,
output reg adv
);
@@ -51,19 +54,22 @@ always @(posedge clk or negedge rst_n)
cnt <= 'd0;
adv <= 'b0;
end else if(cen) begin
if( clr ) begin
if( clr) begin
cnt <= 'd0;
adv <= 'b0;
end else begin
if( on )
{adv, cnt} <= {1'b0, cnt} + {1'b0, delta_n };
else
else begin
cnt <= 'd0;
adv <= 1'b1; // let the rest of the signal chain advance
// when channel is off so all registers go to reset values
end
end
end
reg set_flag, last_set;
reg restart;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
@@ -76,33 +82,41 @@ always @(posedge clk or negedge rst_n)
end
// Address
reg last_on;
always @(posedge clk or negedge rst_n)
if(!rst_n) begin
addr <= 'd0;
nibble_sel <= 'b0;
set_flag <= 'd0;
end else if(cen) begin
last_on <= on;
if( (on && !last_on) || clr ) begin
chon <= 'b0;
restart <= 'b0;
clr_dec <= 'b1;
end else if( !on || clr ) begin
restart <= 'd0;
chon <= 'd0;
clr_dec <= 'd1;
end else if( acmd_up_b && on ) begin
restart <= 'd1;
end else if( cen ) begin
if( restart && adv ) begin
addr <= {astart,8'd0};
nibble_sel <= 'b0;
end else if( on && adv ) begin
if( addr[23:8] < aend ) begin
restart <= 'd0;
chon <= 'd1;
clr_dec <= 'd0;
end else if( chon && adv ) begin
if( { addr, nibble_sel } != { aend, 8'hFF, 1'b1 } ) begin
{ addr, nibble_sel } <= { addr, nibble_sel } + 25'd1;
set_flag <= 'd0;
end
else begin
end else if(arepeat) begin
restart <= 'd1;
clr_dec <= 'd1;
end else begin
set_flag <= 'd1;
if(arepeat) begin
addr <= {astart,8'd0};
nibble_sel <= 'b0;
end
chon <= 'd0;
clr_dec <= 'd1;
end
end
end // cen
endmodule // jt10_adpcmb_cnt
endmodule // jt10_adpcmb_cnt

12
common/Sound/JT12/hdl/adpcm/jt10_adpcmb_interpol.v
View File

@@ -37,7 +37,8 @@ reg start_div=1'b0;
reg [3:0] deltan, pre_dn;
reg [stages-1:0] adv2;
reg signed [15:0] pcminter;
wire [15:0] step, next_step;
wire [15:0] next_step;
reg [15:0] step;
reg step_sign, next_step_sign;
assign pcmout = pcminter;
@@ -50,8 +51,8 @@ always @(posedge clk) if(cen55) begin
if ( adv ) begin
pre_dn <= 'd1;
deltan <= pre_dn;
end else
pre_dn <= pre_dn + 1;
end else if ( pre_dn != 4'hF )
pre_dn <= pre_dn + 1'd1;
end
@@ -59,14 +60,13 @@ always @(posedge clk) if(cen) begin
start_div <= 1'b0;
if(adv2[1]) begin
pcmlast <= pcmdec;
pcminter <= pcmlast;
end
if(adv2[4]) begin
pre_dx <= { pcmdec[15], pcmdec } - { pcmlast[15], pcmlast };
end
if( adv2[5] ) begin
start_div <= 1'b1;
delta_x <= pre_dx[16] ? ~pre_dx[15:0]+1 : pre_dx[15:0];
delta_x <= pre_dx[16] ? ~pre_dx[15:0]+1'd1 : pre_dx[15:0];
next_step_sign <= pre_dx[16];
end
end
@@ -77,7 +77,7 @@ always @(posedge clk) if(cen55) begin
step_sign <= next_step_sign;
pcminter <= pcmlast;
end
else pcminter <= step_sign ? pcminter - step : pcminter + step;
else pcminter <= ( (pcminter < pcmlast) == step_sign ) ? pcminter : step_sign ? pcminter - step : pcminter + step;
end
jt10_adpcm_div #(.dw(16)) u_div(

21
common/Sound/JT12/hdl/jt03.v
View File

@@ -39,6 +39,8 @@ module jt03(
input [7:0] IOB_in,
output [7:0] IOA_out,
output [7:0] IOB_out,
output IOA_oe,
output IOB_oe,
// Separated output
output [ 7:0] psg_A,
output [ 7:0] psg_B,
@@ -47,11 +49,14 @@ module jt03(
// combined output
output [ 9:0] psg_snd,
output signed [15:0] snd,
output snd_sample
output snd_sample,
// Debug
//input [ 7:0] debug_bus,
output [ 7:0] debug_view
);
jt12_top #(
.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_adpcm(0) )
.use_lfo(0),.use_ssg(1), .num_ch(3), .use_pcm(0), .use_adpcm(0), .mask_div(0) )
u_jt12(
.rst ( rst ), // rst should be at least 6 clk&cen cycles long
.clk ( clk ), // CPU clock
@@ -64,10 +69,12 @@ u_jt12(
.dout ( dout ),
.irq_n ( irq_n ),
// YM2203 I/O pins
.IOA_out ( IOA_out ),
.IOB_out ( IOB_out ),
.IOA_in ( IOA_in ),
.IOB_in ( IOB_in ),
.IOA_out ( IOA_out ),
.IOB_out ( IOB_out ),
.IOA_oe ( IOA_oe ),
.IOB_oe ( IOB_oe ),
// Unused ADPCM pins
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
.adpcma_addr ( ), // real hardware has 10 pins multiplexed through RMPX pin
@@ -91,7 +98,11 @@ u_jt12(
.snd_right ( snd ),
.snd_left (),
.snd_sample ( snd_sample )
.snd_sample ( snd_sample ),
//.debug_bus ( debug_bus ),
.debug_bus ( 8'd0 ),
.debug_view ( debug_view )
);
endmodule // jt03

1
common/Sound/JT12/hdl/jt03_acc.v
View File

@@ -20,7 +20,6 @@
*/
`timescale 1ns / 1ps
// Use for YM2203
// no left/right channels

3
common/Sound/JT12/hdl/jt10.v
View File

@@ -91,7 +91,8 @@ u_jt12(
.snd_left ( snd_left ),
.snd_sample ( snd_sample ),
// unused pins
.en_hifi_pcm ( 1'b0 ) // used only on YM2612 mode
.en_hifi_pcm ( 1'b0 ), // used only on YM2612 mode
.debug_view ( )
);
endmodule // jt03

3
common/Sound/JT12/hdl/jt12.v
View File

@@ -75,6 +75,7 @@ jt12_top u_jt12(
.psg_snd (),
.snd_right ( snd_right ), // FM+PSG
.snd_left ( snd_left ), // FM+PSG
.snd_sample ( snd_sample )
.snd_sample ( snd_sample ),
.debug_view ( )
);
endmodule // jt03

40
common/Sound/JT12/hdl/jt12_div.v
View File

@@ -18,19 +18,18 @@
Date: 14-2-2017
*/
`timescale 1ns / 1ps
module jt12_div(
input rst,
input clk,
input cen /* synthesis direct_enable */,
input [1:0] div_setting,
output reg clk_en, // after prescaler
output reg clk_en_2, // cen divided by 2
output reg clk_en_ssg,
output reg clk_en_666, // 666 kHz
output reg clk_en_111, // 111 kHz
output reg clk_en_55 // 55 kHz
input [1:0] div_setting,
output reg clk_en, // after prescaler
output reg clk_en_2, // cen divided by 2
output reg clk_en_ssg,
output reg clk_en_666, // 666 kHz
output reg clk_en_111, // 111 kHz
output reg clk_en_55 // 55 kHz
);
parameter use_ssg=0;
@@ -81,6 +80,17 @@ initial clk_en_666 = 1'b0;
reg cen_55_int;
reg [1:0] div2=2'b0;
reg pre_clk_en, pre_clk_en_2, pre_clk_en_ssg, pre_clk_en_666, pre_clk_en_111, pre_clk_en_55;
always @(negedge clk) begin // It's important to leave the negedge to use the physical clock enable input
clk_en <= pre_clk_en;
clk_en_2 <= pre_clk_en_2;
clk_en_ssg <= pre_clk_en_ssg;
clk_en_666 <= pre_clk_en_666;
clk_en_111 <= pre_clk_en_111;
clk_en_55 <= pre_clk_en_55;
end
always @(posedge clk) begin
cen_int <= opn_cnt == 4'd0;
cen_ssg_int <= ssg_cnt == 3'd0;
@@ -88,18 +98,18 @@ always @(posedge clk) begin
cen_adpcm3_int <= adpcm_cnt111 == 3'd0;
cen_55_int <= adpcm_cnt55 == 3'd0;
`ifdef FASTDIV
// always enabled for fast sims (use with GYM output, timer will not work well)
// always enabled for fast sims (use with GYM output, the timers will not work well)
clk_en <= 1'b1;
clk_en_ssg <= 1'b1;
clk_en_666 <= 1'b1;
clk_en_55 <= 1'b1;
`else
clk_en <= cen & cen_int;
clk_en_2 <= cen && (div2==2'b00);
clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
clk_en_666 <= cen & cen_adpcm_int;
clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
pre_clk_en <= cen & cen_int;
pre_clk_en_2 <= cen && (div2==2'b00);
pre_clk_en_ssg <= use_ssg ? (cen & cen_ssg_int) : 1'b0;
pre_clk_en_666 <= cen & cen_adpcm_int;
pre_clk_en_111 <= cen & cen_adpcm_int & cen_adpcm3_int;
pre_clk_en_55 <= cen & cen_adpcm_int & cen_adpcm3_int & cen_55_int;
`endif
end

1
common/Sound/JT12/hdl/jt12_exprom.v
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT12.

1
common/Sound/JT12/hdl/jt12_kon.v
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT12.

1
common/Sound/JT12/hdl/jt12_lfo.v
View File

@@ -18,7 +18,6 @@
Date: 25-2-2017
*/
`timescale 1ns / 1ps
/*

25
common/Sound/JT12/hdl/jt12_mmr.v
View File

@@ -18,7 +18,6 @@
Date: 14-2-2017
*/
`timescale 1ns / 1ps
module jt12_mmr(
input rst,
@@ -52,6 +51,7 @@ module jt12_mmr(
output reg fast_timers,
input flag_A,
input overflow_A,
output reg [1:0] div_setting,
// PCM
output reg [8:0] pcm,
output reg pcm_en,
@@ -77,6 +77,7 @@ module jt12_mmr(
output reg [15:0] adeltan_b, // Delta-N
output reg [ 7:0] aeg_b, // Envelope Generator Control
output reg [ 6:0] flag_ctl,
output reg [ 6:0] flag_mask,
// Operator
output xuse_prevprev1,
output xuse_internal,
@@ -122,13 +123,11 @@ module jt12_mmr(
// PSG interace
output [3:0] psg_addr,
output [7:0] psg_data,
output reg psg_wr_n
output reg psg_wr_n,
input [7:0] debug_bus
);
parameter use_ssg=0, num_ch=6, use_pcm=1, use_adpcm=0;
reg [1:0] div_setting;
parameter use_ssg=0, num_ch=6, use_pcm=1, use_adpcm=0, mask_div=1;
jt12_div #(.use_ssg(use_ssg)) u_div (
.rst ( rst ),
@@ -200,6 +199,13 @@ endgenerate
reg part;
`ifdef SIMULATION
always @(posedge clk) if( write && rst ) begin
$display("WARNING [JT12]: detected write request while in reset.\nThis is likely a glue-logic error in the CPU-FM module.");
$finish;
end
`endif
// this runs at clk speed, no clock gating here
// if I try to make this an async rst it fails to map it
// as flip flops but uses latches instead. So I keep it as sync. reset
@@ -266,6 +272,7 @@ always @(posedge clk) begin : memory_mapped_registers
if( !addr[0] ) begin
selected_register <= din;
part <= addr[1];
if (!mask_div)
case(din)
// clock divider: should work only for ym2203
// and ym2608.
@@ -374,7 +381,11 @@ always @(posedge clk) begin : memory_mapped_registers
4'h9: adeltan_b[ 7:0] <= din;
4'ha: adeltan_b[15:8] <= din;
4'hb: aeg_b <= din;
4'hc: flag_ctl <= {din[7],din[5:0]}; // this lasts a single clock cycle
4'hc: begin
flag_mask <= ~{din[7],din[5:0]};
flag_ctl <= {din[7],din[5:0]}; // this lasts a single clock cycle
end
default:;
endcase
end

1
common/Sound/JT12/hdl/jt12_mod.v
View File

@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT12.

1
common/Sound/JT12/hdl/jt12_op.v
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@@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* This file is part of JT12.

1
common/Sound/JT12/hdl/jt12_pg.v
View File

@@ -24,7 +24,6 @@ http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc
*/
`timescale 1ns / 1ps
/*

1
common/Sound/JT12/hdl/jt12_pm.v
View File

@@ -18,7 +18,6 @@
Date: 14-10-2018
*/
`timescale 1ns / 1ps
// This implementation follows that of Alexey Khokholov (Nuke.YKT) in C language.

1
common/Sound/JT12/hdl/jt12_sh.v
View File

@@ -18,7 +18,6 @@
Date: 1-31-2017
*/
`timescale 1ns / 1ps
// stages must be greater than 2
module jt12_sh #(parameter width=5, stages=24 )

1
common/Sound/JT12/hdl/jt12_sh24.v
View File

@@ -18,7 +18,6 @@
Date: 1-31-2017
*/
`timescale 1ns / 1ps
module jt12_sh24 #(parameter width=5 )
(

1
common/Sound/JT12/hdl/jt12_sh_rst.v
View File

@@ -18,7 +18,6 @@
Date: 1-31-2017
*/
`timescale 1ns / 1ps
// stages must be greater than 2
module jt12_sh_rst #(parameter width=5, stages=32, rstval=1'b0 )

1
common/Sound/JT12/hdl/jt12_single_acc.v
View File

@@ -23,7 +23,6 @@
// Accumulates an arbitrary number of inputs with saturation
// restart the sum when input "zero" is high
`timescale 1ns / 1ps
module jt12_single_acc #(parameter
win=14, // input data width

1
common/Sound/JT12/hdl/jt12_sumch.v
View File

@@ -18,7 +18,6 @@
Date: 1-31-2017
*/
`timescale 1ns / 1ps
/* The input is {op[1:0], ch[2:0]}
it adds 1 to the channel and overflow to the operator correctly */

25
common/Sound/JT12/hdl/jt12_timers.v
View File

@@ -22,7 +22,6 @@
Timer B = 2304*(256-NB)/Phi M
*/
`timescale 1ns / 1ps
module jt12_timers(
input clk,
@@ -101,8 +100,8 @@ module jt12_timer #(parameter
output reg flag,
output reg overflow
);
reg last_load;
/* verilator lint_off WIDTH */
reg load_l;
reg [CW-1:0] cnt, next;
reg [FW-1:0] free_cnt, free_next;
reg free_ov;
@@ -113,7 +112,7 @@ always@(posedge clk, posedge rst)
else /*if(cen)*/ begin
if( clr_flag )
flag <= 1'b0;
else if(overflow) flag<=1'b1;
else if( cen && zero && load && overflow ) flag<=1'b1;
end
always @(*) begin
@@ -121,21 +120,21 @@ always @(*) begin
{overflow, next } = { 1'b0, cnt } + (FREE_EN ? free_ov : 1'b1);
end
always @(posedge clk) if(cen && zero) begin : counter
last_load <= load;
if( (load && !last_load) || overflow ) begin
cnt <= start_value;
end
else if( last_load ) cnt <= next;
always @(posedge clk) begin
load_l <= load;
if( !load_l && load ) begin
cnt <= start_value;
end else if( cen && zero && load )
cnt <= overflow ? start_value : next;
end
// Free running counter
always @(posedge clk) begin
if( rst ) begin
free_cnt <= {FW{1'b0}};
end else if( cen&&zero ) begin
free_cnt <= 0;
end else if( cen && zero ) begin
free_cnt <= free_cnt+1'd1;
end
end
/* verilator lint_on WIDTH */
endmodule

35
common/Sound/JT12/hdl/jt12_top.v
View File

@@ -27,7 +27,7 @@ http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc
module jt12_top (
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
input cen, // optional clock enable, it not needed leave as 1'b1
(* direct_enable *) input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
@@ -50,6 +50,8 @@ module jt12_top (
input [7:0] IOB_in,
output [7:0] IOA_out,
output [7:0] IOB_out,
output IOA_oe,
output IOB_oe,
// Separated output
output [ 7:0] psg_A,
output [ 7:0] psg_B,
@@ -64,7 +66,9 @@ module jt12_top (
output [ 9:0] psg_snd,
output signed [15:0] snd_right, // FM+PSG
output signed [15:0] snd_left, // FM+PSG
output snd_sample
output snd_sample,
input [ 7:0] debug_bus,
output [ 7:0] debug_view
);
// parameters to select the features for each chip type
@@ -72,6 +76,7 @@ module jt12_top (
parameter use_lfo=1, use_ssg=0, num_ch=6, use_pcm=1;
parameter use_adpcm=0;
parameter JT49_DIV=2;
parameter mask_div=1;
wire flag_A, flag_B, busy;
@@ -162,10 +167,13 @@ wire [ 7:0] aeg_b; // Envelope Generator Control
wire [ 5:0] adpcma_flags; // ADPMC-A read over flags
wire adpcmb_flag;
wire [ 6:0] flag_ctl;
wire [ 6:0] flag_mask;
wire [ 1:0] div_setting;
wire clk_en_2, clk_en_666, clk_en_111, clk_en_55;
assign debug_view = { 4'd0, flag_B, flag_A, div_setting };
generate
if( use_adpcm==1 ) begin: gen_adpcm
wire rst_n;
@@ -217,7 +225,7 @@ if( use_adpcm==1 ) begin: gen_adpcm
.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
.acmd_rst_b ( acmd_rst_b ), // Control - Reset
//.acmd_up_b ( acmd_up_b ), // Control - New command received
.acmd_up_b ( acmd_up_b ), // Control - New command received
.alr_b ( alr_b ), // Left / Right
.astart_b ( astart_b ), // Start address
.aend_b ( aend_b ), // End address
@@ -268,6 +276,8 @@ end else begin : gen_adpcm_no
assign adpcma_roe_n = 'b1;
assign adpcmb_addr = 'd0;
assign adpcmb_roe_n = 'd1;
assign adpcma_flags = 0;
assign adpcmb_flag = 0;
end
endgenerate
@@ -278,8 +288,8 @@ jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
.flag_A ( flag_A ),
.flag_B ( flag_B ),
.busy ( busy ),
.adpcma_flags ( adpcma_flags ),
.adpcmb_flag ( adpcmb_flag ),
.adpcma_flags ( adpcma_flags & flag_mask[5:0] ),
.adpcmb_flag ( adpcmb_flag & flag_mask[6] ),
.psg_dout ( psg_dout ),
.addr ( addr ),
.dout ( dout )
@@ -287,7 +297,7 @@ jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
/* verilator tracing_on */
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm))
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm), .mask_div(mask_div))
u_mmr(
.rst ( rst ),
.clk ( clk ),
@@ -345,6 +355,7 @@ jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_a
.adeltan_b ( adeltan_b ), // Delta-N
.aeg_b ( aeg_b ), // Envelope Generator Control
.flag_ctl ( flag_ctl ),
.flag_mask ( flag_mask ),
// Operator
.xuse_prevprev1 ( xuse_prevprev1 ),
.xuse_internal ( xuse_internal ),
@@ -389,7 +400,9 @@ jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_a
// PSG interace
.psg_addr ( psg_addr ),
.psg_data ( psg_data ),
.psg_wr_n ( psg_wr_n )
.psg_wr_n ( psg_wr_n ),
.debug_bus ( debug_bus ),
.div_setting(div_setting)
);
/* verilator tracing_on */
@@ -442,7 +455,7 @@ endgenerate
`ifndef NOSSG
generate
if( use_ssg==1 ) begin : gen_ssg
jt49 #(.COMP(2'b00), .CLKDIV(JT49_DIV))
jt49 #(.COMP(2'b01), .CLKDIV(JT49_DIV))
u_psg( // note that input ports are not multiplexed
.rst_n ( ~rst ),
.clk ( clk ), // signal on positive edge
@@ -457,11 +470,13 @@ generate
.C ( psg_C ),
.dout ( psg_dout ),
.sel ( 1'b1 ), // half clock speed
// Unused:
.IOA_out ( IOA_out ),
.IOB_out ( IOB_out ),
.IOA_in ( IOA_in ),
.IOB_in ( IOB_in ),
.IOA_oe ( IOA_oe ),
.IOB_oe ( IOB_oe ),
// Unused:
.sample ( )
);
assign snd_left = fm_snd_left + { 1'b0, psg_snd[9:0],5'd0};

14
common/Sound/JT49/jt49.v
View File

@@ -39,14 +39,16 @@ module jt49 ( // note that input ports are not multiplexed
input [7:0] IOA_in,
output [7:0] IOA_out,
output IOA_oe,
input [7:0] IOB_in,
output [7:0] IOB_out
output [7:0] IOB_out,
output IOB_oe
);
parameter [2:0] COMP=3'b000;
parameter [1:0] COMP=2'b00;
parameter CLKDIV=3;
wire [2:0] comp = COMP;
wire [1:0] comp = COMP;
reg [7:0] regarray[15:0];
wire [7:0] port_A, port_B;
@@ -60,8 +62,10 @@ wire cen16, cen256;
assign IOA_out = regarray[14];
assign IOB_out = regarray[15];
assign port_A = !regarray[7][6] ? IOA_in : IOA_out;
assign port_B = !regarray[7][7] ? IOB_in : IOB_out;
assign port_A = IOA_in;
assign port_B = IOB_in;
assign IOA_oe = regarray[7][6];
assign IOB_oe = regarray[7][7];
assign sample = cen16;
jt49_cen #(.CLKDIV(CLKDIV)) u_cen(

10
common/Sound/JT49/jt49_bus.v
View File

@@ -42,12 +42,14 @@ module jt49_bus ( // note that input ports are not multiplexed
input [7:0] IOA_in,
output [7:0] IOA_out,
output IOA_oe,
input [7:0] IOB_in,
output [7:0] IOB_out
output [7:0] IOB_out,
output IOB_oe
);
parameter [2:0] COMP=3'b000;
parameter [1:0] COMP=2'b00;
reg wr_n, cs_n;
reg [3:0] addr;
@@ -94,8 +96,10 @@ jt49 #(.COMP(COMP)) u_jt49( // note that input ports are not multiplexed
.C ( C ),
.IOA_in ( IOA_in ),
.IOA_out( IOA_out ),
.IOA_oe ( IOA_oe ),
.IOB_in ( IOB_in ),
.IOB_out( IOB_out )
.IOB_out( IOB_out ),
.IOB_oe ( IOB_oe )
);
endmodule // jt49_bus

37
common/Sound/JT49/jt49_exp.v
View File

@@ -21,7 +21,6 @@
*/
`timescale 1ns / 1ps
// Compression vs dynamic range
// 0 -> 43.6dB
@@ -31,12 +30,12 @@
module jt49_exp(
input clk,
input [2:0] comp, // compression
input [1:0] comp, // compression
input [4:0] din,
output reg [7:0] dout
);
reg [7:0] lut[0:159];
reg [7:0] lut[0:127];
always @(posedge clk)
dout <= lut[ {comp,din} ];
@@ -170,38 +169,6 @@ initial begin
lut[125] = 8'd229;
lut[126] = 8'd241;
lut[127] = 8'd255;
lut[128] = 8'd0;
lut[129] = 8'd8;
lut[130] = 8'd10;
lut[131] = 8'd12;
lut[132] = 8'd16;
lut[133] = 8'd22;
lut[134] = 8'd29;
lut[135] = 8'd35;
lut[136] = 8'd44;
lut[137] = 8'd50;
lut[138] = 8'd56;
lut[139] = 8'd60;
lut[140] = 8'd64;
lut[141] = 8'd85;
lut[142] = 8'd97;
lut[143] = 8'd103;
lut[144] = 8'd108;
lut[145] = 8'd120;
lut[146] = 8'd127;
lut[147] = 8'd134;
lut[148] = 8'd141;
lut[149] = 8'd149;
lut[150] = 8'd157;
lut[151] = 8'd166;
lut[152] = 8'd175;
lut[153] = 8'd185;
lut[154] = 8'd195;
lut[155] = 8'd206;
lut[156] = 8'd217;
lut[157] = 8'd229;
lut[158] = 8'd241;
lut[159] = 8'd255;
end
endmodule

1
common/Sound/JT49/jt49_noise.v
View File

@@ -21,7 +21,6 @@
*/
`timescale 1ns / 1ps
module jt49_noise(
(* direct_enable *) input cen,

27
common/Sound/jtopl/common.qip Normal file
View File

@@ -0,0 +1,27 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_slot_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]

4
common/Sound/jtopl/jt2413.qip Normal file
View File

@@ -0,0 +1,4 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) common.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jt2413.v]

32
common/Sound/jtopl/jt26.qip
View File

@@ -1,30 +1,4 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_csr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_div.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_lfo.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pm.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_cnt.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_ctrl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_final.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_pure.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg_step.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_eg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_exprom.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_logsin.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_op.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_comb.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_inc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_sum.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg_rhy.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_pg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg_ch.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh_rst.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_sh.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_single_acc.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_timers.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_noise.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_slot_cnt.v]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) common.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_mmr.v]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl_reg.v]

4
common/Sound/jtopl/jtopl2.qip
View File

@@ -1,2 +1,2 @@
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl2.v ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip ]
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopl2.v]

7
common/Sound/jtopl/jtopl_mmr.v
View File

@@ -98,6 +98,13 @@ reg wave_mode, // 1 if waveform selection is enabled (OPL2)
note_sel; // keyboard split, not implemented
reg [ 4:0] rhy_kon;
`ifdef SIMULATION
always @(posedge clk) if( write && rst ) begin
$display("WARNING [JTOPL]: detected write request while in reset.\nThis is likely a glue-logic error in the CPU-FM module.");
$finish;
end
`endif
// this runs at clk speed, no clock gating here
// if I try to make this an async rst it fails to map it
// as flip flops but uses latches instead. So I keep it as sync. reset

2
common/Sound/jtopl/jtopll.qip Normal file
View File

@@ -0,0 +1,2 @@
set_global_assignment -name QIP_FILE [file join $::quartus(qip_path) jt26.qip]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) jtopll.v]