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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 09:02:08 +00:00

Playing with SDRAM

This commit is contained in:
Gehstock 2018-07-23 19:15:20 +02:00
parent 0ba8f8a7b1
commit be2537441d
8 changed files with 15 additions and 16 deletions

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@ -0,0 +1 @@
use sdram für 32k ERAM need Test

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@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
@ -154,9 +154,6 @@ set_global_assignment -name TOP_LEVEL_ENTITY ace_mist
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON

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@ -3,6 +3,7 @@ del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q output
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files

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@ -68,7 +68,7 @@ pll pll(
.c0(clk_sys),//26.0Mhz
.c1(clk_65),//6.5Mhz
.c2(clk_cpu),//3.25Mhz
.c3(clk_sdram),//100Mhz
.c3(SDRAM_CLK),//100Mhz
.locked(locked)
);
@ -127,7 +127,7 @@ video_mixer #(.LINE_LENGTH(800), .HALF_DEPTH(1)) video_mixer
.VGA_HS(VGA_HS)
);
wire [24:0]sd_addr;
wire [14:0]sd_addr;
wire [7:0]sd_dout;
wire [7:0]sd_din;
wire sd_we;
@ -145,9 +145,9 @@ sram sram(
.SDRAM_nRAS(SDRAM_nRAS),
.SDRAM_nCAS(SDRAM_nCAS),
.SDRAM_CKE(SDRAM_CKE),
.init(~reset),
.clk_sdram(clk_sdram),
.addr(sd_addr), // 25 bit address
.init(~locked),
.clk_sdram(SDRAM_CLK),
.addr({10'b0000000000,sd_addr}), // 25 bit address
.dout(sd_dout), // data output to cpu
.din(sd_din), // data input from cpu
.we(sd_we), // cpu requests write

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@ -1,2 +1,2 @@
`define BUILD_DATE "171124"
`define BUILD_TIME "193745"
`define BUILD_DATE "180723"
`define BUILD_TIME "190837"

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@ -33,9 +33,9 @@ module jupiter_ace (
output wire vsync,
output wire mic,
output wire spk,
output wire sd_addr,
input wire sd_dout,
output wire sd_din,
output wire [14:0] sd_addr,
input wire [7:0] sd_dout,
output wire [7:0] sd_din,
output wire sd_we,
output wire sd_rd,
input wire sd_ready
@ -111,8 +111,8 @@ module jupiter_ace (
.we(~wr_n)
);
assign sd_addr = AZ80[13:0];
//assign sd_dout = dout_eram;
assign sd_addr = AZ80[14:0];
assign dout_eram = sd_dout;
assign sd_din = DoutZ80;
assign sd_we = ~wr_n;
assign sd_rd = eram_enable;