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Code Issues Releases Wiki Activity

Unbreak Vectrex again - this is annoying

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This commit is contained in:
Gyorgy Szombathelyi
2020-01-04 01:13:59 +01:00
parent 51f612f34c
commit bf69898f57
3 changed files with 4 additions and 76 deletions
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71
Console_MiST/GCE - Vectrex_MiST/rtl/dac.vhd
View File

@@ -1,71 +0,0 @@
-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity dac is
generic (
msbi_g : integer := 9
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(msbi_g downto 0);
dac_o : out std_logic
);
end dac;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dac is
signal DACout_q : std_logic;
signal DeltaAdder_s,
SigmaAdder_s,
SigmaLatch_q,
DeltaB_s : unsigned(msbi_g+2 downto 0);
begin
DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
SigmaLatch_q(msbi_g+2);
DeltaB_s(msbi_g downto 0) <= (others => '0');
DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
seq: process (clk_i, res_n_i)
begin
if res_n_i = '0' then
SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
DACout_q <= '0';
elsif clk_i'event and clk_i = '1' then
SigmaLatch_q <= SigmaAdder_s;
DACout_q <= SigmaLatch_q(msbi_g+2);
end if;
end process seq;
dac_o <= DACout_q;
end rtl;

4
Console_MiST/GCE - Vectrex_MiST/rtl/vectrex_mist.sv
View File

@@ -166,7 +166,7 @@ vectrex vectrex (
.dbg_cpu_addr ( )
);
dac dac (
dac #(10) dac (
.clk_i ( clk_24 ),
.res_n_i ( 1 ),
.dac_i ( audio ),
@@ -198,7 +198,7 @@ mist_video #(.COLOR_DEPTH(4)) mist_video
.G(g),
.B(b),
.VGA_HS(VGA_HS),
.VGA_VS(VGS_VS),
.VGA_VS(VGA_VS),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B)

5
Console_MiST/GCE - Vectrex_MiST/vectrex_MiST.qsf
View File

@@ -41,7 +41,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
@@ -344,7 +344,6 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
set_global_assignment -name USE_SIGNALTAP_FILE output_files/sdram.stp
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
@@ -353,7 +352,6 @@ set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd
set_global_assignment -name VHDL_FILE rtl/m6522a.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/mc6809is.v
set_global_assignment -name VERILOG_FILE rtl/mc6809.v
@@ -362,4 +360,5 @@ set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd
set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top