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Tank Battalion

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This commit is contained in:
Marcel
2022-10-31 15:24:06 +01:00
parent d8abd48628
commit bfef66d461
26 changed files with 78605 additions and 9 deletions
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4
Arcade_MiST/Gremlin Blockade Hardware/rtl/Blockede_MiST.sv
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@@ -226,8 +226,8 @@ begin
dip_comotion_lives <= sw[0];
dip_overlay_type <= sw[2:1];
dip_boom <= sw[3];
IN_1 <= ~{m_coin1, 2'b0, m_one_player, dip_comotion_lives, dip_boom, 2'b00};
IN_2 <= ~{m_left2, m_down2, m_right2, m_up2, m_left, m_down, m_right, m_up};
IN_1 <= ~{m_coin1, 2'b0, m_one_player, dip_comotion_lives, dip_boom, 2'b00};
IN_2 <= ~{m_left3, m_down3, m_right3, m_up3, m_left, m_down, m_right, m_up};
IN_4 <= ~{m_left4, m_down4, m_right4, m_up4, m_left4, m_down4, m_right4, m_up4};
end
7'h2: // GAME_HUSTLE

20
Arcade_MiST/Gremlin Blockade Hardware/rtl/blockade.v
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@@ -54,6 +54,13 @@ localparam GAME_HUSTLE = 2;
localparam GAME_BLASTO = 3;
localparam GAME_MINESWEEPER = 4;
localparam GAME_MINESWEEPER4 = 5;
localparam COIN_START_TIMER_WIDTH = 6;
reg [COIN_START_TIMER_WIDTH-1:0] coin_start;
localparam COIN_LATCH_TIMER_WIDTH = 6;
reg [COIN_LATCH_TIMER_WIDTH-1:0] coin_latch;
// CPU and Video system clock enables
// ----------------------------------
@@ -116,7 +123,8 @@ wire WR_N;
wire SYNC /*verilator public_flat*/;
// CPU reset can originate from system reset signal or coin start signal (only for CoMotion, Hustle, and Blasto)
wire RESET = reset || (game_mode != GAME_BLOCKADE && coin_start > 6'b0);
//wire RESET = reset || (game_mode != GAME_BLOCKADE && coin_start > 6'b0);
wire RESET = reset || (game_mode != GAME_BLOCKADE && coin_start > {COIN_START_TIMER_WIDTH{1'b0}});
// 8080A CPU
vm80a cpu
@@ -417,9 +425,7 @@ assign audio_r = audio_l;
// ------------
wire OUTP1 = OUTP && ADDR[0];
reg coin_last;
reg [5:0] coin_start;
reg coin_inserted;
reg [5:0] coin_latch;
always @(posedge clk) begin
if(reset)
@@ -434,10 +440,10 @@ always @(posedge clk) begin
begin
if(coin_inserted)
begin
coin_latch <= 6'b111111;
coin_latch <= {COIN_LATCH_TIMER_WIDTH{1'b1}};
coin_inserted <= 1'b0;
end
if(coin_latch > 6'b0) coin_latch <= coin_latch - 1'b1;
if(coin_latch > {COIN_LATCH_TIMER_WIDTH{1'b0}}) coin_latch <= coin_latch - 1'b1;
end
// When coin input is going high, latch coin inserted and start reset pulse
@@ -445,11 +451,11 @@ always @(posedge clk) begin
if(coin && !coin_last)
begin
coin_inserted <= 1'b1;
coin_start <= 6'b111111;
coin_start <= {COIN_START_TIMER_WIDTH{1'b1}};
end
// Decrement coin start timer if active
if(coin_start > 6'b0) coin_start <= coin_start - 6'b1;
if(coin_start > {COIN_START_TIMER_WIDTH{1'b0}}) coin_start <= coin_start - 6'b1;
end
end

39
Arcade_MiST/Namco Tank_Battalion/README.txt Normal file
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@@ -0,0 +1,39 @@
---------------------------------------------------------------------------------
--
-- Arcade version of Tank Battalion for MiSTer from Namco - MiSTerRetroWolf
--
-- V 1.0 08/20/2022 - Nick Stone
---------------------------------------------------------------------------------
-- Supports screen and controls rotation on HDMI output.
-- Sound now supported via samples
--
-- Inputs:
-- UP,DOWN,LEFT,RIGHT : Tank Movements
-- Fire
-- Coin 1
-- Start 1 Player
-- Start 2 Players (alternate play)
-- Test button: in DIP settings enable test mode
-- and then the test button toggle which bullet is selected
--
--
---------------------------------------------------------------------------------
*** Attention ***
ROMs are not included. In order to use this arcade, you need to provide the
correct ROMs.
To simplify the process .mra files are provided in the releases folder, that
specifies the required ROMs with checksums. The ROMs .zip filename refers to the
corresponding file of the M.A.M.E. project.
Please refer to https://github.com/MiSTer-devel/Main_MiSTer/wiki/Arcade-Roms for
information on how to setup and use the environment.
Quickreference for folders and file placement:
/_Arcade/<game name>.mra
/_Arcade/cores/<game rbf>.rbf
/_Arcade/mame/<mame rom>.zip
/_Arcade/hbmame/<hbmame rom>.zip

30
Arcade_MiST/Namco Tank_Battalion/TankBatt.qpf Normal file
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@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 16:01:18 November 25, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "16:01:18 November 25, 2020"
# Revisions
PROJECT_REVISION = "TankBatt"

189
Arcade_MiST/Namco Tank_Battalion/TankBatt.qsf Normal file
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@@ -0,0 +1,189 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
# Date created = 14:46:10 October 31, 2022
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TankBatt_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TankBatt_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/Tankb_fpga.v
set_global_assignment -name VERILOG_FILE rtl/ttl_chips.v
set_global_assignment -name VERILOG_FILE rtl/sound_FSM.v
set_global_assignment -name VHDL_FILE rtl/EngineSound.vhd
set_global_assignment -name VERILOG_FILE rtl/clock.v
set_global_assignment -name VERILOG_FILE rtl/ram.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/mist/mist.qip"
set_global_assignment -name QIP_FILE "D:/GitHub/Mist_FPGA/common/CPU/T65/T65.qip"
set_global_assignment -name VHDL_FILE rtl/rom/l3.vhd
set_global_assignment -name VHDL_FILE rtl/rom/k3.vhd
set_global_assignment -name VHDL_FILE rtl/rom/a1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/b1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/c1.vhd
set_global_assignment -name VHDL_FILE rtl/rom/d1.vhd
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SEARCH_PATH Mist_FPGA/common/CPU/T80/ -tag from_archive
set_global_assignment -name SEARCH_PATH Mist_FPGA/common/Sound/ym2149/ -tag from_archive
set_global_assignment -name SEARCH_PATH Mist_FPGA/common/mist/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/rom/ -tag from_archive
set_global_assignment -name SEARCH_PATH rtl/ttl/ -tag from_archive
set_global_assignment -name TOP_LEVEL_ENTITY TankBatt_MiST
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/dect.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------------
# start ENTITY(TankBatt_MiST)
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TankBatt_MiST)
# -------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

15
Arcade_MiST/Namco Tank_Battalion/clean.bat Normal file
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@@ -0,0 +1,15 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

164
Arcade_MiST/Namco Tank_Battalion/rtl/EngineSound.vhd Normal file
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@@ -0,0 +1,164 @@
-- Motor sound generator for Kee Games Ultra Tank
-- This was originally created for Sprint 2 - Identical circuit
-- Similar circuits are used in a number of other games
-- (c) 2017 James Sweet
--
-- Original circuit used a 555 configured as an astable oscillator with the frequency controlled by
-- a four bit binary value. The output of this oscillator drives a counter configured to produce an
-- irregular thumping simulating the sound of an engine.
--
-- This is free software: you can redistribute
-- it and/or modify it under the terms of the GNU General
-- Public License as published by the Free Software
-- Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This is distributed in the hope that it will
-- be useful, but WITHOUT ANY WARRANTY; without even the
-- implied warranty of MERCHANTABILITY or FITNESS FOR A
-- PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity EngineSound is
generic(
constant Freq_tune : integer := 50 -- Value from 0-100 used to tune the overall engine sound frequency
);
port(
Clk_6 : in std_logic;
Reset : in std_logic;
highrpm : in std_logic;
Motor : out std_logic_vector(5 downto 0)
);
end EngineSound;
architecture rtl of EngineSound is
signal RPM_val : integer range 1 to 350;
signal Ramp_term_unfilt : integer range 1 to 80000;
signal Ramp_Count : integer range 0 to 80000;
signal Ramp_term : integer range 1 to 80000;
signal Freq_mod : integer range 0 to 400;
signal Motor_Clk : std_logic;
signal Counter_A : std_logic;
signal Counter_B : unsigned(2 downto 0);
signal Counter_A_clk : std_logic;
signal Motor_prefilter : unsigned(1 downto 0);
signal Motor_filter_t1 : unsigned(3 downto 0);
signal Motor_filter_t2 : unsigned(3 downto 0);
signal Motor_filter_t3 : unsigned(3 downto 0);
signal Motor_filtered : unsigned(5 downto 0);
signal ena_count : std_logic_vector(10 downto 0) := (others => '0');
signal ena_3k : std_logic := '0';
begin
Enable: process(clk_6)
begin
if rising_edge(CLK_6) then
ena_count <= ena_count + "1";
ena_3k <= '0';
if (ena_count(10 downto 0) = "00000000000") then
ena_3k <= '1';
end if;
end if;
end process;
-- The frequency of the oscillator is set by a 4 bit binary value controlled by the game CPU
-- in the real hardware this is a 555 coupled to a 4 bit resistor DAC used to pull the frequency.
-- The output of this DAC has a capacitor to smooth out the frequency variation.
-- The constants assigned to RPM_val can be tweaked to adjust the frequency curve
Speed_select: process(Clk_6)
begin
if rising_edge(Clk_6) then
if (highrpm = '1') then
RPM_val <= 25;
else
RPM_val <= 50;
end if;
end if;
end process;
-- There is a RC filter between the frequency control DAC and the 555 to smooth out the transitions between the
-- 16 possible states. We can simulate a reasonable approximation of that behavior using a linear slope which is
-- not truly accurate but should be close enough.
RC_filt: process(clk_6, ena_3k, ramp_term_unfilt)
begin
if rising_edge(clk_6) then
if ena_3k = '1' then
if ramp_term_unfilt > ramp_term then
ramp_term <= ramp_term + 10;
elsif ramp_term_unfilt = ramp_term then
ramp_term <= ramp_term;
else
ramp_term <= ramp_term - 8;
end if;
end if;
end if;
end process;
-- Ramp_term terminates the ramp count, the higher this value, the longer the ramp will count up and the lower
-- the frequency. RPM_val is multiplied by a constant which can be adjusted by changing the value of freq_tune
-- to simulate the function of the frequency adjustment pot in the original hardware.
ramp_term_unfilt <= ((200 - freq_tune) * RPM_val);
-- Variable frequency oscillator roughly approximating the function of a 555 astable oscillator
Ramp_osc: process(clk_6)
begin
if rising_edge(clk_6) then
motor_clk <= '1';
ramp_count <= ramp_count + 1;
if ramp_count > ramp_term then
ramp_count <= 0;
motor_clk <= '0';
end if;
end if;
end process;
-- 7492 counter with XOR on two of the outputs creates lumpy engine sound from smooth pulse train
-- 7492 has two sections, one div-by-2 and one div-by-6.
Engine_counter: process(motor_clk, counter_A_clk, counter_B, reset)
begin
if reset = '1' then
Counter_B <= (others => '0');
elsif rising_edge(motor_clk) then
Counter_B <= Counter_B + '1';
end if;
Counter_A_clk <= Counter_B(0) xor Counter_B(2);
if reset = '1' then
Counter_A <= '0';
elsif rising_edge(counter_A_clk) then
Counter_A <= (not Counter_A);
end if;
end process;
motor_prefilter <= ('0' & Counter_B(2)) + ('0' & Counter_B(1)) + ('0' & Counter_A);
-- Very simple low pass filter, borrowed from MikeJ's Asteroids code
Engine_filter: process(clk_6)
begin
if rising_edge(clk_6) then
if (ena_3k = '1') then
motor_filter_t1 <= ("00" & motor_prefilter) + ("00" & motor_prefilter);
motor_filter_t2 <= motor_filter_t1;
motor_filter_t3 <= motor_filter_t2;
end if;
motor_filtered <= ("00" & motor_filter_t1) +
('0' & motor_filter_t2 & '0') +
("00" & motor_filter_t3);
end if;
end process;
motor <= std_logic_vector(motor_filtered);
end rtl;

178
Arcade_MiST/Namco Tank_Battalion/rtl/TankBatt_MiST.sv Normal file
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@@ -0,0 +1,178 @@
module TankBatt_MiST
(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
//Todo Sound
localparam CONF_STR = {
"CENTIPED;;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
// "O6,Joystick Swap,Off,On;",
"O8,Test Mode,Off,On;",
"O9,Lives,3,2;",
"OCD,Coinage,1 Coin/1 Credit,2 Coins/1 Credit,1 Coin/2 Credits,Freeplay;",
"OAB,Bonus,20000,10000,None,15000;",
"OE,Cabinet,Upright,Cocktail;",
"T0,Reset;",
"V,v1.50.",`BUILD_DATE
};
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire joyswap = status[6];
wire service = status[8];
wire cabinet = status[14];
wire [1:0] coinage = status[13:12];
wire lives = status[9];
wire [1:0] bonus = status[13:12];
wire [1:0] orientation = 2'b11;
assign LED = 1'b1;
assign AUDIO_R = AUDIO_L;
wire clk_6, clk_18, clk_36;
wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_36),//36.864
.c1(clk_18),//18.432
.c2(clk_6)//6.144
);
wire [63:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [31:0] joystick_0;
wire [31:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire no_csync;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire r, g, b;
wire hs, vs, vb, hb;
wire blankn = ~(hb | vb);
wire [15:0] audio;
wire [5:0] motor;
wire resetn = ~(status[0] | buttons[1]);
Tankb_fpga Tankb_fpga(
.CLK_18M(clk_18),
.CLK_6M(clk_6),
.RESET_n(resetn),
.vid_r(r),
.vid_g(g),
.vid_b(b),
.vid_hs(hs),
.vid_vs(vs),
.vid_hb(hb),
.vid_vb(vb),
.P1(~{service,m_coin2,m_coin1,m_fireA,m_right,m_down,m_left,m_up}),
.P2(~{1'b0,m_two_players,m_one_player,m_fire2A,m_right2,m_down2,m_left2,m_up2}),
.DSW(~{2'b00,lives,bonus,coinage,cabinet}),
.audio(audio)
);
mist_video #(.COLOR_DEPTH(1), .SD_HCNT_WIDTH(9)) mist_video(
.clk_sys ( clk_36 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( ~hs ),
.VSync ( ~vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.scanlines ( scanlines ),
.rotate ( {orientation[1],rotate} ),
.ce_divider ( 1'b0 ),
.blend ( blend ),
.scandoubler_disable(scandoublerD ),
.no_csync ( no_csync ),
.ypbpr ( ypbpr )
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_18 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.no_csync (no_csync ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(16))
dac (
.clk_i(clk_18),
.res_n_i(1),
.dac_i({~audio[15],audio[14:0]}),
.dac_o(AUDIO_L)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_18 ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( orientation ),
.joyswap ( joyswap ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

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module Tankb_fpga(
input CLK_18M,
input CLK_6M,
input RESET_n,
output vid_r,
output vid_g,
output vid_b,
output vid_hs,
output vid_vs,
output vid_cs,
output vid_hb,
output vid_vb,
input [7:0] P1,
input [7:0] P2,
input [7:0] DSW,
output signed [15:0] audio
);
wire nRESET = (nRESET_PO & RESET_n);
//power-on reset
reg [5:0] reset_cnt = 0;
wire nRESET_PO = &reset_cnt;
always @(posedge clk) begin
reset_cnt <= reset_cnt + !nRESET_PO;
end
//end power-on reset
//wire & reg setup
wire clk = CLK_18M;
wire PUR = nRESET;
wire A5_1_nq,A6_1_q,A6_1_nq,A6_2_q,A6_2_nq;
wire H1,H2,H4,H8,H16,H32,H64,H128,nH256;
wire A5_2_d=(~H64 & H32);
wire H256=~nH256;
wire B6_ca,C6_ca,E6_ca,D6_ca;
wire nHSYNC;
wire M6Hz=~A6_2_q;
wire nM6PRI=A6_1_nq;
wire D5_2_nq;
wire Phi=H4;
wire nH4_nH8=(~H4 & ~H8);
wire V1,V2,V4,V8,V16,V32,V64,V128,nVSYNC;
wire H256star,nH256star;
wire nCOMPSYNC=(nHSYNC & nVSYNC);
wire nINTACK,nIRQ,VBLANK;
wire F5_1_d=~(V128 & V64 & V32);
wire [7:0] L2_q,K2_d;
wire J2_q;
wire [5:0] J3_q;
wire RBG2;
wire E5_14=!(H4 & H2 & H1);
wire [3:0] D4_2_y;
wire C4_11=(D4_2_y[2] & D4_2_y[0]);
wire [3:0] B2_y,C2_y,B3_y;
wire [11:0] VA;
wire Phi2=Phi;
wire NMION = J4_q[7];
wire explode = J4_q[5];
wire fire = J4_q[4];
wire motor_hi = J4_q[3];
wire motor_on = J4_q[2];
wire nNMI = ~(VBLANK & NMION);
//end wire & reg setup
assign vid_hs = ~nHSYNC;
assign vid_vs = ~nVSYNC;
assign vid_hb = H256star;
assign vid_vb = VBLANK;
////wires
wire nDIPSW,F4_o9,F4_o8,F4_o6,nIN1,nIN0,nWDR,nOUT1,nOUT0;
wire [7:0] rom1a_dout,rom1b_dout,rom1c_dout,rom1d_dout;
wire [7:0] ram1e1j_dout,ram1f1k_dout,ram1h1l_dout,vram_dout,bullet_dout;
wire DIP_Y,IN1_Y,IN0_Y;
//start of address decoding
wire nPhi2,nWO,C4_6,nROM;
assign nROM=!A[13];
wire [3:0] C3_1_y;
ls139 icC3_1(
.a(A[11]),
.b(A[12]),
.n_g(nROM),
.y(C3_1_y)
);
wire nROM_A1_cs = C3_1_y[0];
wire nROM_B1_cs = C3_1_y[1];
wire nROM_C1_cs = C3_1_y[2];
wire nROM_D1_cs = C3_1_y[3];
wire [3:0] C3_2_y,D4_1_y;
assign nPhi2=~Phi2;
wire E4_3=!(nROM & H2);
assign C4_6=(E4_3 & C3_2_y[1]);
ls139 icC3_2(
.a(r_w),
.b(1'b0),
.n_g(A[13]),
.y(C3_2_y)
);
assign nWO=C3_2_y[0];
ls139 icD4_1(
.a(A[10]),
.b(A[11]),
.n_g(C4_6),
.y(D4_1_y)
);
wire nVRAM=D4_1_y[2];
wire nWRAM1=D4_1_y[1];
wire nWRAM0=D4_1_y[0];
ls42 icF4(
.in({D4_1_y[3],nWO,A[4],A[3]}),
.out({F4_o9,F4_o8,nDIPSW,F4_o6,nIN1,nIN0,nWDR,nINTACK,nOUT1,nOUT0})
);
//end address decode
//start horizontal timer
ls107 icA6_1(
.clear(PUR),
.clk(~clk),
.j(A6_2_nq),
.k(PUR),
.q(A6_1_q),
.qnot(A6_1_nq)
);
ls107 icA6_2(
.clear(PUR),
.clk(~clk),
.j(A6_1_q),
.k(PUR),
.q(A6_2_q),
.qnot(A6_2_nq)
);
ls74 icA5(
.n_pre1(PUR),
.n_pre2(PUR),
.n_clr1(PUR),
.n_clr2(H256),
.clk1(M6Hz),
.clk2(H16),
.d1(A5_1_nq),
.d2(A5_2_d),
.q1(H1),
.n_q1(A5_1_nq),
.q2(),
.n_q2(nHSYNC)
);
ls161 icB6(
.n_clr(PUR),
.clk(M6Hz),
.din(4'b0),
.enp(H1),
.ent(H1),
.n_load(PUR),
.q({H16,H8,H4,H2}),
.rco(B6_ca)
);
ls161 icC6(
.n_clr(PUR),
.clk(M6Hz),
.din(4'b0100),
.enp(B6_ca),
.ent(B6_ca),
.n_load(~C6_ca),
.q({nH256,H128,H64,H32}),
.rco(C6_ca)
);
//end horizontal timer
//start vertical timer
ls74 icD5(
.n_pre1(PUR),
.n_pre2(PUR),
.n_clr1(PUR),
.n_clr2(PUR),
.clk1(H8),
.clk2(nHSYNC),
.d1(H256),
.d2(D5_2_nq),
.q1(H256star),
.n_q1(nH256star),
.q2(V1),
.n_q2(D5_2_nq)
);
ls161 icD6(
.n_clr(PUR),
.clk(nHSYNC),
.din(4'b1100),
.enp(V1),
.ent(V1),
.n_load(~E6_ca),
.q({V16,V8,V4,V2}),
.rco(D6_ca)
);
ls161 icE6(
.n_clr(PUR),
.clk(nHSYNC),
.din(4'b0111),
.enp(D6_ca),
.ent(D6_ca),
.n_load(~E6_ca),
.q({nVSYNC,V128,V64,V32}),
.rco(E6_ca)
);
//end vertical timer
//vblank
ls74 icF5(
.n_pre1(PUR),
.n_pre2(nINTACK),
.n_clr1(PUR),
.n_clr2(PUR),
.clk1(V16),
.clk2(V16),
.d1(F5_1_d),
.d2(1'b0),
.q1(),
.n_q1(VBLANK),
.q2(nIRQ),
.n_q2()
);
//end vblank
//start screen render 3
wire [7:0] dsp_din;
ls273 icL2(
.d(dsp_din),
.clk(H4),
.res(PUR),
.q(L2_q)
);
k3 k3(
.clk(clk),
.addr({L2_q,V4,V2,V1}),
.data(K2_d)
);
ls166 icJ2(
.clk(M6Hz),
.load(C4_11),
.in(K2_d),
.out(J2_q)
);
//end of screen render 3
//start of screen render 4
ls174 icJ3(
.d(L2_q[7:2]),
.clk(C4_11),
.mr(PUR),
.q(J3_q)
);
wire vid_i;
l3 l3(
.clk(clk),
.addr({J3_q[5:0],E3_q,J2_q}),
.data({vid_b,vid_g,vid_r,vid_i})
);
//end of screen render 4
//screen render 1a
ls139 icD4_2(
.a(H256),
.b(H256star),
.n_g(E5_14),
.y(D4_2_y)
);
//end of screen render 1a
//start of address buffers
wire C4_3=(1'b1 & H256);//nPhi2 - 1'b1
ls157 icB2(
.i0({4{1'b0}}),
.i1({PUR,1'b0,V128,V64}),
.n_e(C4_3),//1'b0
.s(1'b1),
.z(B2_y)
);
assign VA[11]=B2_y[3];
assign VA[10]=B2_y[2];
assign VA[9]=B2_y[1];
assign VA[8]=B2_y[0];
ls157 icC2(
.i0({4{1'b0}}),
.i1({V32,V16,V8,H128}),
.n_e(C4_3),//
.s(1'b1),
.z(C2_y)
);
assign VA[7]=C2_y[3];
assign VA[6]=C2_y[2];
assign VA[5]=C2_y[1];
assign VA[4]=C2_y[0];
ls157 icB3(
.i0({4{1'b0}}),
.i1({H64,H32,H16,H8}),
.n_e(1'b0),
.s(1'b1),
.z(B3_y)
);
assign VA[3]=B3_y[3];
assign VA[2]=B3_y[2];
assign VA[1]=B3_y[1];
assign VA[0]=B3_y[0];
//end of address buffers
//start of video out
assign vid_cs = nCOMPSYNC;
//end of video out
//start of cpuclk
wire cpu_clken;
clock cpu_clk1(
.clk(clk),
.rst_n(nRESET),
.Phi2(Phi2),
.cpu_clken(cpu_clken)
);
//end of cpuclk
//CPU 6502
wire [15:0] A;
wire r_w;
wire [7:0] cpudata_in,cpudata_out;
T65 T65(
.Res_n(nRESET),
.Enable(cpu_clken),
.Clk(clk),
.Rdy(1),
.IRQ_n(nIRQ),
.NMI_n(nNMI),
.R_W_n(r_w),
.A(A),
.DI(cpudata_in),
.DO(cpudata_out)
);
//end of CPU 6502
//start of ROMs
a1 a1(
.clk(clk),
.addr(A[10:0]),
.data(rom1a_dout)
);
b1 b1(
.clk(clk),
.addr(A[10:0]),
.data(rom1b_dout)
);
c1 c1(
.clk(clk),
.addr(A[10:0]),
.data(rom1c_dout)
);
d1 d1(
.clk(clk),
.addr(A[10:0]),
.data(rom1d_dout)
);
//end of ROMs
//start RAMs
ram2114_DP icE1_J1( //a is cpu side, b is display side - WRAM0
.data_a(cpudata_out),
.data_b(),
.addr_a(A[10:0]),
.addr_b(VA[10:0]),
.we_a(!nWO & !nWRAM0),
.we_b(1'b0),
.clk(clk),
.q_a(ram1e1j_dout),
.q_b(bullet_dout)
);
ram2114 icF1_K1(
.data(cpudata_out),
.addr(A[10:0]),
.we(!nWO & !nWRAM1),
.clk(clk),
.q(ram1f1k_dout)
);
ram2114_DP icH1_L1( //a is cpu side, b is display side
.data_a(cpudata_out),
.data_b(),
.addr_a(A[10:0]),
.addr_b(VA[10:0]),
.we_a(!nWO & !nVRAM),
.we_b(1'b0),
.clk(clk),
.q_a(ram1h1l_dout),
.q_b(vram_dout)
);
//end RAMs
//start of Address muxing
assign cpudata_in = !nROM_A1_cs ? rom1a_dout :
!nROM_B1_cs ? rom1b_dout :
!nROM_C1_cs ? rom1c_dout :
!nROM_D1_cs ? rom1d_dout :
!nWRAM0 ? ram1e1j_dout :
!nWRAM1 ? ram1f1k_dout :
!nVRAM ? ram1h1l_dout :
!nDIPSW ? {DIP_Y,7'b0000000} :
!nIN0 ? {IN0_Y,7'b0000000} :
!nIN1 ? {IN1_Y,7'b0000000} :
8'hFF;
wire nWRAM0_VA = (VA[11:4] == 8'b00000000);
wire nVRAM_VA = (VA[11:10] == 2'b10);
assign dsp_din = nWRAM0_VA ? bullet_dout :
nVRAM_VA ? vram_dout :
8'hFF;
//end of Address muxing
//bullet render 2
wire F3_out,E4_11,H3_ca;
wire [3:0] H3_sigma,H2_sigma;
assign F3_out=!(H256 & H2_sigma[3] & H2_sigma[2] & H2_sigma[1] & H2_sigma[0] & H3_sigma[3] & H3_sigma[2] & E4_11);
ls283 icH3(
.a({V8,V4,V2,V1}),
.b(L2_q[3:0]),
.c_in(1'b0),
.sum(H3_sigma),
.c_out(H3_ca)
);
ls283 icH2(
.a({V128,V64,V32,V16}),
.b(L2_q[7:4]),
.c_in(H3_ca),
.sum(H2_sigma),
.c_out()
);
wire D2_d,E3_1_nq,E3_q;
assign E4_11=!(H3_sigma[1] & H3_sigma[0]);
ls74 icE3(
.n_pre1(PUR),
.n_pre2(PUR),
.n_clr1(PUR),
.n_clr2(nH256star),
.clk1(H8),
.clk2(nM6PRI),
.d1(F3_out),
.d2(D2_d),
.q1(),
.n_q1(E3_1_nq),
.q2(E3_q),
.n_q2()
);
wire E4_6,E5_out;
assign E4_6=!(H2 & H1);
assign E5_out=!(E3_1_nq & nH4_nH8 & E4_6);
//end of bullet render 2
//bullet render 1
wire [3:0] F2_q,E2_q;
wire F2_ca;
wire C5_3=(H256star & E5_out);
ls163 icF2(
.n_clr(D4_2_y[2]),
.clk(M6Hz),
.din(L2_q[3:0]),
.enp(1'b1),
.ent(1'b1),
.n_load(D4_2_y[3]),
.q(F2_q),
.rco(F2_ca)
);
ls163 icE2(
.n_clr(D4_2_y[2]),
.clk(M6Hz),
.din(L2_q[7:4]),
.enp(F2_ca),
.ent(F2_ca),
.n_load(D4_2_y[3]),
.q(E2_q),
.rco()
);
ram8125 icD2(
.di(H256star),
.addr({E2_q,F2_q}),
.we(!M6Hz),
.clk(clk),
.cs(!C5_3),
.q(D2_d)
);
//end of bullet render 1
//start of peripherals
ls251 icF7(
.CBA(A[2:0]),
.s(nDIPSW),
.D(DSW),
.Y(DIP_Y),
.W()
);
ls251 icD7(
.CBA(A[2:0]),
.s(nIN1),
.D(P2),
.Y(IN1_Y),
.W()
);
ls251 icE7(
.CBA(A[2:0]),
.s(nIN0),
.D(P1),
.Y(IN0_Y),
.W()
);
wire [7:0] J4_q;
ls259 icJ4(
.A(A[2:0]),
.nE(nOUT1),
.nC(nRESET),
.D(cpudata_out[0]),
.Q(J4_q)
);
//end of peripherals
//start of sound
wire [15:0] wav1_amp;
wire [15:0] wav2_amp;
wire [15:0] wav3_amp;
sound #(52095,"rom/explode.txt") wav1
(
.clk(CLK_18M),
.trigger(explode),//needs to be the explosion latch
.RESET_n(RESET_n),
.sound_out(wav1_amp)
);
sound #(21791,"rom/fire.txt") wav2
(
.clk(CLK_18M),
.trigger(fire),//needs to be the fire latch
.RESET_n(RESET_n),
.sound_out(wav2_amp)
);
EngineSound EngineSound(
.Clk_6(CLK_6M),
.Reset(motor_on),
.highrpm(motor_hi),
.Motor(wav3_amp[14:9])
);
// Audio mixer
// -----------
// - Combine discrete audio circuit and wave output, then invert
wire signed [15:0] sound_combined = 16'hFFFF - (wav1_amp + wav2_amp + wav3_amp);
assign audio = sound_combined; //can just use sound combined if no pause
//end of sound
endmodule

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Arcade_MiST/Namco Tank_Battalion/rtl/build_id.tcl Normal file
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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

29
Arcade_MiST/Namco Tank_Battalion/rtl/clock.v Normal file
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module clock(
input clk,
input rst_n,
input Phi2,
output cpu_clken
);
wire ff1_out;
ls74 LS74
(
.n_pre1(1'b1),
.n_pre2(),
.n_clr1(1'b1),
.n_clr2(),
.clk1(clk),
.clk2(),
.d1(Phi2),
.d2(),
.q1(ff1_out),
.q2(),
.n_q1(),
.n_q2()
);
wire int1 = (Phi2 ^ ff1_out);
assign cpu_clken = (Phi2 & int1);
endmodule

4
Arcade_MiST/Namco Tank_Battalion/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

376
Arcade_MiST/Namco Tank_Battalion/rtl/pll.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire4 = sub_wire0[2:2];
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire c2 = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire6),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 52,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 71,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 375,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 256,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 508,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 71,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "52"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "508"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.865383"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "18.431999"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "3.773622"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "71"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "2"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "71"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.86400000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "18.43200000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "3.77000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "52"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "375"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "256"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "508"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "71"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

170
Arcade_MiST/Namco Tank_Battalion/rtl/ram.v Normal file
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@@ -0,0 +1,170 @@
module ram2114
(
input [7:0] data,
input [10:0] addr,
input we,clk,
output [7:0] q
);
reg [7:0] ram[2047:0];
reg [10:0] addr_reg;
//RAM initialization Option 1 - Fill
initial
begin : INIT
integer i;
for(i = 0; i < 2048; i = i + 1)
ram[i] = {8{1'b0}};
end
always @ (posedge clk)
begin
// Write
if (we)//!
ram[addr] <= data;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule
module ram2114_DP
(
input [7:0] data_a, data_b,
input [10:0] addr_a, addr_b,
input we_a, we_b, clk,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[2047:0];
initial
begin : INIT
integer i;
for(i = 0; i < 2048; i = i + 1)
ram[i] = {8{1'b0}};
end
// Port A
always @ (posedge clk)
begin
if (we_a) //!
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
if (we_b) //
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
else
begin
q_b <= ram[addr_b];
end
end
endmodule
//New Modules
module ram8125
(
input di,
input [7:0] addr,
input we,clk,cs,
output q
);
reg ram[0:1023];
reg [7:0] addr_reg;
initial
begin : INIT
integer i;
for(i = 0; i < 1024; i = i + 1)
ram[i] = 1'b0;
end
always @ (posedge clk)
begin
// Write
if (we && cs)
ram[addr] <= di;
addr_reg <= addr;
end
assign q = ram[addr_reg];
endmodule
/*============================================================================
Generic single-port RAM module
Author: Jim Gregory - https://github.com/JimmyStones/
Version: 1.0
Date: 2022-01-28
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>.
===========================================================================*/
`timescale 1 ps / 1 ps
module spram # (
parameter address_width = 8,
parameter data_width = 8,
parameter init_file= ""
)
(
input clk,
input [(address_width-1):0] address,
input [(data_width-1):0] data,
output reg [(data_width-1):0] q,
input wren
);
localparam ramLength = (2**address_width);
reg [(data_width-1):0] mem [ramLength-1:0];
initial begin
if (init_file>0) $readmemh(init_file, mem);
end
always @(posedge clk)
begin
if (wren)
begin
mem[address] <= data;
q <= data;
end
else
begin
q <= mem[address];
end
end
endmodule

150
Arcade_MiST/Namco Tank_Battalion/rtl/rom/a1.vhd Normal file
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@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity a1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of a1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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X"E8",X"0A",X"09",X"B0",X"B0",X"C3",X"BE",X"B9",X"BF",X"B3",X"B0",X"A2",X"C8",X"09",X"09",X"B0",
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X"C2",X"B3",X"B0",X"A2",X"E8",X"0A",X"12",X"B0",X"B0",X"B0",X"B0",X"B0",X"B0",X"B0",X"B0",X"B0",
X"C9",X"B1",X"BC",X"C0",X"B0",X"B5",X"B5",X"C2",X"B6",X"EA",X"0A",X"05",X"C3",X"C5",X"BE",X"BF",
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X"C4",X"BF",X"BE",X"EC",X"0A",X"04",X"BB",X"BE",X"B1",X"C4",X"3B",X"0B",X"14",X"A0",X"A8",X"A9",
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X"3A",X"4D",X"53",X"54",X"31",X"32",X"38",X"0D",X"4D",X"53",X"54",X"31",X"32",X"31",X"09",X"54",
X"59",X"41",X"0D",X"09",X"43",X"4C",X"43",X"0D",X"09",X"41",X"44",X"43",X"09",X"5A",X"20",X"3A",
X"4D",X"42",X"55",X"46",X"41",X"44",X"4C",X"0D",X"09",X"41",X"4E",X"44",X"09",X"49",X"20",X"2F",
X"31",X"46",X"48",X"0D",X"09",X"43",X"4D",X"50",X"09",X"49",X"20",X"2F",X"32",X"0D",X"09",X"42",
X"45",X"51",X"09",X"52",X"20",X"3A",X"4D",X"53",X"54",X"31",X"32",X"38",X"0D",X"09",X"43",X"4D",
X"50",X"09",X"49",X"20",X"2F",X"31",X"44",X"48",X"0D",X"09",X"42",X"4E",X"45",X"09",X"52",X"20",
X"3A",X"4D",X"53",X"54",X"45",X"4E",X"31",X"0D",X"4D",X"53",X"54",X"31",X"32",X"38",X"09",X"4C",
X"44",X"41",X"09",X"49",X"20",X"2F",X"31",X"30",X"48",X"0D",X"09",X"52",X"54",X"53",X"0D",X"4D",
X"53",X"54",X"31",X"30",X"33",X"09",X"49",X"4E",X"59",X"0D",X"4D",X"53",X"54",X"31",X"30",X"34",
X"09",X"49",X"4E",X"58",X"0D",X"4D",X"53",X"54",X"45",X"4E",X"31",X"09",X"4C",X"44",X"41",X"09",
X"49",X"59",X"3A",X"4D",X"42",X"55",X"46",X"41",X"44",X"4C",X"0D",X"09",X"43",X"4D",X"50",X"09",
X"49",X"20",X"2F",X"31",X"31",X"48",X"0D",X"09",X"42",X"43",X"43",X"09",X"52",X"20",X"3A",X"4D",
X"53",X"54",X"31",X"30",X"32",X"0D",X"09",X"43",X"4D",X"50",X"09",X"49",X"20",X"2F",X"39",X"30",
X"48",X"0D",X"09",X"42",X"43",X"53",X"09",X"52",X"20",X"3A",X"4D",X"53",X"54",X"31",X"30",X"32",
X"0D",X"09",X"4C",X"44",X"41",X"09",X"49",X"20",X"2F",X"30",X"0D",X"4D",X"53",X"54",X"31",X"30",
X"32",X"09",X"52",X"54",X"53",X"0D",X"3B",X"0D",X"4D",X"53",X"31",X"30",X"58",X"09",X"54",X"58");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Namco Tank_Battalion/rtl/rom/b1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity b1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of b1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"20",X"A1",X"6F",X"20",X"B8",X"7B",X"2C",X"0F",X"0C",X"30",X"49",X"A9",X"01",X"8D",X"00",X"0C",
X"8D",X"01",X"0C",X"20",X"A2",X"79",X"20",X"F8",X"7C",X"90",X"25",X"A0",X"01",X"20",X"75",X"77",
X"F0",X"1E",X"A5",X"B5",X"30",X"04",X"C6",X"B5",X"D0",X"E1",X"A0",X"01",X"B9",X"0D",X"0C",X"10",
X"0F",X"B9",X"05",X"0C",X"10",X"0A",X"88",X"10",X"F3",X"A0",X"00",X"2C",X"07",X"0C",X"30",X"07",
X"98",X"29",X"01",X"A8",X"A9",X"01",X"2C",X"A9",X"00",X"99",X"08",X"0C",X"20",X"A1",X"7E",X"20",
X"82",X"70",X"F0",X"AC",X"20",X"96",X"6F",X"20",X"B2",X"6F",X"20",X"26",X"70",X"20",X"85",X"70",
X"2C",X"0F",X"0C",X"10",X"F5",X"60",X"20",X"96",X"6F",X"20",X"00",X"68",X"20",X"B2",X"6F",X"E6",
X"C7",X"A5",X"CA",X"85",X"A4",X"58",X"A5",X"CB",X"F0",X"08",X"20",X"45",X"6C",X"20",X"13",X"6E",
X"F0",X"09",X"20",X"45",X"6C",X"20",X"64",X"6E",X"20",X"23",X"6F",X"20",X"27",X"71",X"20",X"54",
X"73",X"20",X"C9",X"6F",X"20",X"78",X"6C",X"A5",X"B8",X"D0",X"06",X"20",X"2A",X"71",X"A2",X"01",
X"2C",X"A2",X"00",X"8E",X"0A",X"0C",X"A2",X"01",X"8E",X"0F",X"0C",X"A2",X"FF",X"86",X"5E",X"A5",
X"8B",X"C5",X"2C",X"F0",X"FA",X"85",X"2C",X"C6",X"59",X"C6",X"5A",X"A2",X"00",X"A5",X"59",X"D0",
X"03",X"8E",X"0D",X"0C",X"A5",X"5A",X"D0",X"03",X"8E",X"0C",X"0C",X"A5",X"5C",X"F0",X"0F",X"C6",
X"5C",X"A5",X"5C",X"A2",X"01",X"29",X"08",X"D0",X"02",X"A2",X"00",X"8E",X"09",X"0C",X"A9",X"00",
X"85",X"14",X"A2",X"0A",X"B5",X"3C",X"F0",X"37",X"E6",X"14",X"20",X"C4",X"73",X"B5",X"47",X"86",
X"24",X"10",X"70",X"29",X"7F",X"D0",X"36",X"8A",X"0A",X"AA",X"A0",X"00",X"20",X"57",X"74",X"9D",
X"60",X"02",X"20",X"55",X"74",X"9D",X"60",X"02",X"A0",X"20",X"20",X"56",X"74",X"9D",X"60",X"02",
X"20",X"55",X"74",X"9D",X"60",X"02",X"A9",X"14",X"20",X"16",X"74",X"A6",X"24",X"F6",X"47",X"CA",
X"CA",X"10",X"C1",X"4C",X"FC",X"6A",X"A9",X"18",X"AC",X"A9",X"1C",X"D0",X"EB",X"C9",X"09",X"F0",
X"F5",X"C9",X"12",X"F0",X"F4",X"C9",X"1B",X"D0",X"E4",X"8A",X"0A",X"AA",X"A0",X"00",X"BD",X"60",
X"02",X"91",X"28",X"E8",X"C8",X"BD",X"60",X"02",X"91",X"28",X"A0",X"20",X"E8",X"BD",X"60",X"02",
X"91",X"28",X"E8",X"C8",X"BD",X"60",X"02",X"91",X"28",X"A6",X"24",X"A0",X"00",X"94",X"3C",X"94",
X"47",X"F0",X"BC",X"D0",X"5E",X"38",X"B5",X"3B",X"E9",X"21",X"B0",X"02",X"D6",X"3C",X"95",X"3B",
X"20",X"C6",X"73",X"20",X"64",X"74",X"A0",X"03",X"20",X"2C",X"74",X"9D",X"00",X"02",X"E8",X"88",
X"10",X"F6",X"20",X"6E",X"74",X"C6",X"23",X"D0",X"ED",X"38",X"A5",X"28",X"E9",X"5F",X"B0",X"02",
X"C6",X"29",X"85",X"28",X"A9",X"18",X"4C",X"18",X"69",X"A2",X"20",X"2C",X"A2",X"30",X"A0",X"04",
X"84",X"23",X"A0",X"03",X"8A",X"91",X"28",X"AA",X"E8",X"88",X"10",X"F8",X"20",X"6E",X"74",X"C6",
X"23",X"D0",X"EF",X"4C",X"1B",X"69",X"A0",X"00",X"20",X"FE",X"6C",X"A0",X"20",X"20",X"FE",X"6C",
X"4C",X"59",X"69",X"C9",X"09",X"F0",X"D2",X"C9",X"12",X"F0",X"D1",X"C9",X"1B",X"F0",X"CA",X"C9",
X"24",X"F0",X"07",X"C9",X"60",X"F0",X"DF",X"4C",X"1D",X"69",X"20",X"64",X"74",X"A0",X"03",X"BD",
X"00",X"02",X"91",X"28",X"E8",X"88",X"10",X"F7",X"20",X"6E",X"74",X"C6",X"23",X"D0",X"EE",X"A6",
X"24",X"B5",X"48",X"10",X"0E",X"29",X"40",X"F0",X"07",X"A9",X"EC",X"85",X"2E",X"20",X"05",X"74",
X"4C",X"5B",X"69",X"18",X"B5",X"3B",X"69",X"21",X"90",X"02",X"F6",X"3C",X"95",X"3B",X"20",X"C6",
X"73",X"B5",X"48",X"AA",X"24",X"B5",X"10",X"03",X"09",X"70",X"2C",X"09",X"60",X"A0",X"00",X"91",
X"28",X"A0",X"20",X"18",X"69",X"01",X"91",X"28",X"E0",X"0A",X"D0",X"09",X"A9",X"80",X"20",X"34",
X"76",X"A9",X"80",X"D0",X"03",X"BD",X"25",X"6C",X"20",X"34",X"76",X"C6",X"A5",X"E6",X"A7",X"20",
X"76",X"6D",X"86",X"8E",X"4C",X"1B",X"69",X"20",X"0D",X"6D",X"A9",X"00",X"8D",X"0F",X"0C",X"A5",
X"B8",X"D0",X"0E",X"A0",X"D9",X"A2",X"61",X"20",X"9A",X"73",X"A0",X"E0",X"A2",X"61",X"20",X"9A",
X"73",X"20",X"94",X"70",X"A5",X"B8",X"F0",X"76",X"24",X"13",X"70",X"21",X"C6",X"A4",X"F0",X"1D",
X"A5",X"A7",X"85",X"A6",X"C9",X"14",X"90",X"07",X"20",X"22",X"71",X"A9",X"00",X"85",X"90",X"A9",
X"00",X"85",X"A5",X"A5",X"B4",X"F0",X"5F",X"20",X"57",X"6C",X"4C",X"A1",X"68",X"24",X"B5",X"10",
X"14",X"A0",X"69",X"A2",X"61",X"20",X"9A",X"73",X"A0",X"E7",X"A2",X"61",X"20",X"9A",X"73",X"A0",
X"EE",X"A2",X"61",X"D0",X"1D",X"A0",X"4A",X"A2",X"61",X"20",X"9A",X"73",X"A4",X"B5",X"F0",X"07",
X"A0",X"3C",X"A2",X"61",X"20",X"9A",X"73",X"A0",X"D9",X"A2",X"61",X"20",X"9A",X"73",X"A0",X"E0",
X"A2",X"61",X"20",X"9A",X"73",X"A9",X"80",X"A4",X"B5",X"F0",X"01",X"4A",X"05",X"B4",X"C9",X"C0",
X"D0",X"12",X"A5",X"B5",X"D0",X"05",X"20",X"C9",X"6F",X"30",X"03",X"20",X"CC",X"6F",X"20",X"9A",
X"70",X"4C",X"6C",X"68",X"85",X"B4",X"A2",X"00",X"A5",X"B5",X"D0",X"08",X"A2",X"7F",X"24",X"CD",
X"10",X"02",X"A2",X"FF",X"86",X"B5",X"20",X"6E",X"6C",X"4C",X"A1",X"68",X"A5",X"53",X"05",X"54",
X"F0",X"56",X"F8",X"18",X"A2",X"FD",X"B5",X"56",X"75",X"A3",X"95",X"A3",X"E8",X"D0",X"F7",X"D8",
X"A9",X"00",X"85",X"53",X"85",X"54",X"A5",X"9F",X"30",X"09",X"A5",X"A1",X"C5",X"CC",X"90",X"03",
X"20",X"94",X"6D",X"A2",X"03",X"CA",X"30",X"1B",X"B5",X"A0",X"D5",X"C3",X"90",X"15",X"F0",X"F5",
X"B5",X"A0",X"95",X"C3",X"CA",X"10",X"F9",X"24",X"B5",X"10",X"05",X"20",X"FA",X"71",X"D0",X"03",
X"20",X"E2",X"71",X"A2",X"02",X"A5",X"B5",X"F0",X"07",X"10",X"0A",X"20",X"EC",X"71",X"D0",X"08",
X"20",X"DC",X"71",X"D0",X"03",X"20",X"D4",X"71",X"A5",X"14",X"D0",X"22",X"A5",X"13",X"F0",X"03",
X"4C",X"47",X"6A",X"A5",X"A7",X"C9",X"14",X"90",X"15",X"20",X"0D",X"6D",X"A9",X"00",X"8D",X"0F",
X"0C",X"20",X"22",X"71",X"A9",X"00",X"85",X"90",X"20",X"57",X"6C",X"4C",X"A1",X"68",X"A5",X"8D",
X"C9",X"3C",X"90",X"0E",X"A9",X"00",X"85",X"8D",X"E6",X"8E",X"E6",X"8F",X"E6",X"91",X"D0",X"02",
X"E6",X"92",X"A5",X"92",X"D0",X"17",X"A0",X"01",X"A5",X"91",X"C9",X"14",X"F0",X"0A",X"C9",X"28",
X"F0",X"05",X"C9",X"3C",X"D0",X"07",X"C8",X"C8",X"84",X"26",X"20",X"53",X"71",X"A5",X"A6",X"C9",
X"14",X"B0",X"0E",X"A5",X"A5",X"C5",X"99",X"B0",X"08",X"A5",X"8E",X"C5",X"9A",X"90",X"02",X"66",
X"57",X"A5",X"13",X"D0",X"42",X"A0",X"04",X"A5",X"8B",X"29",X"20",X"F0",X"02",X"A0",X"00",X"84",
X"2E",X"20",X"05",X"74",X"2C",X"0F",X"0C",X"30",X"03",X"4C",X"43",X"7D",X"A5",X"B8",X"F0",X"2B",
X"A5",X"8B",X"29",X"10",X"F0",X"18",X"A5",X"B5",X"D0",X"06",X"A0",X"91",X"A2",X"60",X"D0",X"11",
X"30",X"06",X"A0",X"97",X"A2",X"60",X"D0",X"09",X"A0",X"9D",X"A2",X"60",X"D0",X"03",X"20",X"2E",
X"6C",X"20",X"9A",X"73",X"4C",X"AF",X"68",X"A5",X"B8",X"D0",X"F3",X"A0",X"D9",X"A2",X"61",X"20",
X"9A",X"73",X"A0",X"E0",X"A2",X"61",X"20",X"9A",X"73",X"A5",X"C0",X"F0",X"E1",X"A9",X"00",X"8D",
X"0F",X"0C",X"4C",X"6C",X"68",X"03",X"00",X"06",X"00",X"15",X"00",X"30",X"00",X"80",X"A5",X"B5",
X"D0",X"06",X"A0",X"A3",X"A2",X"60",X"D0",X"0C",X"30",X"06",X"A0",X"A9",X"A2",X"60",X"D0",X"04",
X"A0",X"AF",X"A2",X"60",X"60",X"20",X"06",X"70",X"20",X"EC",X"6D",X"4C",X"96",X"71",X"20",X"06",
X"70",X"20",X"FF",X"6D",X"4C",X"B6",X"71",X"20",X"9A",X"70",X"A5",X"B5",X"F0",X"08",X"20",X"CC",
X"6F",X"20",X"94",X"72",X"F0",X"62",X"20",X"C9",X"6F",X"20",X"8E",X"72",X"F0",X"0D",X"20",X"9A",
X"70",X"A5",X"B5",X"D0",X"4D",X"20",X"94",X"72",X"20",X"CC",X"6F",X"20",X"B5",X"6F",X"A5",X"B5",
X"D0",X"06",X"20",X"DC",X"6F",X"4C",X"8B",X"6C",X"20",X"DF",X"6F",X"A5",X"B8",X"F0",X"0D",X"20",
X"45",X"6C",X"20",X"8B",X"6E",X"24",X"90",X"30",X"0A",X"20",X"85",X"6E",X"20",X"0E",X"73",X"A9",
X"80",X"85",X"90",X"20",X"97",X"70",X"20",X"45",X"6C",X"20",X"EA",X"70",X"20",X"B1",X"6D",X"20",
X"49",X"6D",X"20",X"E8",X"6E",X"20",X"E9",X"6F",X"A5",X"B5",X"D0",X"03",X"4C",X"B8",X"72",X"4C",
X"BE",X"72",X"20",X"C9",X"6F",X"20",X"8E",X"72",X"24",X"B5",X"10",X"AF",X"20",X"B5",X"6F",X"20",
X"DF",X"6F",X"20",X"4E",X"6C",X"20",X"C3",X"6E",X"24",X"90",X"30",X"0A",X"20",X"A4",X"6E",X"20",
X"58",X"73",X"A9",X"80",X"85",X"90",X"20",X"97",X"70",X"20",X"4E",X"6C",X"20",X"EA",X"70",X"20",
X"A2",X"6D",X"20",X"40",X"6D",X"20",X"E3",X"6E",X"20",X"EF",X"6F",X"4C",X"BE",X"72",X"B1",X"28",
X"C9",X"11",X"90",X"04",X"C9",X"60",X"90",X"04",X"A9",X"00",X"91",X"28",X"60",X"A9",X"06",X"85",
X"8A",X"24",X"13",X"70",X"07",X"A9",X"00",X"85",X"2E",X"20",X"05",X"74",X"20",X"2E",X"6C",X"20",
X"9A",X"73",X"A5",X"8A",X"D0",X"FC",X"60",X"A2",X"09",X"A0",X"9E",X"86",X"29",X"84",X"28",X"A5",
X"A7",X"60",X"A2",X"0B",X"A0",X"80",X"86",X"29",X"84",X"28",X"A9",X"14",X"38",X"E5",X"A7",X"60",
X"20",X"32",X"6D",X"A2",X"FE",X"A0",X"FF",X"D0",X"07",X"20",X"27",X"6D",X"A2",X"CF",X"A0",X"CE",
X"85",X"26",X"84",X"24",X"86",X"25",X"A2",X"0A",X"A0",X"00",X"C6",X"26",X"30",X"03",X"A5",X"25",
X"2C",X"A5",X"24",X"91",X"28",X"C8",X"C0",X"02",X"90",X"F0",X"20",X"7A",X"74",X"CA",X"D0",X"E8",
X"60",X"20",X"32",X"6D",X"10",X"0A",X"24",X"B5",X"30",X"F7",X"20",X"27",X"6D",X"38",X"E9",X"01",
X"4A",X"A0",X"00",X"90",X"01",X"C8",X"AA",X"F0",X"06",X"20",X"7A",X"74",X"CA",X"D0",X"FA",X"A9",
X"CF",X"91",X"28",X"60",X"A9",X"80",X"85",X"9F",X"A9",X"49",X"85",X"5C",X"E6",X"A4",X"24",X"B5",
X"10",X"0F",X"A9",X"86",X"38",X"E5",X"A4",X"85",X"23",X"A0",X"60",X"A2",X"09",X"A9",X"48",X"D0",
X"0B",X"A6",X"A4",X"CA",X"86",X"23",X"A0",X"7E",X"A2",X"0B",X"A9",X"4C",X"84",X"28",X"86",X"29",
X"A2",X"05",X"86",X"24",X"85",X"25",X"A6",X"23",X"CA",X"30",X"10",X"A5",X"25",X"20",X"16",X"74",
X"20",X"7A",X"74",X"20",X"7A",X"74",X"C6",X"24",X"D0",X"EE",X"60",X"A9",X"00",X"A8",X"91",X"28",
X"C8",X"91",X"28",X"A0",X"20",X"91",X"28",X"C8",X"91",X"28",X"D0",X"E4",X"A2",X"60",X"A0",X"B5",
X"20",X"9A",X"73",X"A5",X"C9",X"D0",X"01",X"60",X"A2",X"60",X"A0",X"97",X"4C",X"9A",X"73",X"A2",
X"60",X"A0",X"CE",X"D0",X"F7",X"80",X"61",X"8A",X"61",X"A0",X"61",X"B1",X"61",X"B6",X"61",X"CA",
X"61",X"CF",X"61",X"A5",X"C0",X"D0",X"E0",X"A2",X"0C",X"86",X"5D",X"BC",X"05",X"6E",X"BD",X"06",
X"6E",X"AA",X"20",X"9A",X"73",X"A6",X"5D",X"CA",X"CA",X"10",X"EE",X"20",X"03",X"6F",X"A0",X"00",
X"84",X"2F",X"B9",X"25",X"6C",X"85",X"AB",X"A0",X"B5",X"A9",X"09",X"A2",X"0B",X"20",X"14",X"6F",
X"A9",X"A0",X"8D",X"95",X"09",X"20",X"94",X"70",X"8D",X"D5",X"09",X"8D",X"B5",X"09",X"8D",X"95",
X"09",X"20",X"A3",X"70",X"A4",X"2F",X"C8",X"C8",X"C0",X"0A",X"D0",X"D4",X"A9",X"AA",X"8D",X"B5",
X"09",X"A9",X"00",X"60",X"A2",X"60",X"A0",X"FC",X"20",X"9A",X"73",X"A6",X"CC",X"30",X"10",X"A2",
X"61",X"A0",X"10",X"20",X"9A",X"73",X"A0",X"72",X"A9",X"09",X"A2",X"2C",X"20",X"14",X"6F",X"A0",
X"2B",X"A2",X"61",X"D0",X"1C",X"A0",X"42",X"A2",X"61",X"D0",X"1D",X"A2",X"61",X"A0",X"4A",X"20",
X"9A",X"73",X"A5",X"B5",X"F0",X"07",X"A2",X"61",X"A0",X"3C",X"20",X"9A",X"73",X"A2",X"61",X"A0",
X"57",X"4C",X"9A",X"73",X"A2",X"61",X"A0",X"61",X"20",X"D0",X"6E",X"A5",X"B5",X"30",X"06",X"A0",
X"8E",X"A9",X"09",X"D0",X"5F",X"A0",X"51",X"A9",X"0A",X"84",X"2A",X"85",X"2B",X"A9",X"20",X"A0",
X"00",X"F0",X"59",X"A2",X"61",X"A0",X"69",X"20",X"9A",X"73",X"A0",X"76",X"A2",X"61",X"D0",X"D1",
X"20",X"9A",X"73",X"A5",X"B8",X"D0",X"03",X"A6",X"E3",X"2C",X"A6",X"A3",X"86",X"AA",X"A2",X"0A",
X"4C",X"A4",X"7B",X"20",X"E8",X"73",X"D0",X"03",X"20",X"D5",X"73",X"20",X"D3",X"6E",X"A5",X"B5",
X"10",X"06",X"A0",X"00",X"A9",X"0A",X"D0",X"C1",X"A0",X"DF",X"D0",X"B5",X"A2",X"60",X"A0",X"E7",
X"4C",X"9A",X"73",X"A5",X"CB",X"F0",X"F5",X"A2",X"60",X"A0",X"F3",X"20",X"9A",X"73",X"A2",X"20",
X"A0",X"7F",X"A9",X"0A",X"84",X"2A",X"85",X"2B",X"A9",X"E0",X"A0",X"20",X"85",X"25",X"A9",X"00",
X"4C",X"16",X"72",X"20",X"03",X"6F",X"A9",X"FF",X"85",X"B8",X"A5",X"CB",X"D0",X"0D",X"20",X"73",
X"77",X"D0",X"08",X"A2",X"03",X"20",X"A4",X"7B",X"20",X"E8",X"6E",X"A5",X"27",X"49",X"01",X"85",
X"27",X"A6",X"C0",X"E0",X"01",X"F0",X"03",X"8D",X"01",X"0C",X"8D",X"00",X"0C",X"A0",X"10",X"20",
X"B4",X"70",X"A6",X"C0",X"0E",X"0D",X"0C",X"6A",X"0E",X"0E",X"0C",X"6A",X"85",X"5F",X"24",X"5F",
X"50",X"0A",X"10",X"05",X"88",X"D0",X"E8",X"F0",X"BA",X"E0",X"02",X"AD",X"E0",X"01",X"A5",X"CB",
X"F0",X"02",X"90",X"F0",X"A0",X"00",X"70",X"02",X"A0",X"40",X"84",X"B4",X"84",X"C9",X"A5",X"CB",
X"F0",X"08",X"50",X"03",X"20",X"AE",X"7B",X"20",X"AE",X"7B",X"A2",X"FF",X"86",X"B8",X"E8",X"8E",
X"01",X"0C",X"8E",X"00",X"0C",X"60",X"A2",X"18",X"A9",X"00",X"9D",X"00",X"0C",X"CA",X"10",X"FA",
X"60",X"A2",X"F0",X"A9",X"00",X"CA",X"95",X"10",X"8D",X"18",X"0C",X"D0",X"F8",X"F0",X"12",X"A2",
X"00",X"2C",X"A2",X"C0",X"2C",X"A2",X"9F",X"A9",X"00",X"CA",X"95",X"00",X"8D",X"18",X"0C",X"D0",
X"F8",X"8E",X"09",X"0C",X"E8",X"8E",X"0A",X"0C",X"60",X"A9",X"87",X"2C",X"A9",X"9F",X"85",X"23",
X"A2",X"00",X"A9",X"90",X"A4",X"B8",X"F0",X"2D",X"A0",X"17",X"D0",X"1B",X"A9",X"D0",X"2C",X"A9",
X"E8",X"A2",X"00",X"A0",X"47",X"84",X"23",X"D0",X"EB",X"A2",X"66",X"A9",X"23",X"D0",X"04",X"A2",
X"66",X"A9",X"32",X"A0",X"0E",X"84",X"23",X"86",X"1F",X"85",X"1E",X"A6",X"23",X"B1",X"1E",X"95");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Namco Tank_Battalion/rtl/rom/c1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity c1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of c1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"60",X"CA",X"88",X"10",X"F8",X"60",X"A9",X"00",X"A2",X"0F",X"95",X"00",X"CA",X"10",X"FB",X"A9",
X"00",X"A0",X"0B",X"84",X"1F",X"A0",X"00",X"84",X"1E",X"A2",X"04",X"88",X"91",X"1E",X"D0",X"FB",
X"C6",X"1F",X"CA",X"D0",X"F6",X"60",X"A0",X"40",X"A2",X"08",X"84",X"28",X"86",X"29",X"A0",X"FF",
X"C8",X"A5",X"28",X"29",X"20",X"F0",X"03",X"A9",X"EA",X"2C",X"A9",X"DA",X"18",X"20",X"24",X"74",
X"C0",X"1F",X"90",X"EC",X"20",X"6E",X"74",X"A5",X"29",X"C9",X"0B",X"D0",X"E1",X"A5",X"28",X"C9",
X"C0",X"90",X"DB",X"60",X"20",X"5E",X"70",X"24",X"B5",X"10",X"02",X"49",X"FF",X"60",X"A9",X"02",
X"25",X"60",X"18",X"F0",X"01",X"38",X"A9",X"01",X"25",X"61",X"69",X"00",X"4A",X"66",X"61",X"66",
X"60",X"A9",X"4A",X"25",X"60",X"D0",X"06",X"A9",X"43",X"65",X"61",X"85",X"61",X"A5",X"60",X"85",
X"C2",X"60",X"A9",X"03",X"2C",X"A9",X"C0",X"85",X"1F",X"20",X"96",X"74",X"8D",X"18",X"0C",X"A5",
X"1F",X"D0",X"F6",X"60",X"A2",X"04",X"2C",X"A2",X"06",X"2C",X"A2",X"0D",X"20",X"A3",X"70",X"CA",
X"D0",X"FA",X"60",X"A9",X"01",X"8D",X"0A",X"0C",X"A9",X"00",X"8D",X"09",X"0C",X"8D",X"0C",X"0C",
X"8D",X"0D",X"0C",X"2C",X"A9",X"50",X"38",X"48",X"E9",X"01",X"D0",X"FC",X"68",X"E9",X"01",X"8D",
X"18",X"0C",X"08",X"48",X"AD",X"0F",X"0C",X"30",X"03",X"4C",X"43",X"7D",X"A5",X"B8",X"30",X"07",
X"A5",X"C0",X"F0",X"03",X"4C",X"1D",X"6C",X"68",X"28",X"D0",X"DC",X"60",X"A9",X"10",X"84",X"1E",
X"86",X"1F",X"A0",X"1B",X"91",X"1E",X"88",X"10",X"FB",X"60",X"A2",X"08",X"A0",X"42",X"20",X"DC",
X"70",X"A2",X"0B",X"A0",X"A2",X"20",X"DE",X"70",X"A0",X"82",X"20",X"FF",X"70",X"A0",X"9D",X"48",
X"84",X"1E",X"A0",X"0B",X"84",X"1F",X"A0",X"00",X"A2",X"1B",X"68",X"91",X"1E",X"48",X"20",X"AE",
X"74",X"CA",X"D0",X"F6",X"68",X"60",X"A5",X"A3",X"24",X"CE",X"30",X"05",X"F8",X"18",X"69",X"03",
X"D8",X"60",X"A2",X"03",X"20",X"A4",X"7B",X"20",X"B5",X"6F",X"85",X"26",X"20",X"16",X"71",X"C9",
X"0A",X"90",X"02",X"A9",X"09",X"0A",X"0A",X"0A",X"A8",X"A2",X"05",X"B9",X"CF",X"64",X"24",X"CF",
X"30",X"03",X"B9",X"1F",X"65",X"95",X"93",X"C8",X"CA",X"10",X"F0",X"A9",X"00",X"85",X"A5",X"85",
X"A6",X"85",X"A7",X"A5",X"93",X"20",X"90",X"71",X"BD",X"6F",X"65",X"85",X"99",X"A5",X"94",X"20",
X"90",X"71",X"BD",X"7F",X"65",X"85",X"9A",X"A5",X"96",X"20",X"90",X"71",X"BD",X"9F",X"65",X"85",
X"9C",X"A5",X"97",X"20",X"90",X"71",X"BD",X"AF",X"65",X"85",X"9D",X"A5",X"98",X"20",X"90",X"71",
X"BD",X"BF",X"65",X"85",X"9E",X"A5",X"95",X"20",X"90",X"71",X"BD",X"8F",X"65",X"85",X"9B",X"60",
X"0A",X"0A",X"65",X"26",X"AA",X"60",X"A9",X"A0",X"8D",X"A1",X"09",X"8D",X"C1",X"09",X"8D",X"E1",
X"0A",X"8D",X"01",X"0B",X"A4",X"C9",X"D0",X"09",X"8D",X"81",X"08",X"8D",X"A1",X"08",X"20",X"D2",
X"71",X"20",X"DA",X"71",X"30",X"2C",X"A9",X"D0",X"8D",X"3E",X"0A",X"8D",X"5E",X"0A",X"8D",X"FE",
X"08",X"8D",X"1E",X"09",X"8D",X"5E",X"0B",X"8D",X"7E",X"0B",X"20",X"EA",X"71",X"20",X"F2",X"71",
X"30",X"28",X"A2",X"5A",X"A9",X"A1",X"A0",X"08",X"D0",X"30",X"A2",X"42",X"A9",X"01",X"A0",X"0B",
X"D0",X"28",X"A2",X"25",X"A9",X"C1",X"A0",X"09",X"D0",X"20",X"A2",X"5A",X"A9",X"BE",X"A0",X"0A",
X"D0",X"0E",X"A2",X"42",X"A9",X"5E",X"A0",X"08",X"D0",X"06",X"A2",X"25",X"A9",X"9E",X"A0",X"09",
X"84",X"2B",X"A0",X"20",X"84",X"25",X"A0",X"00",X"F0",X"08",X"84",X"2B",X"A0",X"E0",X"84",X"25",
X"A0",X"A0",X"85",X"2A",X"A9",X"02",X"85",X"2D",X"A9",X"00",X"85",X"26",X"B5",X"A0",X"48",X"4A",
X"4A",X"4A",X"4A",X"20",X"38",X"72",X"A5",X"2D",X"D0",X"02",X"C6",X"26",X"68",X"29",X"0F",X"20",
X"38",X"72",X"CA",X"C6",X"2D",X"10",X"E5",X"60",X"F0",X"02",X"C6",X"26",X"24",X"B5",X"10",X"03",
X"09",X"D0",X"2C",X"09",X"A0",X"24",X"26",X"30",X"02",X"A9",X"00",X"91",X"2A",X"98",X"18",X"65",
X"25",X"A8",X"60",X"A5",X"1E",X"95",X"6D",X"A5",X"1F",X"95",X"6E",X"A5",X"1D",X"95",X"6C",X"60",
X"86",X"1F",X"84",X"1E",X"85",X"1D",X"A5",X"1D",X"0A",X"0A",X"65",X"18",X"A0",X"00",X"91",X"1E",
X"69",X"01",X"C8",X"91",X"1E",X"69",X"01",X"A0",X"20",X"91",X"1E",X"C8",X"69",X"01",X"91",X"1E",
X"60",X"84",X"21",X"86",X"22",X"A0",X"82",X"A2",X"0B",X"84",X"1E",X"86",X"1F",X"60",X"A0",X"80",
X"A2",X"02",X"D0",X"04",X"A0",X"40",X"A2",X"05",X"20",X"81",X"72",X"A0",X"1A",X"84",X"24",X"A4",
X"24",X"B1",X"1E",X"C9",X"11",X"90",X"02",X"A9",X"00",X"A0",X"00",X"20",X"8D",X"74",X"C6",X"24",
X"D0",X"ED",X"20",X"DE",X"72",X"D0",X"E4",X"60",X"A0",X"80",X"A2",X"02",X"D0",X"04",X"A0",X"40",
X"A2",X"05",X"20",X"81",X"72",X"A0",X"1A",X"84",X"24",X"A0",X"00",X"B1",X"21",X"A4",X"24",X"91",
X"1E",X"20",X"8F",X"74",X"C6",X"24",X"D0",X"F1",X"20",X"DE",X"72",X"D0",X"E8",X"60",X"20",X"AE",
X"74",X"C9",X"42",X"D0",X"04",X"A5",X"1F",X"C9",X"08",X"60",X"A5",X"C7",X"4C",X"FB",X"72",X"A5",
X"B8",X"F0",X"F7",X"A6",X"A3",X"E0",X"09",X"90",X"06",X"A5",X"C2",X"29",X"07",X"10",X"0A",X"BD",
X"F5",X"61",X"24",X"CF",X"30",X"03",X"BD",X"FE",X"61",X"0A",X"AA",X"60",X"C6",X"BA",X"20",X"EF",
X"72",X"BD",X"07",X"62",X"A8",X"BD",X"08",X"62",X"85",X"1F",X"84",X"1E",X"A0",X"80",X"A2",X"02",
X"A5",X"B5",X"D0",X"04",X"A5",X"BA",X"F0",X"04",X"A0",X"40",X"A2",X"05",X"84",X"21",X"86",X"22",
X"A0",X"00",X"A2",X"55",X"86",X"23",X"A2",X"08",X"B1",X"1E",X"85",X"24",X"06",X"24",X"A9",X"00",
X"90",X"02",X"A9",X"01",X"20",X"8D",X"74",X"CA",X"D0",X"F2",X"20",X"86",X"74",X"C6",X"23",X"D0",
X"E5",X"86",X"BA",X"60",X"24",X"CD",X"10",X"B4",X"20",X"EF",X"72",X"BD",X"17",X"62",X"A8",X"BD",
X"18",X"62",X"84",X"1E",X"85",X"1F",X"A0",X"40",X"A2",X"05",X"84",X"21",X"86",X"22",X"A0",X"00",
X"A2",X"55",X"86",X"23",X"A2",X"04",X"B1",X"1E",X"4A",X"4A",X"4A",X"4A",X"10",X"04",X"A2",X"08",
X"B1",X"1E",X"85",X"24",X"46",X"24",X"A9",X"00",X"90",X"02",X"A9",X"01",X"20",X"8D",X"74",X"CA",
X"D0",X"F2",X"20",X"96",X"74",X"C6",X"23",X"D0",X"E5",X"60",X"86",X"2B",X"84",X"2A",X"A0",X"00",
X"B1",X"2A",X"85",X"28",X"E6",X"2A",X"D0",X"02",X"E6",X"2B",X"B1",X"2A",X"85",X"29",X"E6",X"2A",
X"D0",X"02",X"E6",X"2B",X"B1",X"2A",X"A8",X"A2",X"00",X"B1",X"2A",X"81",X"28",X"20",X"7A",X"74",
X"88",X"D0",X"F6",X"60",X"B5",X"3B",X"85",X"28",X"B5",X"3C",X"85",X"29",X"60",X"A2",X"00",X"A9",
X"80",X"A0",X"0C",X"D0",X"26",X"A2",X"8A",X"8E",X"5E",X"0A",X"E8",X"8E",X"5F",X"0A",X"A0",X"1E",
X"84",X"28",X"A0",X"0A",X"A9",X"80",X"D0",X"11",X"A2",X"9A",X"8E",X"A0",X"09",X"E8",X"8E",X"A1",
X"09",X"A0",X"C0",X"84",X"28",X"A0",X"09",X"A9",X"90",X"A2",X"0C",X"86",X"2E",X"D0",X"12",X"A9",
X"90",X"A0",X"E3",X"D0",X"08",X"24",X"B5",X"30",X"F6",X"A9",X"80",X"A0",X"FB",X"84",X"28",X"A0",
X"09",X"84",X"29",X"18",X"65",X"2E",X"A0",X"00",X"18",X"91",X"28",X"C8",X"69",X"01",X"91",X"28",
X"A0",X"20",X"69",X"01",X"91",X"28",X"C8",X"69",X"01",X"91",X"28",X"60",X"A5",X"29",X"C9",X"0B",
X"D0",X"08",X"A5",X"28",X"C9",X"A2",X"90",X"0C",X"B0",X"18",X"C9",X"08",X"D0",X"06",X"A5",X"28",
X"C9",X"5E",X"90",X"0E",X"98",X"18",X"65",X"28",X"29",X"1F",X"C9",X"02",X"F0",X"04",X"C9",X"1D",
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X"A8",X"F0",X"34",X"88",X"88",X"30",X"3A",X"F0",X"40",X"A0",X"00",X"20",X"96",X"74",X"B1",X"1E",
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X"85",X"1B",X"A0",X"21",X"D0",X"BE",X"A8",X"F0",X"0F",X"88",X"88",X"30",X"14",X"F0",X"1B",X"20",
X"C9",X"74",X"20",X"46",X"75",X"F0",X"F8",X"60",X"20",X"F5",X"74",X"20",X"46",X"75",X"F0",X"F8",
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X"CA",X"10",X"E7",X"A5",X"9D",X"C5",X"8F",X"A9",X"01",X"60",X"A5",X"60",X"C5",X"9C",X"A9",X"01",
X"60",X"A4",X"6D",X"84",X"1E",X"A4",X"6E",X"84",X"1F",X"A4",X"6C",X"84",X"1D",X"F0",X"0F",X"88",
X"88",X"30",X"14",X"F0",X"1B",X"20",X"C9",X"74",X"20",X"AC",X"75",X"F0",X"F8",X"60",X"20",X"F5",
X"74",X"20",X"AC",X"75",X"F0",X"F8",X"60",X"20",X"01",X"75",X"20",X"AC",X"75",X"F0",X"F8",X"60",
X"20",X"09",X"75",X"20",X"AC",X"75",X"F0",X"F8",X"60",X"A9",X"00",X"60",X"F0",X"FB",X"A2",X"01",
X"B5",X"1B",X"C9",X"10",X"F0",X"0B",X"90",X"F1",X"29",X"F0",X"C9",X"50",X"F0",X"04",X"CA",X"10",
X"EF",X"18",X"A9",X"01",X"60",X"B5",X"00",X"18",X"69",X"03",X"49",X"F8",X"29",X"F8",X"85",X"1E",
X"A9",X"02",X"06",X"1E",X"2A",X"06",X"1E",X"2A",X"95",X"31",X"B5",X"01",X"4A",X"4A",X"4A",X"18",
X"65",X"1E",X"95",X"30",X"60",X"B5",X"31",X"85",X"1E",X"B5",X"30",X"46",X"1E",X"6A",X"46",X"1E",
X"6A",X"29",X"F8",X"49",X"F8",X"38",X"E9",X"01",X"95",X"00",X"B5",X"30",X"0A",X"0A",X"0A",X"18",
X"69",X"06",X"95",X"01",X"60",X"B5",X"6C",X"49",X"01",X"C5",X"1D",X"18",X"08",X"A5",X"37",X"69",
X"0B",X"4A",X"4A",X"4A",X"29",X"06",X"49",X"06",X"28",X"D0",X"10",X"69",X"02",X"C9",X"08",X"D0",
X"0A",X"A4",X"A7",X"C0",X"06",X"F0",X"09",X"C0",X"0C",X"F0",X"05",X"A6",X"58",X"95",X"48",X"60",
X"A9",X"0A",X"D0",X"F7",X"A4",X"B8",X"F0",X"0D",X"F8",X"18",X"65",X"53",X"85",X"53",X"A5",X"54",
X"69",X"00",X"85",X"54",X"D8",X"60",X"D5",X"01",X"D0",X"0F",X"98",X"D5",X"00",X"D0",X"0A",X"A9",
X"00",X"95",X"31",X"95",X"01",X"95",X"00",X"85",X"19",X"60",X"A9",X"08",X"A8",X"D0",X"03",X"A9",
X"04",X"A8",X"85",X"19",X"84",X"1A",X"B5",X"36",X"C9",X"02",X"90",X"01",X"E8",X"29",X"01",X"F0",
X"08",X"B5",X"00",X"38",X"E5",X"1A",X"95",X"00",X"60",X"A5",X"19",X"18",X"75",X"00",X"95",X"00",
X"60",X"B5",X"30",X"85",X"1E",X"B5",X"31",X"85",X"1F",X"B5",X"36",X"85",X"1D",X"29",X"02",X"D0",
X"03",X"A0",X"01",X"2C",X"A0",X"20",X"B1",X"1E",X"84",X"1A",X"85",X"1C",X"A0",X"00",X"84",X"19",
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X"F0",X"03",X"A9",X"1A",X"2C",X"A9",X"11",X"2C",X"A9",X"08",X"2C",X"A9",X"FF",X"18",X"75",X"1B",
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X"02",X"D0",X"03",X"A9",X"08",X"2C",X"A9",X"10",X"E0",X"00",X"F0",X"03",X"38",X"E9",X"04",X"A8",
X"8A",X"49",X"01",X"AA",X"B5",X"1B",X"85",X"20",X"88",X"B9",X"13",X"66",X"30",X"06",X"C5",X"20",
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X"85",X"1C",X"A5",X"1D",X"A0",X"00",X"29",X"02",X"D0",X"0E",X"C4",X"1B",X"F0",X"06",X"A0",X"02",
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X"D0",X"ED",X"86",X"19",X"A2",X"0A",X"B5",X"3C",X"F0",X"04",X"CA",X"CA",X"10",X"F8",X"60",X"A5",
X"B8",X"F0",X"0E",X"A2",X"00",X"24",X"B5",X"10",X"02",X"A2",X"08",X"BD",X"04",X"0C",X"29",X"80",
X"60",X"20",X"71",X"75",X"90",X"09",X"20",X"5E",X"70",X"C9",X"D0",X"90",X"02",X"A9",X"00",X"60",
X"A4",X"1D",X"C0",X"01",X"D0",X"03",X"20",X"AE",X"74",X"C0",X"02",X"D0",X"03",X"20",X"96",X"74",
X"A5",X"1E",X"95",X"3B",X"A5",X"1F",X"95",X"3C",X"60",X"A5",X"B8",X"F0",X"07",X"A9",X"1F",X"85",
X"59",X"8D",X"0D",X"0C",X"60",X"20",X"06",X"77",X"F0",X"03",X"4C",X"41",X"78",X"20",X"37",X"77",
X"30",X"26",X"20",X"A0",X"77",X"86",X"58",X"A6",X"19",X"D0",X"0C",X"A9",X"80",X"A6",X"58",X"95",
X"48",X"05",X"13",X"85",X"13",X"D0",X"03",X"20",X"05",X"76",X"20",X"A9",X"77",X"A9",X"00",X"A6",
X"19",X"95",X"6E",X"10",X"7A",X"20",X"64",X"77",X"30",X"75",X"A9",X"C0",X"95",X"48",X"85",X"13",
X"20",X"A9",X"77",X"A5",X"6A",X"95",X"3B",X"A5",X"6B",X"95",X"3C",X"D0",X"62",X"A6",X"16",X"4C");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

150
Arcade_MiST/Namco Tank_Battalion/rtl/rom/d1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity d1 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of d1 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"5F",X"76",X"A6",X"16",X"20",X"C5",X"75",X"20",X"81",X"76",X"F0",X"35",X"29",X"F0",X"A4",X"16",
X"F0",X"0A",X"E0",X"40",X"D0",X"0E",X"C9",X"40",X"D0",X"0A",X"F0",X"99",X"E0",X"50",X"D0",X"04",
X"C9",X"50",X"F0",X"91",X"C9",X"A0",X"B0",X"08",X"E0",X"90",X"F0",X"B9",X"E0",X"80",X"F0",X"B5",
X"A2",X"01",X"B5",X"1B",X"F0",X"08",X"C9",X"10",X"90",X"2B",X"C9",X"40",X"90",X"21",X"CA",X"10",
X"F1",X"A9",X"FF",X"85",X"19",X"A6",X"16",X"B5",X"01",X"B4",X"00",X"A6",X"17",X"20",X"46",X"76",
X"A6",X"16",X"B5",X"01",X"B4",X"00",X"A6",X"18",X"20",X"46",X"76",X"A5",X"19",X"D0",X"9E",X"A6",
X"16",X"20",X"4F",X"76",X"60",X"A2",X"01",X"20",X"B0",X"76",X"B0",X"39",X"85",X"21",X"A2",X"00",
X"20",X"B0",X"76",X"B0",X"30",X"A8",X"10",X"1C",X"A5",X"21",X"10",X"18",X"A9",X"00",X"A8",X"91",
X"1E",X"98",X"A4",X"1A",X"91",X"1E",X"20",X"64",X"77",X"30",X"D4",X"20",X"90",X"77",X"A9",X"80",
X"95",X"47",X"D0",X"CB",X"98",X"10",X"02",X"49",X"FF",X"A0",X"00",X"91",X"1E",X"A5",X"21",X"10",
X"02",X"49",X"FF",X"10",X"DD",X"20",X"DD",X"76",X"B0",X"03",X"4C",X"41",X"78",X"86",X"21",X"20",
X"B0",X"76",X"10",X"02",X"A9",X"00",X"A6",X"21",X"B4",X"19",X"10",X"C8",X"B5",X"6C",X"85",X"1D",
X"85",X"20",X"B5",X"6D",X"85",X"1E",X"85",X"21",X"B4",X"6E",X"84",X"1F",X"84",X"22",X"60",X"A5",
X"22",X"C5",X"1C",X"F0",X"04",X"B0",X"17",X"90",X"12",X"A2",X"80",X"A5",X"1B",X"29",X"E0",X"85",
X"17",X"A5",X"21",X"29",X"E0",X"C5",X"17",X"F0",X"07",X"B0",X"03",X"A2",X"01",X"2C",X"A2",X"00",
X"86",X"17",X"A2",X"80",X"A5",X"1B",X"29",X"1F",X"85",X"18",X"A5",X"21",X"29",X"1F",X"C5",X"18",
X"F0",X"07",X"B0",X"03",X"A2",X"02",X"2C",X"A2",X"03",X"86",X"18",X"20",X"54",X"70",X"29",X"01",
X"AA",X"B5",X"17",X"30",X"09",X"C5",X"20",X"F0",X"1A",X"20",X"BE",X"74",X"90",X"28",X"8A",X"49",
X"01",X"AA",X"B5",X"17",X"30",X"0D",X"C5",X"20",X"F0",X"09",X"A6",X"22",X"A4",X"21",X"20",X"BA",
X"74",X"90",X"13",X"A5",X"20",X"A6",X"22",X"A4",X"21",X"20",X"BA",X"74",X"B0",X"11",X"A5",X"61",
X"C5",X"9E",X"B0",X"0B",X"90",X"46",X"20",X"5E",X"70",X"C5",X"9B",X"B0",X"E6",X"90",X"40",X"20",
X"54",X"70",X"08",X"A5",X"20",X"28",X"30",X"03",X"49",X"03",X"2C",X"49",X"02",X"A6",X"22",X"A4",
X"21",X"20",X"BA",X"74",X"90",X"29",X"A5",X"1D",X"49",X"01",X"A6",X"22",X"A4",X"21",X"20",X"BA",
X"74",X"90",X"1C",X"A5",X"20",X"49",X"01",X"A6",X"22",X"A4",X"21",X"20",X"BA",X"74",X"90",X"0F",
X"A5",X"20",X"A6",X"22",X"A4",X"21",X"85",X"1D",X"84",X"1E",X"86",X"1F",X"A9",X"80",X"2C",X"A9",
X"00",X"85",X"58",X"0A",X"A8",X"91",X"21",X"C8",X"91",X"21",X"A0",X"20",X"91",X"21",X"C8",X"91",
X"21",X"60",X"A0",X"03",X"A2",X"04",X"24",X"B5",X"10",X"02",X"A2",X"0C",X"CA",X"BD",X"00",X"0C",
X"0A",X"90",X"04",X"88",X"10",X"F6",X"60",X"BD",X"BC",X"79",X"A8",X"60",X"03",X"01",X"02",X"00",
X"FF",X"FF",X"FF",X"FF",X"02",X"00",X"03",X"01",X"A2",X"00",X"20",X"BC",X"78",X"A9",X"E3",X"85",
X"1B",X"A9",X"09",X"85",X"1C",X"20",X"CF",X"78",X"4C",X"48",X"7A",X"48",X"98",X"48",X"8A",X"48",
X"E6",X"8D",X"E6",X"8B",X"20",X"A2",X"79",X"B0",X"02",X"84",X"5E",X"A5",X"8B",X"29",X"07",X"D0",
X"66",X"A5",X"6E",X"F0",X"5F",X"A5",X"B8",X"F0",X"CF",X"20",X"A2",X"79",X"90",X"0C",X"A9",X"FF",
X"A4",X"5E",X"85",X"5E",X"30",X"12",X"C4",X"6C",X"F0",X"0E",X"C4",X"6C",X"D0",X"0C",X"98",X"A6",
X"6E",X"A4",X"6D",X"20",X"BA",X"74",X"90",X"18",X"A4",X"6C",X"A6",X"6D",X"A5",X"6E",X"84",X"1D",
X"86",X"1E",X"85",X"1F",X"A5",X"5B",X"F0",X"04",X"C6",X"5B",X"10",X"0D",X"A9",X"00",X"F0",X"06",
X"A9",X"04",X"85",X"5B",X"A9",X"01",X"8D",X"0B",X"0C",X"A9",X"00",X"A8",X"91",X"6D",X"C8",X"91",
X"6D",X"A0",X"20",X"91",X"6D",X"C8",X"91",X"6D",X"A2",X"00",X"A0",X"40",X"84",X"18",X"20",X"66",
X"72",X"20",X"53",X"72",X"4C",X"21",X"7B",X"85",X"1D",X"0A",X"18",X"65",X"1D",X"AA",X"85",X"16",
X"B5",X"6E",X"D0",X"41",X"24",X"57",X"10",X"EC",X"20",X"5E",X"70",X"29",X"01",X"0A",X"AA",X"A1",
X"62",X"F0",X"08",X"8A",X"49",X"02",X"AA",X"A1",X"62",X"D0",X"D9",X"E6",X"A6",X"E6",X"A5",X"A9",
X"00",X"85",X"57",X"85",X"8E",X"B5",X"63",X"85",X"1F",X"A9",X"63",X"24",X"B5",X"10",X"02",X"A9",
X"7B",X"85",X"1E",X"20",X"5E",X"70",X"29",X"01",X"F0",X"01",X"E8",X"B5",X"66",X"85",X"1D",X"A6",
X"16",X"A0",X"50",X"D0",X"A7",X"A5",X"8B",X"29",X"08",X"D0",X"76",X"20",X"BC",X"78",X"F0",X"05",
X"8A",X"29",X"01",X"F0",X"0A",X"A4",X"6A",X"84",X"1B",X"A4",X"6B",X"84",X"1C",X"D0",X"06",X"84",
X"1C",X"A4",X"6D",X"84",X"1B",X"20",X"CF",X"78",X"A6",X"16",X"A0",X"50",X"84",X"18",X"20",X"66",
X"72",X"20",X"53",X"72",X"48",X"20",X"16",X"71",X"A8",X"68",X"C0",X"12",X"B0",X"0C",X"24",X"CF",
X"30",X"04",X"C0",X"06",X"B0",X"04",X"24",X"58",X"10",X"37",X"A4",X"8A",X"D0",X"33",X"20",X"16",
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X"31",X"30",X"32",X"0D",X"09",X"42",X"45",X"51",X"09",X"52",X"20",X"3A",X"53",X"54",X"50",X"31",
X"30",X"35",X"0D",X"09",X"4A",X"53",X"52",X"09",X"41",X"20",X"3A",X"53",X"42",X"32",X"30",X"41",
X"44",X"31",X"0D",X"53",X"54",X"50",X"31",X"30",X"32",X"09",X"4A",X"53",X"52",X"09",X"41",X"20",
X"3A",X"44",X"45",X"43",X"41",X"86",X"09",X"49",X"1E",X"0A",X"DB",X"79",X"43",X"7D",X"6C",X"7C");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

52096
Arcade_MiST/Namco Tank_Battalion/rtl/rom/explode.txt Normal file
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21792
Arcade_MiST/Namco Tank_Battalion/rtl/rom/fire.txt Normal file
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150
Arcade_MiST/Namco Tank_Battalion/rtl/rom/k3.vhd Normal file
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@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity k3 is
port (
clk : in std_logic;
addr : in std_logic_vector(10 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of k3 is
type rom is array(0 to 2047) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"E0",X"EE",X"EE",X"EE",X"0E",X"EE",X"EE",
X"EE",X"E0",X"EE",X"EE",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"EE",X"0E",X"EE",X"EE",
X"0E",X"00",X"0E",X"0E",X"0E",X"0E",X"0E",X"0E",X"E0",X"E0",X"E0",X"E0",X"E0",X"00",X"E0",X"E0",
X"E0",X"E0",X"E0",X"E0",X"00",X"00",X"00",X"00",X"0E",X"00",X"0E",X"0E",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"E0",X"00",X"E0",X"E0",X"00",X"00",X"00",X"00",X"0E",X"0E",X"0E",X"0E",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"02",X"02",X"FE",X"FE",X"42",X"02",X"00",X"00",X"78",X"FC",X"96",X"92",X"92",X"F2",X"60",X"00",
X"0C",X"6E",X"9A",X"9A",X"B2",X"F2",X"6C",X"00",X"38",X"7C",X"C2",X"82",X"86",X"7C",X"38",X"00",
X"AA",X"55",X"AA",X"55",X"AA",X"55",X"AA",X"55",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"02",X"22",X"3B",X"1F",X"09",X"1E",X"00",X"00",X"08",X"50",X"70",X"E0",X"78",X"30",
X"06",X"0D",X"1F",X"32",X"04",X"00",X"00",X"00",X"60",X"F0",X"B8",X"E8",X"44",X"00",X"00",X"00",
X"40",X"70",X"3B",X"1F",X"1D",X"0B",X"0E",X"7C",X"00",X"02",X"4E",X"FC",X"C8",X"7C",X"38",X"30",
X"0E",X"1F",X"1D",X"0B",X"1F",X"32",X"60",X"00",X"78",X"38",X"EC",X"F8",X"6C",X"66",X"02",X"00",
X"8E",X"64",X"79",X"3F",X"97",X"9D",X"38",X"75",X"53",X"86",X"8C",X"DD",X"FD",X"69",X"10",X"BF",
X"FC",X"19",X"DF",X"BB",X"7F",X"64",X"C0",X"9C",X"B8",X"3C",X"5E",X"F0",X"F9",X"DC",X"B6",X"B3",
X"00",X"00",X"04",X"04",X"08",X"10",X"A0",X"C0",X"00",X"00",X"00",X"08",X"02",X"78",X"FE",X"D6",
X"00",X"00",X"28",X"38",X"24",X"00",X"1C",X"7F",X"00",X"00",X"20",X"30",X"18",X"09",X"0D",X"03",
X"00",X"08",X"E4",X"F0",X"B0",X"60",X"E0",X"C0",X"AB",X"FD",X"FE",X"7F",X"77",X"2F",X"4F",X"E3",
X"67",X"DB",X"FE",X"FE",X"FD",X"6D",X"F1",X"D7",X"04",X"04",X"09",X"11",X"01",X"07",X"0F",X"1B",
X"B0",X"F4",X"66",X"B4",X"B6",X"61",X"C0",X"80",X"CF",X"AF",X"17",X"A7",X"F3",X"DF",X"FF",X"E7",
X"7B",X"F6",X"E8",X"E6",X"FE",X"B6",X"6D",X"FF",X"1D",X"1B",X"0D",X"1E",X"1D",X"0F",X"03",X"00",
X"30",X"40",X"A0",X"90",X"48",X"04",X"00",X"00",X"FA",X"BC",X"7C",X"F8",X"E2",X"04",X"00",X"00",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

38
Arcade_MiST/Namco Tank_Battalion/rtl/rom/l3.vhd Normal file
View File

@@ -0,0 +1,38 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity l3 is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of l3 is
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
X"0",X"2",X"E",X"2",X"0",X"2",X"E",X"2",X"0",X"2",X"E",X"2",X"0",X"3",X"E",X"3",
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X"0",X"3",X"E",X"3",X"0",X"3",X"E",X"3",X"0",X"3",X"E",X"3",X"0",X"3",X"E",X"3",
X"0",X"F",X"E",X"F",X"0",X"F",X"E",X"F",X"0",X"F",X"E",X"F",X"0",X"F",X"E",X"F",
X"0",X"7",X"E",X"7",X"0",X"7",X"E",X"7",X"0",X"7",X"E",X"7",X"0",X"7",X"E",X"7",
X"0",X"C",X"E",X"C",X"0",X"C",X"E",X"C",X"0",X"C",X"E",X"C",X"0",X"C",X"E",X"C",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",
X"0",X"7",X"E",X"7",X"0",X"7",X"E",X"7",X"0",X"7",X"E",X"7",X"0",X"A",X"E",X"A",
X"0",X"B",X"E",X"B",X"0",X"B",X"E",X"B",X"0",X"7",X"E",X"7",X"0",X"A",X"E",X"A",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"3",X"E",X"3",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"C",X"E",X"C",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"3",X"E",X"3",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",
X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"E",X"E",X"E",X"0",X"C",X"E",X"C");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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Arcade_MiST/Namco Tank_Battalion/rtl/sound_FSM.v Normal file
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module sound # (
parameter wav_length= 16'd38174;
parameter init_file= ""
)
(
input clk,
input trigger,
input RESET_n,
output signed [15:0] sound_out
);
reg sndclk = 1'b0;
always @(posedge clk) begin
sndclk <= ~sndclk;
end
reg wav_playing = 1'b0;
wire wav_play;
reg [WAV_COUNTER_SIZE-1:0] wav_counter;
localparam WAV_COUNTER_SIZE = 10;//10
localparam WAV_COUNTER_MAX = 100;//1000
reg signed [7:0] wav_signed;
// Wave player
reg [15:0] wave_rom_addr;
wire [7:0] wave_rom_data_out;
reg [15:0] wave_rom_length = wav_length;
spram #(14,8,init_file) wave_rom //should be 64k here not enough BRAM but it works
(
.clk(clk),
.address(wave_rom_addr),
.wren(1'b0),
.data(),
.q(wave_rom_data_out)
);
clock trig1(
.clk(sndclk),
.rst_n(),
.Phi2(trigger),
.cpu_clken(wav_play)
);
// States
localparam STOP = 0, START = 1, PLAY = 2;
reg [1:0] state = STOP;
always @(posedge clk)
begin
case (state)
STOP : begin
wav_signed <= 8'b0;
wave_rom_addr <= 16'b0; //reset the rom address
wav_counter <= WAV_COUNTER_MAX; // put the wav counter to the maximum
if(wav_play)
begin//wav_play is trigger to play it
state <= START;
//wav_play <= 1'b0;
end
end
START : begin
wav_signed <= 8'b0;
wave_rom_addr <= 16'b0; //reset the rom address
wav_counter <= WAV_COUNTER_MAX; // put the wav counter to the maximum
wav_playing <= 1'b1; //make wav_playing 1
state <= PLAY;
end
PLAY : begin
wav_counter <= wav_counter - 1'b1; //reduce the wav counter by one bit.
if(wav_play)
begin//wav_play is trigger to play it
state <= START;
//wav_play <= 1'b0;
end
if(wav_counter == {WAV_COUNTER_SIZE{1'b0}})// if wav counter is zero.
begin
if(wave_rom_addr < wave_rom_length) // if wave rom address is below wave rom length (38174)
begin
wav_signed <= wave_rom_data_out; //wav signed is wave rom data out
wave_rom_addr <= wave_rom_addr + 16'b1; //wave rom address is incremented by 1 bit
wav_counter <= {WAV_COUNTER_SIZE{1'b1}}; //wav counter is? check this!
end
else //if wave rom address in NOT below wave rom length
begin
state <= STOP;
end
end
end
endcase
end
wire signed [15:0] wav_amplified = { wav_signed[7], {1{wav_signed[7]}}, wav_signed[6:0], {7{wav_signed[7]}} }; //create 16 bit from 8 bit wav
assign sound_out = wav_amplified;
endmodule

621
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//74LS74 Chip pinout:
/* _____________
_| |_
n_clr1 |_|1 14|_| VCC
_| |_
d1 |_|2 13|_| n_clr2
_| |_
clk1 |_|3 12|_| d2
_| |_
n_pre1 |_|4 11|_| clk2
_| |_
q1 |_|5 10|_| n_pre2
_| |_
n_q1 |_|6 9|_| q2
_| |_
GND |_|7 8|_| n_q2
|_____________|
*/
module ls74
(
input n_pre1, n_pre2,
input n_clr1, n_clr2,
input clk1, clk2,
input d1, d2,
output reg q1, q2,
output n_q1, n_q2
);
always @(posedge clk1 or negedge n_pre1 or negedge n_clr1) begin
if(!n_pre1)
q1 <= 1;
else if(!n_clr1)
q1 <= 0;
else
q1 <= d1;
end
assign n_q1 = ~q1;
always @(posedge clk2 or negedge n_pre2 or negedge n_clr2) begin
if(!n_pre2)
q2 <= 1;
else if(!n_clr2)
q2 <= 0;
else
q2 <= d2;
end
assign n_q2 = ~q2;
endmodule
//74LS107 Chip pinout:
/* _____________
_| |_
1J |_|1 14|_| VCC
_| |_
1nQ |_|2 13|_| 1nCLR
_| |_
1Q |_|3 12|_| 1CK
_| |_
1K |_|4 11|_| 2K
_| |_
2Q |_|5 10|_| 2nCLR
_| |_
2nQ |_|6 9|_| 2CK
_| |_
GND |_|7 8|_| 2J
|_____________|
*/
module ls107(
input clear,
input clk,
input j,
input k,
output reg q,
output qnot
);
assign qnot=~q;
always @(negedge clk or negedge clear) begin
if (!clear) q<=1'b0; else
case ({j, k})
2'b00: q<=q;
2'b01: q<=1'b0;
2'b10: q<=1'b1;
2'b11: q<=~q;
endcase
end
endmodule
//74LS161 Chip pinout:
/* _____________
_| |_
n_clr |_|1 16|_| VCC
_| |_
clk |_|2 15|_| rco
_| |_
din(0) |_|3 14|_| q(0)
_| |_
din(1) |_|4 13|_| q(1)
_| |_
din(2) |_|5 12|_| q(2)
_| |_
din(3) |_|6 11|_| q(3)
_| |_
enp |_|7 10|_| ent
_| |_
GND |_|8 9|_| n_load
|_____________|
*/
module ls161 //asynchronous reset/clear
(
input n_clr,
input clk,
input [3:0] din,
input enp, ent,
input n_load,
output [3:0] q,
output rco
);
reg [3:0] data = 4'b0;
always @(posedge clk or negedge n_clr) begin
if(!n_clr)
data <= 4'd0;
else
if(!n_load)
data <= din;
else if(enp && ent)
data <= data + 4'd1;
end
assign q = data;
assign rco = data[0] & data[1] & data[2] & data[3] & ent;
endmodule
//74LS273 Chip pinout:
/* _____________
_| |_
res |_|1 20|_| VCC
_| |_
q(0) |_|2 19|_| q(7)
_| |_
d(0) |_|3 18|_| d(7)
_| |_
d(1) |_|4 17|_| d(6)
_| |_
q(1) |_|5 16|_| q(6)
_| |_
q(2) |_|6 15|_| q(5)
_| |_
d(2) |_|7 14|_| d(5)
_| |_
d(3) |_|8 13|_| d(4)
_| |_
q(3) |_|9 12|_| q(4)
_| |_
GND |_|10 11|_| clk
|_____________|
*/
module ls273
(
input [7:0] d,
input clk,
input res,
output reg [7:0] q
);
always @(posedge clk or negedge res) begin
if(!res)
q <= 8'h00;
else
q <= d;
end
endmodule
//74LS166 Chip pinout:
/* _____________
_| |_
serial input |_|1 16|_| VCC
_| |_
parra in A |_|2 15|_| shift/load
_| |_
parra in B |_|3 14|_| parra in H
_| |_
parra in C |_|4 13|_| serial output
_| |_
parra in D |_|5 12|_| parra in G
_| |_
CLK inhibit |_|6 11|_| parra in F
_| |_
CLK |_|7 10|_| parra in E
_| |_
GND |_|8 9|_| clear
|_____________|
*/
module ls166
(
input clk,
input load,
input [7:0] in,
output out
);
reg [7:0]tmp;
always @(posedge clk)
begin
if (!load)
tmp <= in;
else
tmp <= {tmp[6:0], 1'b0};
end
assign out = tmp[7];
endmodule
//74LS174 Chip pinout:
/* _____________
_| |_
mr |_|1 16|_| VCC
_| |_
q(0) |_|2 15|_| q(5)
_| |_
d(0) |_|3 14|_| d(5)
_| |_
d(1) |_|4 13|_| d(4)
_| |_
q(1) |_|5 12|_| q(4)
_| |_
d(2) |_|6 11|_| d(3)
_| |_
q(2) |_|7 10|_| q(3)
_| |_
GND |_|8 9|_| clk
|_____________|
*/
module ls174
(
input [5:0] d,
input clk,
input mr,
output reg [5:0] q
);
always @(posedge clk or negedge mr) begin
if(!mr)
q <= 6'b000000;
else
q <= d;
end
endmodule
//74LS139 Chip pinout:
/* _____________
_| |_
1n_G |_|1 16|_| VCC
_| |_
1A |_|2 15|_| 2n_G
_| |_
1B |_|3 14|_| 2A
_| |_
1Y0 |_|4 13|_| 2B
_| |_
1Y1 |_|5 12|_| 2Y0
_| |_
1Y2 |_|6 11|_| 2Y1
_| |_
1Y3 |_|7 10|_| 2Y2
_| |_
GND |_|8 9|_| 2Y3
|_____________|
*/
module ls139
(
input a,
input b,
input n_g,
output [3:0] y
);
assign y = (!n_g && !a && !b) ? 4'b1110:
(!n_g && a && !b) ? 4'b1101:
(!n_g && !a && b) ? 4'b1011:
(!n_g && a && b) ? 4'b0111:
4'b1111;
endmodule
//Chip pinout:
/* _____________
_| |_
s |_|1 16|_| VCC
_| |_
i0(0) |_|2 15|_| n_e
_| |_
i1(0) |_|3 14|_| i0(2)
_| |_
z(0) |_|4 13|_| i1(2)
_| |_
i0(1) |_|5 12|_| z(2)
_| |_
i1(1) |_|6 11|_| i0(3)
_| |_
z(1) |_|7 10|_| i1(3)
_| |_
GND |_|8 9|_| z(3)
|_____________|
*/
module ls157
(
input [3:0] i0,
input [3:0] i1,
input n_e,
input s,
output [3:0] z
);
assign z = (!n_e && !s) ? i0:
(!n_e && s) ? i1:
4'b0000;
endmodule
module ls42
(
input [3:0] in,
output reg [9:0] out
);
// in = [DCBA]
// out = [9876543210]
always @ (*)
case (in)
4'b0000: out = 10'b1111111110;
4'b0001: out = 10'b1111111101;
4'b0010: out = 10'b1111111011;
4'b0011: out = 10'b1111110111;
4'b0100: out = 10'b1111101111;
4'b0101: out = 10'b1111011111;
4'b0110: out = 10'b1110111111;
4'b0111: out = 10'b1101111111;
4'b1000: out = 10'b1011111111;
4'b1001: out = 10'b0111111111;
4'b1010: out = 10'b1111111111;
4'b1011: out = 10'b1111111111;
4'b1100: out = 10'b1111111111;
4'b1101: out = 10'b1111111111;
4'b1110: out = 10'b1111111111;
4'b1111: out = 10'b1111111111;
default: out = 10'b1111111111;
endcase
endmodule
//New Modules
//Chip pinout:
/* _____________
_| |_
n_clr |_|1 16|_| VCC
_| |_
clk |_|2 15|_| rco
_| |_
din(0) |_|3 14|_| q(0)
_| |_
din(1) |_|4 13|_| q(1)
_| |_
din(2) |_|5 12|_| q(2)
_| |_
din(3) |_|6 11|_| q(3)
_| |_
enp |_|7 10|_| ent
_| |_
GND |_|8 9|_| n_load
|_____________|
*/
module ls163 //synchronous reset/clear
(
input n_clr,
input clk,
input [3:0] din,
input enp, ent,
input n_load,
output [3:0] q,
output rco
);
reg [3:0] data = 4'b0;
always @(posedge clk) begin
if(!n_clr)
data <= 4'd0;
else
if(!n_load)
data <= din;
else if(enp && ent)
data <= data + 4'd1;
end
assign q = data;
assign rco = data[0] & data[1] & data[2] & data[3] & ent;
endmodule
//Chip pinout:
/* _____________
_| |_
a1 |_|1 14|_| VCC
_| |_
b1 |_|2 13|_| c1
_| |_
a2 |_|3 12|_| y1
_| |_
b2 |_|4 11|_| a3
_| |_
c2 |_|5 10|_| b3
_| |_
y2 |_|6 9|_| c3
_| |_
GND |_|7 8|_| y3
|_____________|
*/
module ls10
(
input a1, a2, a3,
input b1, b2, b3,
input c1, c2, c3,
output y1, y2, y3
);
assign y1 = ~(a1 & b1 & c1);
assign y2 = ~(a2 & b2 & c2);
assign y3 = ~(a3 & b3 & c3);
endmodule
//Chip pinout:
/* _____________
_| |_
a1 |_|1 14|_| VCC
_| |_
b1 |_|2 13|_| a4
_| |_
y1 |_|3 12|_| b4
_| |_
a2 |_|4 11|_| y4
_| |_
b2 |_|5 10|_| a3
_| |_
y2 |_|6 9|_| b3
_| |_
GND |_|7 8|_| y3
|_____________|
*/
module ls08
(
input a1, a2, a3, a4,
input b1, b2, b3, b4,
output y1, y2, y3, y4
);
assign y1 = a1 & b1;
assign y2 = a2 & b2;
assign y3 = a3 & b3;
assign y4 = a4 & b4;
endmodule
//Chip pinout:
/* _____________
_| |_
sum(1) |_|1 16|_| VCC
_| |_
b(1) |_|2 15|_| b(2)
_| |_
a(1) |_|3 14|_| a(2)
_| |_
sum(0) |_|4 13|_| sum(2)
_| |_
a(0) |_|5 12|_| a(3)
_| |_
b(0) |_|6 11|_| b(3)
_| |_
c_in |_|7 10|_| sum(3)
_| |_
GND |_|8 9|_| c_out
|_____________|
*/
module ls283
(
input [3:0] a,
input [3:0] b,
input c_in,
output [3:0] sum,
output c_out
);
wire [4:0] sum_int;
assign sum_int = {1'b0, a} + {1'b0, b} + {4'b0000, c_in};
assign sum = sum_int[3:0];
assign c_out = sum_int[4];
endmodule
//Chip pinout:
/* _____________
_| |_
D(3) |_|1 16|_| VCC
_| |_
D(2) |_|2 15|_| D(4)
_| |_
D(1) |_|3 14|_| D(5)
_| |_
D(0) |_|4 13|_| D(6)
_| |_
Y |_|5 12|_| D(7)
_| |_
W |_|6 11|_| A
_| |_
S |_|7 10|_| B
_| |_
GND |_|8 9|_| C
|_____________|
*/
module ls251
(
input [2:0] CBA,
input s,
input [7:0] D,
output reg Y,W
);
always @ (CBA,s)
begin
if (!s) begin
case (CBA)
3'b000: Y=D[0];
3'b001: Y=D[1];
3'b010: Y=D[2];
3'b011: Y=D[3];
3'b100: Y=D[4];
3'b101: Y=D[5];
3'b110: Y=D[6];
3'b111: Y=D[7];
default: Y=1'bZ;
endcase
W <=!Y;
end
else begin
Y <= 1'bZ;
W <= 1'bZ;
end
end
endmodule
module ls259
(
input [2:0] A,
input nE,
input nC,
input D,
output reg [7:0] Q
);
always @ (nE,nC,D,A)
begin
if (!nC && nE) begin
Q[7:0] <= 8'b00000000;
end
else if (!nC && !nE && !D) begin
Q[7:0] <= 8'b00000000;
end
else if (!nC && !nE && D) begin
case (A)
3'b000: Q[7:0]=8'b00000001;
3'b001: Q[7:0]=8'b00000010;
3'b010: Q[7:0]=8'b00000100;
3'b011: Q[7:0]=8'b00001000;
3'b100: Q[7:0]=8'b00010000;
3'b101: Q[7:0]=8'b00100000;
3'b110: Q[7:0]=8'b01000000;
3'b111: Q[7:0]=8'b10000000;
default: Q[7:0]=8'bZZZZZZZZ;
endcase
end
else if (nC && nE) begin
//no change
end
else if (nC && !nE) begin
case (A)
3'b000: Q[0]=D;
3'b001: Q[1]=D;
3'b010: Q[2]=D;
3'b011: Q[3]=D;
3'b100: Q[4]=D;
3'b101: Q[5]=D;
3'b110: Q[6]=D;
3'b111: Q[7]=D;
default: Q[7:0]=8'bZZZZZZZZ;
endcase
end
end
endmodule

108
common/CPU/6502_6510/ALU.v Normal file
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/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule

1244
common/CPU/6502_6510/cpu.v Normal file
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