mirror of
https://github.com/Gehstock/Mist_FPGA.git
synced 2026-04-03 20:12:50 +00:00
There is a better Version
This commit is contained in:
Marcel
@@ -1,30 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 12:11:46 March 17, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
QUARTUS_VERSION = "13.1"
|
||||
DATE = "12:11:46 March 17, 2019"
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "Laser310_MiST"
|
||||
@@ -1,433 +0,0 @@
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Quartus II 64-Bit
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
# Date created = 17:28:40 June 04, 2019
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
#
|
||||
# Notes:
|
||||
#
|
||||
# 1) The default values for assignments are stored in the file:
|
||||
# Laser310_MiST_assignment_defaults.qdf
|
||||
# If this file doesn't exist, see file:
|
||||
# assignment_defaults.qdf
|
||||
#
|
||||
# 2) Altera recommends that you do not modify this file. This
|
||||
# file is updated automatically by the Quartus II software
|
||||
# and any changes you make may be lost or overwritten.
|
||||
#
|
||||
# -------------------------------------------------------------------------- #
|
||||
|
||||
|
||||
|
||||
# Project-Wide Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014"
|
||||
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
|
||||
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
|
||||
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
|
||||
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
|
||||
set_global_assignment -name SMART_RECOMPILE ON
|
||||
set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/Laser310_MiST.sv
|
||||
set_global_assignment -name VERILOG_FILE rtl/LASER310_TOP.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/mc6847_vga.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/PIXEL_DISPLAY.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/CHAR_GEN.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/PIXEL_GEN.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/VIDEO_OUT.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SVGA_DEFINES.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/SVGA_TIMING_GENERATION.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/ps2_keyboard_glb.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80s.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80n.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_reg.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_mcode.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_core.v
|
||||
set_global_assignment -name VERILOG_FILE rtl/tv80/tv80_alu.v
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_top.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_tone.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_noise.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_latch_ctrl.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_clock_div.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sn76489/sn76489_attenuator.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/spram.vhd
|
||||
set_global_assignment -name VHDL_FILE rtl/pll.vhd
|
||||
set_global_assignment -name VERILOG_FILE rtl/reset_de.v
|
||||
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
|
||||
set_global_assignment -name TEXT_FILE rtl/tv80/Text1.txt
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserKeyboard.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/LaserCassEmu.sv
|
||||
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_location_assignment PIN_7 -to LED
|
||||
set_location_assignment PIN_54 -to CLOCK_27
|
||||
set_location_assignment PIN_144 -to VGA_R[5]
|
||||
set_location_assignment PIN_143 -to VGA_R[4]
|
||||
set_location_assignment PIN_142 -to VGA_R[3]
|
||||
set_location_assignment PIN_141 -to VGA_R[2]
|
||||
set_location_assignment PIN_137 -to VGA_R[1]
|
||||
set_location_assignment PIN_135 -to VGA_R[0]
|
||||
set_location_assignment PIN_133 -to VGA_B[5]
|
||||
set_location_assignment PIN_132 -to VGA_B[4]
|
||||
set_location_assignment PIN_125 -to VGA_B[3]
|
||||
set_location_assignment PIN_121 -to VGA_B[2]
|
||||
set_location_assignment PIN_120 -to VGA_B[1]
|
||||
set_location_assignment PIN_115 -to VGA_B[0]
|
||||
set_location_assignment PIN_114 -to VGA_G[5]
|
||||
set_location_assignment PIN_113 -to VGA_G[4]
|
||||
set_location_assignment PIN_112 -to VGA_G[3]
|
||||
set_location_assignment PIN_111 -to VGA_G[2]
|
||||
set_location_assignment PIN_110 -to VGA_G[1]
|
||||
set_location_assignment PIN_106 -to VGA_G[0]
|
||||
set_location_assignment PIN_136 -to VGA_VS
|
||||
set_location_assignment PIN_119 -to VGA_HS
|
||||
set_location_assignment PIN_65 -to AUDIO_L
|
||||
set_location_assignment PIN_80 -to AUDIO_R
|
||||
set_location_assignment PIN_105 -to SPI_DO
|
||||
set_location_assignment PIN_88 -to SPI_DI
|
||||
set_location_assignment PIN_126 -to SPI_SCK
|
||||
set_location_assignment PIN_127 -to SPI_SS2
|
||||
set_location_assignment PIN_91 -to SPI_SS3
|
||||
set_location_assignment PIN_13 -to CONF_DATA0
|
||||
set_location_assignment PIN_49 -to SDRAM_A[0]
|
||||
set_location_assignment PIN_44 -to SDRAM_A[1]
|
||||
set_location_assignment PIN_42 -to SDRAM_A[2]
|
||||
set_location_assignment PIN_39 -to SDRAM_A[3]
|
||||
set_location_assignment PIN_4 -to SDRAM_A[4]
|
||||
set_location_assignment PIN_6 -to SDRAM_A[5]
|
||||
set_location_assignment PIN_8 -to SDRAM_A[6]
|
||||
set_location_assignment PIN_10 -to SDRAM_A[7]
|
||||
set_location_assignment PIN_11 -to SDRAM_A[8]
|
||||
set_location_assignment PIN_28 -to SDRAM_A[9]
|
||||
set_location_assignment PIN_50 -to SDRAM_A[10]
|
||||
set_location_assignment PIN_30 -to SDRAM_A[11]
|
||||
set_location_assignment PIN_32 -to SDRAM_A[12]
|
||||
set_location_assignment PIN_83 -to SDRAM_DQ[0]
|
||||
set_location_assignment PIN_79 -to SDRAM_DQ[1]
|
||||
set_location_assignment PIN_77 -to SDRAM_DQ[2]
|
||||
set_location_assignment PIN_76 -to SDRAM_DQ[3]
|
||||
set_location_assignment PIN_72 -to SDRAM_DQ[4]
|
||||
set_location_assignment PIN_71 -to SDRAM_DQ[5]
|
||||
set_location_assignment PIN_69 -to SDRAM_DQ[6]
|
||||
set_location_assignment PIN_68 -to SDRAM_DQ[7]
|
||||
set_location_assignment PIN_86 -to SDRAM_DQ[8]
|
||||
set_location_assignment PIN_87 -to SDRAM_DQ[9]
|
||||
set_location_assignment PIN_98 -to SDRAM_DQ[10]
|
||||
set_location_assignment PIN_99 -to SDRAM_DQ[11]
|
||||
set_location_assignment PIN_100 -to SDRAM_DQ[12]
|
||||
set_location_assignment PIN_101 -to SDRAM_DQ[13]
|
||||
set_location_assignment PIN_103 -to SDRAM_DQ[14]
|
||||
set_location_assignment PIN_104 -to SDRAM_DQ[15]
|
||||
set_location_assignment PIN_58 -to SDRAM_BA[0]
|
||||
set_location_assignment PIN_51 -to SDRAM_BA[1]
|
||||
set_location_assignment PIN_85 -to SDRAM_DQMH
|
||||
set_location_assignment PIN_67 -to SDRAM_DQML
|
||||
set_location_assignment PIN_60 -to SDRAM_nRAS
|
||||
set_location_assignment PIN_64 -to SDRAM_nCAS
|
||||
set_location_assignment PIN_66 -to SDRAM_nWE
|
||||
set_location_assignment PIN_59 -to SDRAM_nCS
|
||||
set_location_assignment PIN_33 -to SDRAM_CKE
|
||||
set_location_assignment PIN_43 -to SDRAM_CLK
|
||||
set_location_assignment PLL_1 -to "pll27:pll|altpll:altpll_component"
|
||||
|
||||
# Classic Timing Assignments
|
||||
# ==========================
|
||||
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
||||
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
||||
|
||||
# Analysis & Synthesis Assignments
|
||||
# ================================
|
||||
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
||||
set_global_assignment -name FAMILY "Cyclone III"
|
||||
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
|
||||
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
|
||||
set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
|
||||
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
||||
set_global_assignment -name SAVE_DISK_SPACE OFF
|
||||
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
|
||||
set_global_assignment -name TOP_LEVEL_ENTITY Laser310_MiST
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
|
||||
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
||||
set_global_assignment -name DEVICE EP3C25E144C8
|
||||
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
|
||||
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
|
||||
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
|
||||
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
|
||||
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
|
||||
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
|
||||
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
||||
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
||||
|
||||
# Assembler Assignments
|
||||
# =====================
|
||||
set_global_assignment -name GENERATE_RBF_FILE ON
|
||||
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
|
||||
|
||||
# SignalTap II Assignments
|
||||
# ========================
|
||||
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
||||
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
|
||||
|
||||
# Power Estimation Assignments
|
||||
# ============================
|
||||
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
||||
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
||||
|
||||
# Advanced I/O Timing Assignments
|
||||
# ===============================
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
|
||||
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
|
||||
|
||||
# ---------------------------
|
||||
# start ENTITY(Laser310_MiST)
|
||||
|
||||
# Pin & Location Assignments
|
||||
# ==========================
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
|
||||
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
|
||||
|
||||
# Fitter Assignments
|
||||
# ==================
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_A[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_BA[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQML
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_DQMH
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nRAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCAS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nWE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_nCS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CKE
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_R[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_G[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[5]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[4]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[3]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[2]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[1]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_B[0]
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_HS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to VGA_VS
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to LED
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_L
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DO
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_L
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUDIO_R
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_27
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CONF_DATA0
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DI
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_DO
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SCK
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS2
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SPI_SS3
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQMH
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQML
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nRAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCAS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nWE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_nCS
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CKE
|
||||
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to CLOCK_27
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_DI
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SCK
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS2
|
||||
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to SPI_SS3
|
||||
|
||||
# start DESIGN_PARTITION(Top)
|
||||
# ---------------------------
|
||||
|
||||
# Incremental Compilation Assignments
|
||||
# ===================================
|
||||
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
||||
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
|
||||
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
||||
|
||||
# end DESIGN_PARTITION(Top)
|
||||
# -------------------------
|
||||
|
||||
# end ENTITY(Laser310_MiST)
|
||||
# -------------------------
|
||||
set_global_assignment -name VERILOG_FILE rtl/fdc.v
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
@@ -1,33 +0,0 @@
|
||||
#************************************************************
|
||||
# THIS IS A WIZARD-GENERATED FILE.
|
||||
#
|
||||
# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
|
||||
#
|
||||
#************************************************************
|
||||
|
||||
# Copyright (C) 1991-2014 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
# Clock constraints
|
||||
|
||||
create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27}]
|
||||
create_clock -name {SPI_SCK} -period 10.000 -waveform { 0.000 0.500 } [get_ports {SPI_SCK}]
|
||||
|
||||
# Automatically constrain PLL and other generated clocks
|
||||
derive_pll_clocks -create_base_clocks
|
||||
|
||||
# Automatically calculate clock uncertainty to jitter and other effects.
|
||||
derive_clock_uncertainty
|
||||
@@ -1,11 +0,0 @@
|
||||
{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL warning at tv80_core.v(300): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" { } { } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10090 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10259 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10030 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
{ "" "" "" "*" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
|
||||
@@ -1,15 +0,0 @@
|
||||
@echo off
|
||||
del /s *.bak
|
||||
del /s *.orig
|
||||
del /s *.rej
|
||||
rmdir /s /q db
|
||||
rmdir /s /q incremental_db
|
||||
rmdir /s /q output_files
|
||||
rmdir /s /q simulation
|
||||
rmdir /s /q greybox_tmp
|
||||
del PLLJ_PLLSPE_INFO.txt
|
||||
del *.qws
|
||||
del *.ppf
|
||||
del *.qip
|
||||
del *.ddb
|
||||
pause
|
||||
Binary file not shown.
@@ -1,68 +0,0 @@
|
||||
module CHAR_GEN(
|
||||
// control
|
||||
reset,
|
||||
|
||||
char_code,
|
||||
subchar_line,
|
||||
subchar_pixel,
|
||||
|
||||
pixel_clock,
|
||||
pixel_on
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
|
||||
input [7:0] char_code;
|
||||
input [4:0] subchar_line; // line number within 12 line block
|
||||
input [3:0] subchar_pixel; // pixel position within 8 pixel block
|
||||
|
||||
output pixel_on;
|
||||
|
||||
reg [7:0] latched_data;
|
||||
reg pixel_on;
|
||||
|
||||
wire [11:0] rom_addr = {char_code[7:0], subchar_line[4:1]};
|
||||
wire [7:0] rom_data;
|
||||
|
||||
|
||||
// instantiate the character generator ROM
|
||||
//CHAR_GEN_ROM CHAR_GEN_ROM
|
||||
//(
|
||||
// pixel_clock,
|
||||
// rom_addr,
|
||||
// rom_data
|
||||
//);
|
||||
|
||||
sprom #(
|
||||
.init_file("./roms/charrom_4k.mif"),
|
||||
.widthad_a(12),
|
||||
.width_a(8))
|
||||
CHAR_GEN_ROM(
|
||||
.address(rom_addr),
|
||||
.clock(pixel_clock),
|
||||
.q(rom_data)
|
||||
);
|
||||
|
||||
|
||||
// serialize the CHARACTER MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_on = 1'b0;
|
||||
latched_data = 8'h00;
|
||||
end
|
||||
|
||||
else begin
|
||||
case(subchar_pixel)
|
||||
4'b0101:
|
||||
latched_data [7:0] = {rom_data[0],rom_data[1],rom_data[2],rom_data[3],rom_data[4],rom_data[5],rom_data[6],rom_data[7]};
|
||||
default:
|
||||
if(subchar_pixel[0]==1'b0)
|
||||
{pixel_on,latched_data [7:1]} <= latched_data [7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule //CHAR_GEN
|
||||
@@ -1,19 +0,0 @@
|
||||
module CHAR_GEN_ROM
|
||||
(
|
||||
pixel_clock,
|
||||
address,
|
||||
data
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input [11:0] address;
|
||||
output wire [7:0] data;
|
||||
|
||||
// Character generator
|
||||
char_rom_4k_altera char_rom(
|
||||
.address(address),
|
||||
.clock(pixel_clock),
|
||||
.q(data)
|
||||
);
|
||||
|
||||
endmodule //CHAR_GEN_ROM
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,133 +0,0 @@
|
||||
|
||||
module Laser310_MiST
|
||||
(
|
||||
output LED,
|
||||
output [5:0] VGA_R,
|
||||
output [5:0] VGA_G,
|
||||
output [5:0] VGA_B,
|
||||
output VGA_HS,
|
||||
output VGA_VS,
|
||||
output AUDIO_L,
|
||||
output AUDIO_R,
|
||||
input SPI_SCK,
|
||||
output SPI_DO,
|
||||
input SPI_DI,
|
||||
input SPI_SS2,
|
||||
input SPI_SS3,
|
||||
input CONF_DATA0,
|
||||
input CLOCK_27
|
||||
);
|
||||
|
||||
`include "rtl\build_id.v"
|
||||
|
||||
localparam CONF_STR = {
|
||||
"Laser310;;",
|
||||
"O1,Turbo,Off,On;",
|
||||
"O2,Dos Rom,Off,On;",
|
||||
"O34,Scanlines,Off,25%,50%,75%;",
|
||||
"O5,SHRG,Off,On;",
|
||||
"T6,Reset;",
|
||||
"V,v1.00.",`BUILD_DATE
|
||||
};
|
||||
|
||||
assign LED = 1;
|
||||
assign AUDIO_R = AUDIO_L;
|
||||
|
||||
wire clk_50, clk_25, clk_10, clk_6p25;
|
||||
wire pll_locked;
|
||||
pll pll(
|
||||
.inclk0(CLOCK_27),
|
||||
.areset(0),
|
||||
.c0(clk_50),
|
||||
.c1(clk_25),
|
||||
.c2(clk_10),
|
||||
.c3(clk_6p25)
|
||||
);
|
||||
|
||||
wire [31:0] status;
|
||||
wire [1:0] buttons;
|
||||
wire [1:0] switches;
|
||||
wire [7:0] joystick_0;
|
||||
wire [7:0] joystick_1;
|
||||
wire scandoublerD;
|
||||
wire ypbpr;
|
||||
wire key_pressed;
|
||||
wire [7:0] key_code;
|
||||
wire key_strobe;
|
||||
reg [1:0] audio;
|
||||
wire [7:0] audio_s;
|
||||
wire ce_pix;
|
||||
wire hs, vs;
|
||||
wire [7:0] r,g,b;
|
||||
|
||||
LASER310_TOP LASER310_TOP(
|
||||
.CLK50MHZ(clk_50),
|
||||
.CLK25MHZ(clk_25),
|
||||
.CLK10MHZ(clk_10),
|
||||
.RESET(~(status[0] | status[6] | buttons[1])),
|
||||
.VGA_RED(r),
|
||||
.VGA_GREEN(g),
|
||||
.VGA_BLUE(b),
|
||||
.VGA_HS(hs),
|
||||
.VGA_VS(vs),
|
||||
.AUD_ADCDAT(audio),
|
||||
// .VIDEO_MODE(1'b0),
|
||||
.audio_s(audio_s),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.SWITCH({"00000",~status[5],~status[2],~status[1]}),
|
||||
.UART_RXD(),
|
||||
.UART_TXD()
|
||||
);
|
||||
|
||||
mist_video #(.COLOR_DEPTH(6)) mist_video(
|
||||
.clk_sys(clk_25),
|
||||
.SPI_SCK(SPI_SCK),
|
||||
.SPI_SS3(SPI_SS3),
|
||||
.SPI_DI(SPI_DI),
|
||||
.R(r[5:0]),
|
||||
.G(g[5:0]),
|
||||
.B(b[5:0]),
|
||||
.HSync(hs),
|
||||
.VSync(vs),
|
||||
.VGA_R(VGA_R),
|
||||
.VGA_G(VGA_G),
|
||||
.VGA_B(VGA_B),
|
||||
.VGA_VS(VGA_VS),
|
||||
.VGA_HS(VGA_HS),
|
||||
.scandoubler_disable(1'b1),//scandoublerD),
|
||||
.scanlines(status[4:3]),
|
||||
.ypbpr(ypbpr)
|
||||
);
|
||||
|
||||
user_io #(
|
||||
.STRLEN(($size(CONF_STR)>>3)))
|
||||
user_io(
|
||||
.clk_sys (clk_25 ),
|
||||
.conf_str (CONF_STR ),
|
||||
.SPI_CLK (SPI_SCK ),
|
||||
.SPI_SS_IO (CONF_DATA0 ),
|
||||
.SPI_MISO (SPI_DO ),
|
||||
.SPI_MOSI (SPI_DI ),
|
||||
.buttons (buttons ),
|
||||
.switches (switches ),
|
||||
.scandoubler_disable (scandoublerD ),
|
||||
.ypbpr (ypbpr ),
|
||||
.key_strobe (key_strobe ),
|
||||
.key_pressed (key_pressed ),
|
||||
.key_code (key_code ),
|
||||
.status (status )
|
||||
);
|
||||
|
||||
dac #(
|
||||
.C_bits(15))
|
||||
dac(
|
||||
.clk_i(clk_25),
|
||||
.res_n_i(1),
|
||||
// .dac_i({~audio_s[7],audio_s[6:0],{4{audio}}}),
|
||||
.dac_i({8{audio}}),
|
||||
.dac_o(AUDIO_L)
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -1,122 +0,0 @@
|
||||
module LaserCassEmu(
|
||||
input wire [15:0] CPU_A,
|
||||
input wire CPU_RD,
|
||||
input wire CPU_WR
|
||||
);
|
||||
// cassette
|
||||
|
||||
(*keep*)wire [1:0] CASS_OUT;
|
||||
(*keep*)wire CASS_IN;
|
||||
(*keep*)wire CASS_IN_L;
|
||||
(*keep*)wire CASS_IN_R;
|
||||
|
||||
reg [7:0] LATCHED_IO_DATA_WR;
|
||||
// 用于外部磁带仿真计数
|
||||
//(*keep*)reg EMU_CASS_CLK;
|
||||
|
||||
(*keep*)wire EMU_CASS_EN;
|
||||
(*keep*)wire [1:0] EMU_CASS_DAT;
|
||||
|
||||
`ifdef CASS_EMU
|
||||
|
||||
wire CASS_BUF_RD;
|
||||
wire [15:0] CASS_BUF_A;
|
||||
wire CASS_BUF_WR;
|
||||
wire [7:0] CASS_BUF_DAT;
|
||||
wire [7:0] CASS_BUF_Q;
|
||||
|
||||
// F9 CASS PLAY
|
||||
// F10 CASS STOP
|
||||
|
||||
EMU_CASS_KEY EMU_CASS_KEY(
|
||||
KEY_Fxx[8],
|
||||
KEY_Fxx[9],
|
||||
// cass emu
|
||||
CASS_BUF_RD,
|
||||
//
|
||||
CASS_BUF_A,
|
||||
CASS_BUF_WR,
|
||||
CASS_BUF_DAT,
|
||||
CASS_BUF_Q,
|
||||
// Control Signals
|
||||
EMU_CASS_EN,
|
||||
EMU_CASS_DAT,
|
||||
|
||||
// key emu
|
||||
EMU_KEY,
|
||||
EMU_KEY_EX,
|
||||
EMU_KEY_EN,
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
UART_RXD,
|
||||
UART_TXD,
|
||||
|
||||
// System
|
||||
TURBO_SPEED,
|
||||
// Clock: 10MHz
|
||||
CLK10MHZ,
|
||||
RESET_N
|
||||
);
|
||||
|
||||
|
||||
`ifdef CASS_EMU_16K
|
||||
|
||||
cass_ram_16k_altera cass_buf(
|
||||
.address(CASS_BUF_A[13:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_8K
|
||||
|
||||
cass_ram_8k_altera cass_buf(
|
||||
.address(CASS_BUF_A[12:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_4K
|
||||
|
||||
cass_ram_4k_altera cass_buf(
|
||||
.address(CASS_BUF_A[11:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_2K
|
||||
|
||||
cass_ram_2k_altera cass_buf(
|
||||
.address(CASS_BUF_A[10:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
|
||||
|
||||
(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
|
||||
|
||||
endmodule
|
||||
@@ -1,414 +0,0 @@
|
||||
module LaserKeyboard(
|
||||
input wire CLK50MHZ,
|
||||
input wire [15:0] CPU_A,
|
||||
input wire RESET,
|
||||
input wire CASS_IN,
|
||||
input wire PS2_KBCLK,
|
||||
input wire PS2_KBDAT
|
||||
);
|
||||
|
||||
|
||||
// keyboard
|
||||
reg [4:0] KB_CLK;
|
||||
reg [16:0] RESET_KEY_COUNT;
|
||||
wire [7:0] SCAN;
|
||||
wire PRESS;
|
||||
wire PRESS_N;
|
||||
wire EXTENDED;
|
||||
reg BOOTROM_EN;
|
||||
reg [7:0] BOOTROM_BANK;
|
||||
reg AUTOSTARTROM_EN;
|
||||
reg [7:0] AUTOSTARTROM_BANK;
|
||||
reg [63:0] KEY;
|
||||
reg [9:0] KEY_EX;
|
||||
reg [11:0] KEY_Fxx;
|
||||
wire [7:0] KEY_DATA;
|
||||
//reg [63:0] LAST_KEY;
|
||||
//reg CAPS_CLK;
|
||||
//reg CAPS;
|
||||
wire A_KEY_PRESSED;
|
||||
|
||||
reg [7:0] LATCHED_KEY_DATA;
|
||||
|
||||
// emu keyboard
|
||||
wire [63:0] EMU_KEY;
|
||||
wire [9:0] EMU_KEY_EX;
|
||||
wire EMU_KEY_EN;
|
||||
// keyboard
|
||||
|
||||
/*****************************************************************************
|
||||
* Convert PS/2 keyboard to ASCII keyboard
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
|
||||
A0 R Q E W T 68FEH 0
|
||||
A1 F A D CTRL S G 68FDH 8
|
||||
A2 V Z C SHFT X B 68FBH 16
|
||||
A3 4 1 3 2 5 68F7H 24
|
||||
A4 M 空格 ， . N 68EFH 32
|
||||
A5 7 0 8 - 9 6 68DFH 40
|
||||
A6 U P I RETN O Y 68BFH 48
|
||||
A7 J ； K : L H 687FH 56
|
||||
*/
|
||||
|
||||
// 7: 0
|
||||
// 15: 8
|
||||
// 23:16
|
||||
// 31:24
|
||||
// 39:32
|
||||
// 47:40
|
||||
// 55:48
|
||||
// 63:56
|
||||
|
||||
|
||||
|
||||
// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
|
||||
// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
|
||||
// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
|
||||
// 读 6800H 判断是否有按键按下。
|
||||
|
||||
// The method of keyboard detection is to cyclically ask each line to send a low level signal,
|
||||
// that is, to read the data with the address line "0".
|
||||
// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4,
|
||||
// become 01101***11111110B (A8~A10 does not work,
|
||||
// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
|
||||
// Read 6800H to determine if there is a button press.
|
||||
|
||||
// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
|
||||
// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
|
||||
|
||||
// 键盘扩展
|
||||
// 加入方向键盘
|
||||
// Keyboard extension
|
||||
|
||||
// left: ctrl M 37 KEY_EX[5]
|
||||
// right: ctrl , 35 KEY_EX[6]
|
||||
// up: ctrl . 33 KEY_EX[4]
|
||||
// down: ctrl space 36 KEY_EX[7]
|
||||
// esc: ctrl - 42 KEY_EX[3]
|
||||
// backspace: ctrl M 37 KEY_EX[8]
|
||||
|
||||
// R-Shift
|
||||
|
||||
|
||||
wire [63:0] KEY_C = EMU_KEY_EN?EMU_KEY:KEY;
|
||||
wire [9:0] KEY_EX_C = EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
|
||||
|
||||
//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
|
||||
wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
|
||||
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45], KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21], KEY_C[13], KEY_C[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44], KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20], KEY_C[12], KEY_C[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43], KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19], KEY_C[11], KEY_C[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34], KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41], KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17], KEY_C[ 9], KEY_C[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40], KEY_C[32], KEY_C[24], KEY_C[16], KEY_C[ 8], KEY_C[ 0]})==8'hff;
|
||||
|
||||
/*
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
|
||||
*/
|
||||
|
||||
wire KEY_DATA_BIT7 = 1'b1; // 没有空置，具体用途没有理解
|
||||
//wire KEY_DATA_BIT6 = CASS_IN;
|
||||
wire KEY_DATA_BIT6 = ~CASS_IN;
|
||||
|
||||
assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
|
||||
|
||||
/*
|
||||
assign KEY_DATA = (CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
8'hff;
|
||||
|
||||
assign KEY_DATA =
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
8'hff;
|
||||
*/
|
||||
|
||||
|
||||
assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
|
||||
|
||||
always @(posedge KB_CLK[3] or negedge RESET)
|
||||
begin
|
||||
if(~RESET)
|
||||
begin
|
||||
KEY <= 64'hFFFFFFFFFFFFFFFF;
|
||||
KEY_EX <= 10'h3FF;
|
||||
KEY_Fxx <= 12'h000;
|
||||
// CAPS_CLK <= 1'b0;
|
||||
RESET_KEY_COUNT <= 17'h1FFFF;
|
||||
|
||||
BOOTROM_BANK <= 0;
|
||||
BOOTROM_EN <= 1'b0;
|
||||
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//KEY[?] <= CAPS;
|
||||
if(RESET_KEY_COUNT[16]==1'b0)
|
||||
RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
|
||||
|
||||
case(SCAN)
|
||||
/*8'h07:
|
||||
begin
|
||||
KEY_Fxx[11] <= PRESS; // F12 RESET
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b0;
|
||||
BOOTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h78: KEY_Fxx[10] <= PRESS; // F11
|
||||
8'h09: KEY_Fxx[ 9] <= PRESS; // F10 CASS STOP
|
||||
8'h01: KEY_Fxx[ 8] <= PRESS; // F9 CASS PLAY
|
||||
8'h0A:
|
||||
begin
|
||||
KEY_Fxx[ 7] <= PRESS; // F8 Ctrl or L-Shift BOOT 8
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 39;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 23;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h83:
|
||||
begin
|
||||
KEY_Fxx[ 6] <= PRESS; // F7 Ctrl or L-Shift BOOT 7
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 38;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 22;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0B:
|
||||
begin
|
||||
KEY_Fxx[ 5] <= PRESS; // F6 Ctrl or L-Shift BOOT 6
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 37;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 21;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
KEY_Fxx[ 4] <= PRESS; // F5 Ctrl or L-Shift BOOT 5
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 36;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 20;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0C:
|
||||
begin
|
||||
KEY_Fxx[ 3] <= PRESS; // F4 Ctrl or L-Shift BOOT 4
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 35;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 19;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h04:
|
||||
begin
|
||||
KEY_Fxx[ 2] <= PRESS; // F3 Ctrl or L-Shift BOOT 3
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 34;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 18;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
KEY_Fxx[ 1] <= PRESS; // F2 Ctrl or L-Shift BOOT 2
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 33;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 17;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h05:
|
||||
begin
|
||||
KEY_Fxx[ 0] <= PRESS; // F1 Ctrl or L-Shift BOOT 1
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 32;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 16;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end*/
|
||||
|
||||
8'h16: KEY[28] <= PRESS_N; // 1 !
|
||||
8'h1E: KEY[25] <= PRESS_N; // 2 @
|
||||
8'h26: KEY[27] <= PRESS_N; // 3 #
|
||||
8'h25: KEY[29] <= PRESS_N; // 4 $
|
||||
8'h2E: KEY[24] <= PRESS_N; // 5 %
|
||||
8'h36: KEY[40] <= PRESS_N; // 6 ^
|
||||
8'h3D: KEY[45] <= PRESS_N; // 7 &
|
||||
// 8'h0D: KEY[?] <= PRESS_N; // TAB
|
||||
8'h3E: KEY[43] <= PRESS_N; // 8 *
|
||||
8'h46: KEY[41] <= PRESS_N; // 9 (
|
||||
8'h45: KEY[44] <= PRESS_N; // 0 )
|
||||
8'h4E: KEY[42] <= PRESS_N; // - _
|
||||
// 8'h55: KEY[?] <= PRESS_N; // = +
|
||||
8'h66: KEY_EX[8] <= PRESS_N; // backspace
|
||||
// 8'h0E: KEY[?] <= PRESS_N; // ` ~
|
||||
// 8'h5D: KEY[?] <= PRESS_N; // \ |
|
||||
8'h49: KEY[33] <= PRESS_N; // . >
|
||||
8'h4b: KEY[57] <= PRESS_N; // L
|
||||
8'h44: KEY[49] <= PRESS_N; // O
|
||||
// 8'h11 KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
|
||||
8'h5A: KEY[50] <= PRESS_N; // CR
|
||||
// 8'h54: KEY[?] <= PRESS_N; // [ {
|
||||
// 8'h5B: KEY[?] <= PRESS_N; // ] }
|
||||
8'h52: KEY[58] <= PRESS_N; // ' "
|
||||
8'h1D: KEY[ 1] <= PRESS_N; // W
|
||||
8'h24: KEY[ 3] <= PRESS_N; // E
|
||||
8'h2D: KEY[ 5] <= PRESS_N; // R
|
||||
8'h2C: KEY[ 0] <= PRESS_N; // T
|
||||
8'h35: KEY[48] <= PRESS_N; // Y
|
||||
8'h3C: KEY[53] <= PRESS_N; // U
|
||||
8'h43: KEY[51] <= PRESS_N; // I
|
||||
8'h1B: KEY[ 9] <= PRESS_N; // S
|
||||
8'h23: KEY[11] <= PRESS_N; // D
|
||||
8'h2B: KEY[13] <= PRESS_N; // F
|
||||
8'h34: KEY[ 8] <= PRESS_N; // G
|
||||
8'h33: KEY[56] <= PRESS_N; // H
|
||||
8'h3B: KEY[61] <= PRESS_N; // J
|
||||
8'h42: KEY[59] <= PRESS_N; // K
|
||||
8'h22: KEY[17] <= PRESS_N; // X
|
||||
8'h21: KEY[19] <= PRESS_N; // C
|
||||
8'h2a: KEY[21] <= PRESS_N; // V
|
||||
8'h32: KEY[16] <= PRESS_N; // B
|
||||
8'h31: KEY[32] <= PRESS_N; // N
|
||||
8'h3a: KEY[37] <= PRESS_N; // M
|
||||
8'h41: KEY[35] <= PRESS_N; // , <
|
||||
8'h15: KEY[ 4] <= PRESS_N; // Q
|
||||
8'h1C: KEY[12] <= PRESS_N; // A
|
||||
8'h1A: KEY[20] <= PRESS_N; // Z
|
||||
8'h29: KEY[36] <= PRESS_N; // Space
|
||||
// 8'h4A: KEY[?] <= PRESS_N; // / ?
|
||||
8'h4C: KEY[60] <= PRESS_N; // ; :
|
||||
8'h4D: KEY[52] <= PRESS_N; // P
|
||||
8'h14: KEY[10] <= PRESS_N; // Ctrl either left or right
|
||||
8'h12: KEY[18] <= PRESS_N; // L-Shift
|
||||
8'h59: KEY_EX[0] <= PRESS_N; // R-Shift
|
||||
8'h11:
|
||||
begin
|
||||
if(~EXTENDED)
|
||||
KEY_EX[1] <= PRESS_N; // Repeat really left ALT
|
||||
else
|
||||
KEY_EX[2] <= PRESS_N; // LF really right ALT
|
||||
end
|
||||
8'h76: KEY_EX[3] <= PRESS_N; // Esc
|
||||
8'h75: KEY_EX[4] <= PRESS_N; // up
|
||||
8'h6B: KEY_EX[5] <= PRESS_N; // left
|
||||
8'h74: KEY_EX[6] <= PRESS_N; // right
|
||||
8'h72: KEY_EX[7] <= PRESS_N; // down
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
always @ (posedge CLK50MHZ) // 50MHz
|
||||
KB_CLK <= KB_CLK + 1'b1; // 50/32 = 1.5625 MHz
|
||||
|
||||
ps2_keyboard KEYBOARD(
|
||||
.RESET_N(~RESET),
|
||||
.CLK(KB_CLK[4]),
|
||||
.PS2_CLK(PS2_KBCLK),
|
||||
.PS2_DATA(PS2_KBDAT),
|
||||
.RX_SCAN(SCAN),
|
||||
.RX_PRESSED(PRESS),
|
||||
.RX_EXTENDED(EXTENDED)
|
||||
);
|
||||
|
||||
assign PRESS_N = ~PRESS;
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -1,372 +0,0 @@
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file is part of the NextZ80 project
|
||||
// http://www.opencores.org/cores/nextz80/
|
||||
//
|
||||
// Filename: NextZ80ALU.v
|
||||
// Description: Implementation of Z80 compatible CPU - ALU
|
||||
// Version 1.0
|
||||
// Creation date: 28Jan2011 - 18Mar2011
|
||||
//
|
||||
// Author: Nicolae Dumitrache
|
||||
// e-mail: ndumitrache@opencores.org
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2011 Nicolae Dumitrache
|
||||
//
|
||||
// This source file may be used and distributed without
|
||||
// restriction provided that this copyright statement is not
|
||||
// removed from the file and that any derivative work contains
|
||||
// the original copyright notice and the associated disclaimer.
|
||||
//
|
||||
// This source file is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU Lesser General
|
||||
// Public License as published by the Free Software Foundation;
|
||||
// either version 2.1 of the License, or (at your option) any
|
||||
// later version.
|
||||
//
|
||||
// This source is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. See the GNU Lesser General Public License for more
|
||||
// details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General
|
||||
// Public License along with this source; if not, download it
|
||||
// from http://www.opencores.org/lgpl.shtml
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
//FLAGS: S Z X1 N X2 PV N C
|
||||
// OP[4:0]
|
||||
// 00000 - ADD D0,D1
|
||||
// 00001 - ADC D0,D1
|
||||
// 00010 - SUB D0,D1
|
||||
// 00011 - SBC D0,D1
|
||||
// 00100 - AND D0,D1
|
||||
// 00101 - XOR D0,D1
|
||||
// 00110 - OR D0,D1
|
||||
// 00111 - CP D0,D1
|
||||
// 01000 - INC D0
|
||||
// 01001 - CPL D0
|
||||
// 01010 - DEC D0
|
||||
// 01011 - RRD
|
||||
// 01100 - RLD
|
||||
// 01101 - DAA
|
||||
// 01110 - INC16
|
||||
// 01111 - DEC16
|
||||
// 10000 - ADD16LO
|
||||
// 10001 - ADD16HI
|
||||
// 10010 -
|
||||
// 10011 -
|
||||
// 10100 - CCF, pass D0
|
||||
// 10101 - SCF, pass D0
|
||||
// 10110 -
|
||||
// 10111 -
|
||||
// 11000 - RLCA D0
|
||||
// 11001 - RRCA D0
|
||||
// 11010 - RLA D0
|
||||
// 11011 - RRA D0
|
||||
// 11100 - {ROT, BIT, SET, RES} D0,EXOP
|
||||
// RLC D0 C <-- D0 <-- D0[7]
|
||||
// RRC D0 D0[0] --> D0 --> C
|
||||
// RL D0 C <-- D0 <-- C
|
||||
// RR D0 C --> D0 --> C
|
||||
// SLA D0 C <-- D0 <-- 0
|
||||
// SRA D0 D0[7] --> D0 --> C
|
||||
// SLL D0 C <-- D0 <-- 1
|
||||
// SRL D0 0 --> D0 --> C
|
||||
// 11101 - IN, pass D1
|
||||
// 11110 - FLAGS <- D0
|
||||
// 11111 - NEG D1
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module ALU8(
|
||||
input [7:0] D0,
|
||||
input [7:0] D1,
|
||||
input [7:0] FIN,
|
||||
output reg[7:0] FOUT,
|
||||
output reg [15:0] ALU8DOUT,
|
||||
input [4:0] OP,
|
||||
input [5:0] EXOP, // EXOP[5:4] = 2'b11 for CPI/D/R
|
||||
input LDIFLAGS, // zero HF and NF on inc/dec16
|
||||
input DSTHI // destination lo
|
||||
);
|
||||
|
||||
wire [7:0] daaadjust;
|
||||
wire cdaa, hdaa;
|
||||
daa daa_adjust(.flags(FIN), .val(D0), .adjust(daaadjust), .cdaa(cdaa), .hdaa(hdaa));
|
||||
|
||||
wire parity = ~^ALU8DOUT[15:8];
|
||||
wire zero = ALU8DOUT[15:8] == 0;
|
||||
reg csin, cin;
|
||||
wire [7:0]d0mux = OP[4:1] == 4'b1111 ? 0 : D0;
|
||||
reg [7:0]_d1mux;
|
||||
wire [7:0]d1mux = OP[1] ? ~_d1mux : _d1mux;
|
||||
wire [8:0]sum;
|
||||
wire hf;
|
||||
assign {hf, sum[3:0]} = d0mux[3:0] + d1mux[3:0] + cin;
|
||||
assign sum[8:4] = d0mux[7:4] + d1mux[7:4] + hf;
|
||||
wire overflow = (d0mux[7] & d1mux[7] & !sum[7]) | (!d0mux[7] & !d1mux[7] & sum[7]);
|
||||
reg [7:0]dbit;
|
||||
|
||||
always @* begin
|
||||
ALU8DOUT = 16'hxxxx;
|
||||
FOUT = 8'hxx;
|
||||
case({OP[4:2]})
|
||||
0,1,4,7: _d1mux = D1;
|
||||
2: _d1mux = 1;
|
||||
3: _d1mux = daaadjust; // DAA
|
||||
6,5: _d1mux = 8'hxx;
|
||||
endcase
|
||||
case({OP[2:0], FIN[0]})
|
||||
0,1,2,7,8,9,10,11,12,13: cin = 0;
|
||||
3,4,5,6,14,15: cin = 1;
|
||||
endcase
|
||||
case(EXOP[3:0])
|
||||
0: dbit = 8'b11111110;
|
||||
1: dbit = 8'b11111101;
|
||||
2: dbit = 8'b11111011;
|
||||
3: dbit = 8'b11110111;
|
||||
4: dbit = 8'b11101111;
|
||||
5: dbit = 8'b11011111;
|
||||
6: dbit = 8'b10111111;
|
||||
7: dbit = 8'b01111111;
|
||||
8: dbit = 8'b00000001;
|
||||
9: dbit = 8'b00000010;
|
||||
10: dbit = 8'b00000100;
|
||||
11: dbit = 8'b00001000;
|
||||
12: dbit = 8'b00010000;
|
||||
13: dbit = 8'b00100000;
|
||||
14: dbit = 8'b01000000;
|
||||
15: dbit = 8'b10000000;
|
||||
endcase
|
||||
case(OP[3] ? EXOP[2:0] : OP[2:0])
|
||||
0,5: csin = D0[7];
|
||||
1: csin = D0[0];
|
||||
2,3: csin = FIN[0];
|
||||
4,7: csin = 0;
|
||||
6: csin = 1;
|
||||
endcase
|
||||
case(OP[4:0])
|
||||
0,1,2,3,8,10: begin // ADD, ADC, SUB, SBC, INC, DEC
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
ALU8DOUT[7:0] = sum[7:0];
|
||||
FOUT[0] = OP[3] ? FIN[0] : (sum[8] ^ OP[1]); // inc/dec
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hf ^ OP[1];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero & (FIN[6] | ~EXOP[5] | ~DSTHI | OP[3]); //(EXOP[5] & DSTHI) ? (zero & FIN[6]) : zero; // adc16/sbc16
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
16,17: begin // ADD16LO, ADD16HI
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
ALU8DOUT[7:0] = sum[7:0];
|
||||
FOUT[0] = sum[8];
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hf ^ OP[1];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
7: begin // CP
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = EXOP[5] ? FIN[0] : !sum[8]; // CPI/D/R
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = D1[3];
|
||||
FOUT[4] = !hf;
|
||||
FOUT[5] = D1[5];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
31: begin // NEG
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = !sum[8];
|
||||
FOUT[1] = OP[1];
|
||||
FOUT[2] = overflow;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = !hf;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
4: begin // AND
|
||||
ALU8DOUT[15:8] = D0 & D1;
|
||||
FOUT[0] = 0;
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 1;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
5,6: begin //XOR, OR
|
||||
ALU8DOUT[15:8] = OP[0] ? (D0 ^ D1) : (D0 | D1);
|
||||
FOUT[0] = 0;
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
9: begin // CPL
|
||||
ALU8DOUT[15:8] = ~D0;
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 1;
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 1;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[7:6] = FIN[7:6];
|
||||
end
|
||||
11,12: begin // RLD, RRD
|
||||
if(OP[0]) ALU8DOUT = {D0[7:4], D1[3:0], D0[3:0], D1[7:4]};
|
||||
else ALU8DOUT = {D0[7:4], D1[7:0], D0[3:0]};
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
13: begin // DAA
|
||||
ALU8DOUT[15:8] = sum[7:0];
|
||||
FOUT[0] = cdaa;
|
||||
FOUT[1] = FIN[1];
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = hdaa;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
14,15: begin // inc/dec 16
|
||||
ALU8DOUT = {D0, D1} + (OP[0] ? 16'hffff : 16'h0001);
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = LDIFLAGS ? 1'b0 : FIN[1];
|
||||
FOUT[2] = ALU8DOUT != 0;
|
||||
FOUT[3] = FIN[3];
|
||||
FOUT[4] = LDIFLAGS ? 1'b0 : FIN[4];
|
||||
FOUT[5] = FIN[5];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
20,21: begin // CCF, SCF
|
||||
ALU8DOUT[15:8] = D0;
|
||||
FOUT[0] = OP[0] ? 1'b1 : !FIN[0];
|
||||
FOUT[1] = 1'b0;
|
||||
FOUT[2] = FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = OP[0] ? 1'b0 : FIN[0];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = FIN[6];
|
||||
FOUT[7] = FIN[7];
|
||||
end
|
||||
24,25,26,27, 28: begin // ROT, BIT, RES, SET
|
||||
case({OP[2], EXOP[4:3]})
|
||||
0,1,2,3,4: // rot - shift
|
||||
if(OP[2] ? EXOP[0] : OP[0]){ALU8DOUT[15:8], FOUT[0]} = {csin, D0}; // right
|
||||
else {FOUT[0], ALU8DOUT[15:8]} = {D0, csin}; // left
|
||||
5,6: begin // BIT, RES
|
||||
FOUT[0] = FIN[0];
|
||||
ALU8DOUT[15:8] = D0 & dbit;
|
||||
end
|
||||
7: begin // SET
|
||||
FOUT[0] = FIN[0];
|
||||
ALU8DOUT[15:8] = D0 | dbit;
|
||||
end
|
||||
endcase
|
||||
ALU8DOUT[7:0] = ALU8DOUT[15:8];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = OP[2] ? (EXOP[3] ? zero : parity) : FIN[2];
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = OP[2] & EXOP[3];
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = OP[2] ? zero : FIN[6];
|
||||
FOUT[7] = OP[2] ? ALU8DOUT[15] : FIN[7];
|
||||
end
|
||||
29: begin // IN, pass D1
|
||||
ALU8DOUT = {D1, D1};
|
||||
FOUT[0] = FIN[0];
|
||||
FOUT[1] = 0;
|
||||
FOUT[2] = parity;
|
||||
FOUT[3] = ALU8DOUT[11];
|
||||
FOUT[4] = 0;
|
||||
FOUT[5] = ALU8DOUT[13];
|
||||
FOUT[6] = zero;
|
||||
FOUT[7] = ALU8DOUT[15];
|
||||
end
|
||||
30: FOUT = D0; // FLAGS <- D0
|
||||
default:;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module daa (
|
||||
input [7:0]flags,
|
||||
input [7:0]val,
|
||||
output wire [7:0]adjust,
|
||||
output reg cdaa,
|
||||
output reg hdaa
|
||||
);
|
||||
|
||||
wire h08 = val[7:4] < 9;
|
||||
wire h09 = val[7:4] < 10;
|
||||
wire l05 = val[3:0] < 6;
|
||||
wire l09 = val[3:0] < 10;
|
||||
reg [1:0]aa;
|
||||
assign adjust = ({1'b0, aa[1], aa[1], 2'b0, aa[0], aa[0], 1'b0} ^ {8{flags[1]}}) + flags[1];
|
||||
|
||||
always @* begin
|
||||
case({flags[0], h08, h09, flags[4], l09})
|
||||
5'b00101, 5'b01101: aa = 0;
|
||||
5'b00111, 5'b01111, 5'b01000, 5'b01010, 5'b01100, 5'b01110: aa = 1;
|
||||
5'b00001, 5'b01001, 5'b10001, 5'b10101, 5'b11001, 5'b11101: aa = 2;
|
||||
default: aa = 3;
|
||||
endcase
|
||||
case({flags[0], h08, h09, l09})
|
||||
4'b0011, 4'b0111, 4'b0100, 4'b0110: cdaa = 0;
|
||||
default: cdaa = 1;
|
||||
endcase
|
||||
case({flags[1], flags[4], l05, l09})
|
||||
4'b0000, 4'b0010, 4'b0100, 4'b0110, 4'b1110, 4'b1111: hdaa = 1;
|
||||
default: hdaa = 0;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
|
||||
module ALU16(
|
||||
input [15:0] D0,
|
||||
input [7:0] D1,
|
||||
output wire[15:0] DOUT,
|
||||
input [2:0]OP // 0-NOP, 1-INC, 2-INC2, 3-ADD, 4-NOP, 5-DEC, 6-DEC2
|
||||
);
|
||||
|
||||
reg [15:0] mux;
|
||||
always @*
|
||||
case(OP)
|
||||
0: mux = 0; // post inc
|
||||
1: mux = 1; // post inc
|
||||
2: mux = 2; // post inc
|
||||
3: mux = {D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7], D1[7:0]}; // post inc
|
||||
4: mux = 0; // no post inc
|
||||
5: mux = 16'hffff; // no post inc
|
||||
6: mux = 16'hfffe; // no post inc
|
||||
default: mux = 16'hxxxx;
|
||||
endcase
|
||||
|
||||
assign DOUT = D0 + mux;
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,199 +0,0 @@
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file is part of the NextZ80 project
|
||||
// http://www.opencores.org/cores/nextz80/
|
||||
//
|
||||
// Filename: NextZ80Regs.v
|
||||
// Description: Implementation of Z80 compatible CPU - registers
|
||||
// Version 1.0
|
||||
// Creation date: 28Jan2011 - 18Mar2011
|
||||
//
|
||||
// Author: Nicolae Dumitrache
|
||||
// e-mail: ndumitrache@opencores.org
|
||||
//
|
||||
/////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2011 Nicolae Dumitrache
|
||||
//
|
||||
// This source file may be used and distributed without
|
||||
// restriction provided that this copyright statement is not
|
||||
// removed from the file and that any derivative work contains
|
||||
// the original copyright notice and the associated disclaimer.
|
||||
//
|
||||
// This source file is free software; you can redistribute it
|
||||
// and/or modify it under the terms of the GNU Lesser General
|
||||
// Public License as published by the Free Software Foundation;
|
||||
// either version 2.1 of the License, or (at your option) any
|
||||
// later version.
|
||||
//
|
||||
// This source is distributed in the hope that it will be
|
||||
// useful, but WITHOUT ANY WARRANTY; without even the implied
|
||||
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
|
||||
// PURPOSE. See the GNU Lesser General Public License for more
|
||||
// details.
|
||||
//
|
||||
// You should have received a copy of the GNU Lesser General
|
||||
// Public License along with this source; if not, download it
|
||||
// from http://www.opencores.org/lgpl.shtml
|
||||
//
|
||||
///////////////////////////////////////////////////////////////////////////////////
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
module Z80Reg(
|
||||
input wire [7:0]rstatus, // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy, 6=IFF1, 7=IFF2
|
||||
input wire M1,
|
||||
input wire [5:0]WE, // 5 = flags, 4 = PC, 3 = SP, 2 = tmpHI, 1 = hi, 0 = lo
|
||||
input wire CLK,
|
||||
input wire [15:0]ALU8OUT, // CPU data out bus (output of alu8)
|
||||
input wire [7:0]DI, // CPU data in bus
|
||||
output reg [7:0]DO, // CPU data out bus
|
||||
input wire [15:0]ADDR, // CPU addr bus
|
||||
input wire [7:0]CONST,
|
||||
output reg [7:0]ALU80,
|
||||
output reg [7:0]ALU81,
|
||||
output reg [15:0]ALU160,
|
||||
output wire[7:0]ALU161,
|
||||
input wire [7:0]ALU8FLAGS,
|
||||
output wire [7:0]FLAGS,
|
||||
|
||||
input wire [1:0]DO_SEL, // select DO betwen ALU8OUT lo and th register
|
||||
input wire ALU160_sel, // 0=REG_RSEL, 1=PC
|
||||
input wire [3:0]REG_WSEL, // rdow: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-x ----- [0] = 0HI,1LO
|
||||
input wire [3:0]REG_RSEL, // mux_rdor: [3:1] 0=BC, 1=DE, 2=HL, 3=A-TL, 4=I-R, 5=SP, 7=tmpSP ----- [0] = 0HI, 1LO
|
||||
input wire DINW_SEL, // select RAM write data between (0)ALU8OUT, and 1(DI)
|
||||
input wire XMASK, // 0 if REG_WSEL should not use IX, IY, even if rstatus[4] == 1
|
||||
input wire [2:0]ALU16OP, // ALU16OP
|
||||
input wire WAIT // wait
|
||||
);
|
||||
|
||||
// latch registers
|
||||
reg [15:0]pc=0; // program counter
|
||||
reg [15:0]sp; // stack pointer
|
||||
reg [7:0]r; // refresh
|
||||
reg [15:0]flg = 0;
|
||||
reg [7:0]th; // temp high
|
||||
|
||||
// internal wires
|
||||
wire [15:0]rdor; // R out from RAM
|
||||
wire [15:0]rdow; // W out from RAM
|
||||
wire [3:0]SELW; // RAM W port sel
|
||||
wire [3:0]SELR; // RAM R port sel
|
||||
reg [15:0]DIN; // RAM W in data
|
||||
reg [15:0]mux_rdor; // (3)A reversed mixed with TL, (4)I mixed with R (5)SP
|
||||
|
||||
//------------------------------------ RAM block registers ----------------------------------
|
||||
// 0:BC, 1:DE, 2:HL, 3:A-x, 4:I-x, 5:IX, 6:IY, 7:x-x, 8:BC', 9:DE', 10:HL', 11:A'-x, 12: tmpSP, 13:zero
|
||||
RAM16X8D_regs regs_lo (
|
||||
.DPO(rdor[7:0]), // Read-only data output
|
||||
.SPO(rdow[7:0]), // R/W data output
|
||||
.A(SELW), // R/W address
|
||||
.D(DIN[7:0]), // Write data input
|
||||
.DPRA(SELR), // Read-only address
|
||||
.WCLK(CLK), // Write clock input
|
||||
.WE(WE[0] & !WAIT) // Write enable input
|
||||
);
|
||||
|
||||
RAM16X8D_regs regs_hi (
|
||||
.DPO(rdor[15:8]), // Read-only data output
|
||||
.SPO(rdow[15:8]), // R/W data output
|
||||
.A(SELW), // R/W address
|
||||
.D(DIN[15:8]), // Write data input
|
||||
.DPRA(SELR), // Read-only address
|
||||
.WCLK(CLK), // Write clock input
|
||||
.WE(WE[1] & !WAIT) // Write enable input
|
||||
);
|
||||
|
||||
wire [15:0]ADDR1 = ADDR + !ALU16OP[2]; // address post increment
|
||||
wire [7:0]flgmux = {ALU8FLAGS[7:3], SELR[3:0] == 4'b0100 ? rstatus[7] : ALU8FLAGS[2], ALU8FLAGS[1:0]}; // LD A, I/R IFF2 flag on parity
|
||||
always @(posedge CLK)
|
||||
if(!WAIT) begin
|
||||
if(WE[2]) th <= DI;
|
||||
if(WE[3]) sp <= ADDR1;
|
||||
if(WE[4]) pc <= ADDR1;
|
||||
if({REG_WSEL, WE[0]} == 5'b10011) r <= ALU8OUT[7:0];
|
||||
else if(M1) r[6:0] <= r[6:0] + 1;
|
||||
if(WE[5])
|
||||
if(rstatus[0]) flg[15:8] <= flgmux;
|
||||
else flg[7:0] <= flgmux;
|
||||
end
|
||||
|
||||
assign ALU161 = th;
|
||||
assign FLAGS = rstatus[0] ? flg[15:8] : flg[7:0];
|
||||
|
||||
always @* begin
|
||||
DIN = DINW_SEL ? {DI, DI} : ALU8OUT;
|
||||
ALU80 = REG_WSEL[0] ? rdow[7:0] : rdow[15:8];
|
||||
ALU81 = REG_RSEL[0] ? mux_rdor[7:0] : mux_rdor[15:8];
|
||||
ALU160 = ALU160_sel ? pc : mux_rdor;
|
||||
|
||||
case({REG_WSEL[3], DO_SEL})
|
||||
0: DO = ALU80;
|
||||
1: DO = th;
|
||||
2: DO = FLAGS;
|
||||
3: DO = ALU8OUT[7:0];
|
||||
4: DO = pc[15:8];
|
||||
5: DO = pc[7:0];
|
||||
6: DO = sp[15:8];
|
||||
7: DO = sp[7:0];
|
||||
endcase
|
||||
case({ALU16OP == 4, REG_RSEL[3:0]})
|
||||
5'b01001, 5'b11001: mux_rdor = {rdor[15:8], r};
|
||||
5'b01010, 5'b01011: mux_rdor = sp;
|
||||
5'b01100, 5'b01101, 5'b11100, 5'b11101: mux_rdor = {8'b0, CONST};
|
||||
default: mux_rdor = rdor;
|
||||
endcase
|
||||
end
|
||||
|
||||
RegSelect WSelectW(.SEL(REG_WSEL[3:1]), .RAMSEL(SELW), .rstatus({rstatus[5], rstatus[4] & XMASK, rstatus[3:0]}));
|
||||
RegSelect WSelectR(.SEL(REG_RSEL[3:1]), .RAMSEL(SELR), .rstatus(rstatus[5:0]));
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module RegSelect(
|
||||
input [2:0]SEL,
|
||||
output reg [3:0]RAMSEL,
|
||||
input [5:0]rstatus // 0=af-af', 1=exx, 2=hl-de, 3=hl'-de',4=hl-ixy, 5=ix-iy
|
||||
);
|
||||
|
||||
always @* begin
|
||||
RAMSEL = 4'bxxxx;
|
||||
case(SEL)
|
||||
0: RAMSEL = {rstatus[1], 3'b000}; // BC
|
||||
1: //DE
|
||||
if(rstatus[{1'b1, rstatus[1]}]) RAMSEL = {rstatus[1], 3'b010}; // HL
|
||||
else RAMSEL = {rstatus[1], 3'b001}; // DE
|
||||
2: // HL
|
||||
case({rstatus[5:4], rstatus[{1'b1, rstatus[1]}]})
|
||||
0,4: RAMSEL = {rstatus[1], 3'b010}; // HL
|
||||
1,5: RAMSEL = {rstatus[1], 3'b001}; // DE
|
||||
2,3: RAMSEL = 4'b0101; // IX
|
||||
6,7: RAMSEL = 4'b0110; // IY
|
||||
endcase
|
||||
3: RAMSEL = {rstatus[0], 3'b011}; // A-TL
|
||||
4: RAMSEL = 4; // I-R
|
||||
5: RAMSEL = 12; // tmp SP
|
||||
6: RAMSEL = 13; // zero
|
||||
7: RAMSEL = 7; // temp reg for BIT/SET/RES
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module RAM16X8D_regs(
|
||||
output [7:0]DPO, // Read-only data output
|
||||
output [7:0]SPO, // R/W data output
|
||||
input [3:0]A, // R/W address
|
||||
input [7:0]D, // Write data input
|
||||
input [3:0]DPRA, // Read-only address
|
||||
input WCLK, // Write clock
|
||||
input WE // Write enable
|
||||
);
|
||||
|
||||
reg [7:0]data[15:0];
|
||||
assign DPO = data[DPRA];
|
||||
assign SPO = data[A];
|
||||
|
||||
always @(posedge WCLK)
|
||||
if(WE) data[A] <= D;
|
||||
|
||||
endmodule
|
||||
@@ -1,296 +0,0 @@
|
||||
module PIXEL_DISPLAY (
|
||||
pixel_clock,
|
||||
reset,
|
||||
|
||||
show_border,
|
||||
|
||||
// mode
|
||||
ag,
|
||||
gm,
|
||||
css,
|
||||
|
||||
// text
|
||||
char_column,
|
||||
char_line,
|
||||
subchar_line,
|
||||
subchar_pixel,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x,
|
||||
|
||||
// vram
|
||||
vram_rd_enable,
|
||||
vram_addr,
|
||||
vram_data,
|
||||
|
||||
// vga
|
||||
vga_red,
|
||||
vga_green,
|
||||
vga_blue
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
|
||||
input show_border;
|
||||
|
||||
// mode
|
||||
input ag;
|
||||
input [2:0] gm;
|
||||
input css;
|
||||
|
||||
// text
|
||||
input [6:0] char_column; // character number on the current line
|
||||
input [6:0] char_line; // line number on the screen
|
||||
input [4:0] subchar_line; // the line number within a character block 0-8
|
||||
input [3:0] subchar_pixel; // the pixel number within a character block 0-8
|
||||
|
||||
// graph
|
||||
input [8:0] graph_pixel; // pixel number on the current line
|
||||
input [9:0] graph_line_2x; // line number on the screen
|
||||
input [9:0] graph_line_3x; // line number on the screen
|
||||
|
||||
output vram_rd_enable;
|
||||
output reg [12:0] vram_addr;
|
||||
input [7:0] vram_data;
|
||||
|
||||
output [7:0] vga_red;
|
||||
output [7:0] vga_green;
|
||||
output [7:0] vga_blue;
|
||||
|
||||
|
||||
//// Label Definitions ////
|
||||
|
||||
// Note: all labels must match their defined length--shorter labels will be padded with solid blocks,
|
||||
// and longer labels will be truncated
|
||||
|
||||
// 48 character label for the example text
|
||||
|
||||
wire pixel_on; // high => output foreground color, low => output background color
|
||||
|
||||
|
||||
// 8p 代表每个点占用VGA水平 8 pixel
|
||||
// 2bit 代表每个点取2位值
|
||||
|
||||
wire [1:0] pixel_8p_2bit; // high => output foreground color, low => output background color
|
||||
wire [1:0] pixel_4p_2bit; // high => output foreground color, low => output background color
|
||||
wire pixel_4p_1bit; // high => output foreground color, low => output background color
|
||||
wire pixel_2p_1bit; // high => output foreground color, low => output background color
|
||||
|
||||
reg [7:0] latched_vram_data; // the data that will be written to character memory at the clock rise
|
||||
|
||||
// 锁存数据用于选择调色板
|
||||
reg [7:0] latched_palette_data;
|
||||
|
||||
assign vram_rd_enable = pixel_clock;
|
||||
|
||||
reg [23:0] latched_vga_rgb;
|
||||
wire [23:0] vga_rgb;
|
||||
|
||||
// write the appropriate character data to memory
|
||||
|
||||
always @ (posedge pixel_clock) begin
|
||||
if(ag==1'b0)
|
||||
begin
|
||||
if(subchar_pixel==4'b0001)
|
||||
vram_addr <= {4'b0,char_line[3:0], char_column[4:0]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(subchar_pixel==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
if(graph_pixel[3:0]==4'b0110)
|
||||
latched_palette_data <= latched_vram_data;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(gm)
|
||||
3'b000:
|
||||
begin
|
||||
// 64 x 64 x 4 gm: 000
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b001:
|
||||
begin
|
||||
// 128 x 64 x 2 gm: 001
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {3'b0, graph_line_3x[9:4], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b011:
|
||||
begin
|
||||
// 128 x 96 x 2 gm: 011
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {2'b0, graph_line_2x[9:3], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b100:
|
||||
begin
|
||||
// 128 x 96 x 4 gm: 100
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {1'b0, graph_line_2x[8:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b101:
|
||||
begin
|
||||
// 128 x 192 x 2 gm: 101
|
||||
if(graph_pixel[4:0]==5'b00001)
|
||||
vram_addr <= {1'b0, graph_line_2x[9:1], graph_pixel[8:5]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[4:0]==5'b00011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b110:
|
||||
begin
|
||||
// 128 x 192 x 4 gm: 110
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
3'b111:
|
||||
begin
|
||||
// 256 x 192 x 2 gm: 111
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {graph_line_2x[9:1], graph_pixel[8:4]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
default:
|
||||
begin
|
||||
// 128 x 64 x 4 gm: 010
|
||||
if(graph_pixel[3:0]==4'b0001)
|
||||
vram_addr <= {2'b0,graph_line_3x[9:3], graph_pixel[8:4]};
|
||||
//vram_addr <= {2'b0,graph_line_3x[8:3], graph_pixel[6:2]};
|
||||
// 对于同步sram需要等待 1 个时钟周期
|
||||
if(graph_pixel[3:0]==4'b0011)
|
||||
latched_vram_data <= vram_data;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
latched_vga_rgb <= vga_rgb;
|
||||
end
|
||||
|
||||
// palette
|
||||
/*
|
||||
位\色 绿 黄 蓝 红 浅黄 浅蓝 紫 橙
|
||||
D6 0 0 0 0 1 1 1 1
|
||||
D5 0 0 1 1 0 0 1 1
|
||||
D4 0 1 0 1 0 1 0 1
|
||||
|
||||
0x07 0xff 0x00 // GREEN
|
||||
0xff 0xff 0x00 // YELLOW
|
||||
0x3b 0x08 0xff // BLUE
|
||||
0xcc 0x00 0x3b // RED
|
||||
0xff 0xff 0xff // BUFF
|
||||
0x07 0xe3 0x99 // CYAN
|
||||
0xff 0x1c 0xff // MAGENTA
|
||||
0xff 0x81 0x00 // ORANGE
|
||||
|
||||
0x00 0x00 0x00 // BLACK
|
||||
0x07 0xff 0x00 // GREEN
|
||||
0x3b 0x08 0xff // BLUE
|
||||
0xff 0xff 0xff // BUFF
|
||||
|
||||
*/
|
||||
|
||||
wire [2:0] palette_bit_graph;
|
||||
|
||||
wire [23:0] palette_rgb_border = (~ag)?24'h000000: // 字符模式背景
|
||||
(css)?24'hffffff:24'h07ff00; // 图形模式背景
|
||||
|
||||
wire [23:0] palette_rgb_pixel = 24'h000000;
|
||||
wire [23:0] palette_rgb_background = 24'h07ff00;
|
||||
|
||||
// 64 x 64 x 4 gm: 000
|
||||
// 128 x 64 x 2 gm: 001
|
||||
// 128 x 64 x 4 gm: 010
|
||||
// 128 x 96 x 2 gm: 011
|
||||
// 128 x 96 x 4 gm: 100
|
||||
// 128 x 192 x 2 gm: 101
|
||||
// 128 x 192 x 4 gm: 110
|
||||
// 256 x 192 x 2 gm: 111
|
||||
|
||||
//assign palette_bit_graph = (ag)? {css, pixel_4p_2bit} : latched_palette_data[6:4];
|
||||
|
||||
assign palette_bit_graph = (~ag) ? latched_palette_data[6:4] :
|
||||
(gm==3'b000) ? {css, pixel_8p_2bit } :
|
||||
(gm==3'b001) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b010) ? {css, pixel_4p_2bit } :
|
||||
(gm==3'b011) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b100) ? {css, pixel_4p_2bit } :
|
||||
(gm==3'b101) ? {css, pixel_4p_1bit, pixel_4p_1bit } :
|
||||
(gm==3'b110) ? {css, pixel_4p_2bit } :
|
||||
{css, pixel_2p_1bit, pixel_2p_1bit } ;
|
||||
|
||||
wire [23:0] palette_rgb_graph = (palette_bit_graph==3'b000) ? 24'h07ff00 : // GREEN
|
||||
(palette_bit_graph==3'b001) ? 24'hffff00 : // YELLOW
|
||||
(palette_bit_graph==3'b010) ? 24'h3b08ff : // BLUE
|
||||
(palette_bit_graph==3'b011) ? 24'hcc003b : // RED
|
||||
(palette_bit_graph==3'b100) ? 24'hffffff : // BUFF
|
||||
(palette_bit_graph==3'b101) ? 24'h07e399 : // CYAN
|
||||
(palette_bit_graph==3'b110) ? 24'hff1cff : // MAGENTA
|
||||
24'hff8100 ; // ORANGE
|
||||
|
||||
/*
|
||||
24'h000000 // BLACK
|
||||
24'h07ff00 // GREEN
|
||||
24'h3b08ff // BLUE
|
||||
24'hffffff // BUFF
|
||||
*/
|
||||
|
||||
|
||||
// use the result of the character generator module to choose between the foreground and background color
|
||||
|
||||
assign vga_rgb = (show_border) ? palette_rgb_border :
|
||||
(ag) ? palette_rgb_graph :
|
||||
(~pixel_on) ? palette_rgb_pixel :
|
||||
(latched_palette_data[7]) ? palette_rgb_graph : palette_rgb_background;
|
||||
|
||||
assign vga_red = latched_vga_rgb[23:16];
|
||||
assign vga_green = latched_vga_rgb[15:8];
|
||||
assign vga_blue = latched_vga_rgb[7:0];
|
||||
|
||||
|
||||
// the character generator block includes the character RAM
|
||||
// and the character generator ROM
|
||||
CHAR_GEN CHAR_GEN
|
||||
(
|
||||
.reset(reset), // reset signal
|
||||
|
||||
.char_code(latched_vram_data),
|
||||
.subchar_line(subchar_line), // current line of pixels within current character
|
||||
.subchar_pixel(subchar_pixel), // current column of pixels withing current character
|
||||
|
||||
.pixel_clock(pixel_clock), // read clock
|
||||
.pixel_on(pixel_on) // read data
|
||||
);
|
||||
|
||||
PIXEL_GEN PIXEL_GEN
|
||||
(
|
||||
.reset(reset), // reset signal
|
||||
|
||||
.pixel_code(latched_vram_data),
|
||||
.graph_pixel(graph_pixel), // current column of pixels withing current character
|
||||
|
||||
.pixel_clock(pixel_clock), // read clock
|
||||
|
||||
.pixel_8p_2bit(pixel_8p_2bit), // 64x64x4
|
||||
.pixel_4p_2bit(pixel_4p_2bit), // 128x64x4 128x96x4 128x192x4
|
||||
.pixel_4p_1bit(pixel_4p_1bit), // 128x64x2 128x96x2 128x192x2
|
||||
.pixel_2p_1bit(pixel_2p_1bit) // 256x192x2
|
||||
);
|
||||
|
||||
endmodule //CHAR_DISPLAY
|
||||
@@ -1,129 +0,0 @@
|
||||
module PIXEL_GEN(
|
||||
// control
|
||||
reset,
|
||||
|
||||
pixel_code,
|
||||
graph_pixel,
|
||||
|
||||
pixel_clock,
|
||||
|
||||
pixel_8p_2bit, // 64x64x4
|
||||
pixel_4p_2bit, // 128x64x4 128x96x4 128x192x4
|
||||
pixel_4p_1bit, // 128x64x2 128x96x2 128x192x2
|
||||
pixel_2p_1bit // 256x192x2
|
||||
);
|
||||
|
||||
|
||||
input reset;
|
||||
|
||||
input [7:0] pixel_code;
|
||||
input [8:0] graph_pixel; // pixel number on the current line
|
||||
|
||||
input pixel_clock;
|
||||
|
||||
output reg [1:0] pixel_8p_2bit;
|
||||
output reg [1:0] pixel_4p_2bit;
|
||||
output reg pixel_4p_1bit;
|
||||
output reg pixel_2p_1bit;
|
||||
|
||||
reg [7:0] latched_8p_2bit_data;
|
||||
reg [7:0] latched_4p_2bit_data;
|
||||
reg [7:0] latched_4p_1bit_data;
|
||||
reg [7:0] latched_2p_1bit_data;
|
||||
|
||||
|
||||
// 移位寄存器有四种模式
|
||||
// 每2个点 移 1 位
|
||||
// 每4个点 移 2 位
|
||||
// 每4个点 移 1 位
|
||||
// 每8个点 移 2 位
|
||||
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_8p_2bit <= 2'b00;
|
||||
latched_8p_2bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[4:0])
|
||||
5'b00101:
|
||||
latched_8p_2bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[3:0]==3'b110)
|
||||
{pixel_8p_2bit,latched_8p_2bit_data[7:2]} <= latched_8p_2bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// 延时：图形模式 128x64 4色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_4p_2bit <= 2'b00;
|
||||
latched_4p_2bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[3:0])
|
||||
4'b0101:
|
||||
latched_4p_2bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[1:0]==2'b10)
|
||||
{pixel_4p_2bit,latched_4p_2bit_data[7:2]} <= latched_4p_2bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_4p_1bit <= 2'b00;
|
||||
latched_4p_1bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[4:0])
|
||||
5'b00101:
|
||||
latched_4p_1bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[1:0]==2'b10)
|
||||
{pixel_4p_1bit,latched_4p_1bit_data[7:1]} <= latched_4p_1bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
||||
// 延时：图形模式 256x192 2色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// serialize the GRAPH MODE data
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
pixel_2p_1bit <= 1'b0;
|
||||
latched_2p_1bit_data <= 8'h00;
|
||||
end
|
||||
else begin
|
||||
case(graph_pixel[3:0])
|
||||
4'b0101:
|
||||
latched_2p_1bit_data[7:0] <= pixel_code;
|
||||
default:
|
||||
if(graph_pixel[0]==1'b0)
|
||||
{pixel_2p_1bit,latched_2p_1bit_data[7:1]} <= latched_2p_1bit_data[7:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endmodule //PIXEL_GEN
|
||||
@@ -1,260 +0,0 @@
|
||||
/*
|
||||
---------------------------------------------------------------------------------
|
||||
To select a resolution and refresh rate, remove the comments around the desired
|
||||
block in this file. The pixel clock output by the DCM module should approximately
|
||||
equal the rate specified above the timing block that is uncommented.
|
||||
---------------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// DEFINE THE VARIOUS PIPELINE DELAYS
|
||||
|
||||
`define CHARACTER_DECODE_DELAY 4
|
||||
|
||||
|
||||
// 640 X 480 @ 60Hz with a 25.175MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 48 // pixels
|
||||
`define H_TOTAL 800 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 11 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 31 // lines
|
||||
`define V_TOTAL 524 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/4 = 25.000 MHz
|
||||
`define CLK_DIVIDE 4
|
||||
/*
|
||||
//generic composite,720x288p clk=13.5MHz
|
||||
`define H_ACTIVE 720
|
||||
`define H_FRONT_PORCH 20
|
||||
`define H_SYNCH 64
|
||||
`define H_BACK_PORCH 60
|
||||
`define H_TOTAL 800 // todo
|
||||
|
||||
`define V_ACTIVE 288
|
||||
`define V_FRONT_PORCH 1
|
||||
`define V_SYNCH 3
|
||||
`define V_BACK_PORCH 20
|
||||
`define V_TOTAL 524 // todo
|
||||
|
||||
`define CLK_MULTIPLY 27 // 50 * 27/100 = 13.500 MHz
|
||||
`define CLK_DIVIDE 100
|
||||
|
||||
// 640 X 480 @ 72Hz with a 31.500MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 40 // pixels
|
||||
`define H_BACK_PORCH 128 // pixels
|
||||
`define H_TOTAL 832 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 9 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 28 // lines
|
||||
`define V_TOTAL 520 // lines
|
||||
|
||||
`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 640 X 480 @ 75Hz with a 31.500MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 48 // pixels
|
||||
`define H_TOTAL 800 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 11 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 32 // lines
|
||||
`define V_TOTAL 525 // lines
|
||||
|
||||
`define CLK_MULTIPLY 5 // 50 * 5/8 = 31.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 640 X 480 @ 85Hz with a 36.000MHz pixel clock
|
||||
`define H_ACTIVE 640 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 48 // pixels
|
||||
`define H_BACK_PORCH 112 // pixels
|
||||
`define H_TOTAL 832 // pixels
|
||||
|
||||
`define V_ACTIVE 480 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 25 // lines
|
||||
`define V_TOTAL 509 // lines
|
||||
|
||||
`define CLK_MULTIPLY 18 // 50 * 18/25 = 36.000 MHz
|
||||
`define CLK_DIVIDE 25
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 56Hz with a 38.100MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 128 // pixels
|
||||
`define H_BACK_PORCH 128 // pixels
|
||||
`define H_TOTAL 1088 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 4 // lines
|
||||
`define V_BACK_PORCH 14 // lines
|
||||
`define V_TOTAL 619 // lines
|
||||
|
||||
`define CLK_MULTIPLY 16 // 50 * 16/21 = 38.095 MHz
|
||||
`define CLK_DIVIDE 21
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 60Hz with a 40.000MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 40 // pixels
|
||||
`define H_SYNCH 128 // pixels
|
||||
`define H_BACK_PORCH 88 // pixels
|
||||
`define H_TOTAL 1056 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 4 // lines
|
||||
`define V_BACK_PORCH 23 // lines
|
||||
`define V_TOTAL 628 // lines
|
||||
|
||||
`define CLK_MULTIPLY 4 // 50 * 4/5 = 40.000 MHz
|
||||
`define CLK_DIVIDE 5
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 72Hz with a 50.000MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 56 // pixels
|
||||
`define H_SYNCH 120 // pixels
|
||||
`define H_BACK_PORCH 64 // pixels
|
||||
`define H_TOTAL 1040 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 37 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 23 // lines
|
||||
`define V_TOTAL 666 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 75Hz with a 49.500MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 80 // pixels
|
||||
`define H_BACK_PORCH 160 // pixels
|
||||
`define H_TOTAL 1056 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 2 // lines
|
||||
`define V_BACK_PORCH 21 // lines
|
||||
`define V_TOTAL 624 // lines
|
||||
|
||||
`define CLK_MULTIPLY 2 // 50 * 2/2 = 50.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 800 X 600 @ 85Hz with a 56.250MHz pixel clock
|
||||
`define H_ACTIVE 800 // pixels
|
||||
`define H_FRONT_PORCH 32 // pixels
|
||||
`define H_SYNCH 64 // pixels
|
||||
`define H_BACK_PORCH 152 // pixels
|
||||
`define H_TOTAL 1048 // pixels
|
||||
|
||||
`define V_ACTIVE 600 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 27 // lines
|
||||
`define V_TOTAL 631 // lines
|
||||
|
||||
`define CLK_MULTIPLY 9 // 50 * 9/8 = 56.250 MHz
|
||||
`define CLK_DIVIDE 8
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 60Hz with a 65.000MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 136 // pixels
|
||||
`define H_BACK_PORCH 160 // pixels
|
||||
`define H_TOTAL 1344 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 3 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 29 // lines
|
||||
`define V_TOTAL 806 // lines
|
||||
|
||||
`define CLK_MULTIPLY 13 // 50 * 13/10 = 65.000 MHz
|
||||
`define CLK_DIVIDE 10
|
||||
/*
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 70Hz with a 75.000MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 24 // pixels
|
||||
`define H_SYNCH 136 // pixels
|
||||
`define H_BACK_PORCH 144 // pixels
|
||||
`define H_TOTAL 1328 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 3 // lines
|
||||
`define V_SYNCH 6 // lines
|
||||
`define V_BACK_PORCH 29 // lines
|
||||
`define V_TOTAL 806 // lines
|
||||
|
||||
`define CLK_MULTIPLY 3 // 50 * 3/2 = 75.000 MHz
|
||||
`define CLK_DIVIDE 2
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 75Hz with a 78.750MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 16 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 176 // pixels
|
||||
`define H_TOTAL 1312 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 28 // lines
|
||||
`define V_TOTAL 800 // lines
|
||||
|
||||
`define CLK_MULTIPLY 11 // 50 * 11/7 = 78.571 MHz
|
||||
`define CLK_DIVIDE 7
|
||||
*/
|
||||
|
||||
/*
|
||||
// 1024 X 768 @ 85Hz with a 94.500MHz pixel clock
|
||||
`define H_ACTIVE 1024 // pixels
|
||||
`define H_FRONT_PORCH 48 // pixels
|
||||
`define H_SYNCH 96 // pixels
|
||||
`define H_BACK_PORCH 208 // pixels
|
||||
`define H_TOTAL 1376 // pixels
|
||||
|
||||
`define V_ACTIVE 768 // lines
|
||||
`define V_FRONT_PORCH 1 // lines
|
||||
`define V_SYNCH 3 // lines
|
||||
`define V_BACK_PORCH 36 // lines
|
||||
`define V_TOTAL 808 // lines
|
||||
|
||||
`define CLK_MULTIPLY 17 // 50 * 17/9 = 94.444 MHz
|
||||
`define CLK_DIVIDE 9
|
||||
*/
|
||||
|
||||
@@ -1,353 +0,0 @@
|
||||
`include "SVGA_DEFINES.v"
|
||||
|
||||
|
||||
`define SVGA_DECODE_DELAY 7
|
||||
// 延时：字符模式
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)字库地址 5、(101)锁存字库
|
||||
// 6、(110)移位得到点阵，同时锁存vram数据用于调色板 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// Delay: Character mode
|
||||
// 1 (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) font address 5, (101) latch font
|
||||
// 6, (110) shift to get a lattice, while latching vram data for the palette 7, (111) to create a palette, latch color
|
||||
|
||||
// 延时：图形模式 128x64 4色
|
||||
// 1、(001)锁存 vram 地址，2、(010)读取 vram 3、(011)锁存 vram 数据 4、(100)空 5、(101)数据锁存至移位寄存器
|
||||
// 6、(110)移位得到点阵 7、(111)建立调色板，锁存色彩
|
||||
|
||||
// Delay: graphics mode 128x64 4 colors
|
||||
// 1, (001) latch vram address, 2, (010) read vram 3, (011) latch vram data 4, (100) empty 5, (101) data latched to the shift register
|
||||
// 6, (110) shift to get the dot matrix 7, (111) to create a palette, latch color
|
||||
|
||||
module SVGA_TIMING_GENERATION
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
pixel_count,
|
||||
line_count,
|
||||
|
||||
show_border,
|
||||
|
||||
// text
|
||||
subchar_pixel,
|
||||
subchar_line,
|
||||
char_column,
|
||||
char_line,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x
|
||||
);
|
||||
|
||||
input pixel_clock; // pixel clock
|
||||
input reset; // reset
|
||||
(*keep*)output reg h_synch; // horizontal synch for VGA connector
|
||||
(*keep*)output reg v_synch; // vertical synch for VGA connector
|
||||
output reg blank; // composite blanking
|
||||
output reg [10:0] pixel_count; // counts the pixels in a line
|
||||
output reg [9:0] line_count; // counts the display lines
|
||||
|
||||
(*keep*)output reg show_border;
|
||||
|
||||
// 字符控制
|
||||
(*keep*)output reg [3:0] subchar_pixel; // pixel position within the character
|
||||
(*keep*)output reg [4:0] subchar_line; // identifies the line number within a character block
|
||||
(*keep*)output reg [6:0] char_column; // character number on the current line
|
||||
(*keep*)output reg [6:0] char_line; // line number on the screen
|
||||
|
||||
// 图形控制 128*64
|
||||
(*keep*)output reg [8:0] graph_pixel;
|
||||
(*keep*)output reg [9:0] graph_line_3x;
|
||||
|
||||
// 图形控制 256*192
|
||||
(*keep*)output reg [9:0] graph_line_2x;
|
||||
|
||||
(*keep*)reg h_blank;
|
||||
reg v_blank;
|
||||
|
||||
reg show_pixel;
|
||||
reg show_line;
|
||||
|
||||
// CREATE THE HORIZONTAL LINE PIXEL COUNTER
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset set pixel counter to 0
|
||||
pixel_count <= 11'd0;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL - 1))
|
||||
// last pixel in the line, so reset pixel counter
|
||||
pixel_count <= 11'd0;
|
||||
|
||||
else
|
||||
pixel_count <= pixel_count + 1;
|
||||
end
|
||||
|
||||
// CREATE THE HORIZONTAL SYNCH PULSE
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove h_synch
|
||||
h_synch <= 1'b0;
|
||||
|
||||
else if (pixel_count == (`H_ACTIVE + `H_FRONT_PORCH - 1))
|
||||
// start of h_synch
|
||||
h_synch <= 1'b1;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL - `H_BACK_PORCH - 1))
|
||||
// end of h_synch
|
||||
h_synch <= 1'b0;
|
||||
end
|
||||
|
||||
// CREATE THE VERTICAL FRAME LINE COUNTER
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset set line counter to 0
|
||||
line_count <= 10'd0;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - 1)) & (pixel_count == (`H_TOTAL - 1)))
|
||||
// last pixel in last line of frame, so reset line counter
|
||||
line_count <= 10'd0;
|
||||
|
||||
else if ((pixel_count == (`H_TOTAL - 1)))
|
||||
// last pixel but not last line, so increment line counter
|
||||
line_count <= line_count + 1;
|
||||
end
|
||||
|
||||
// CREATE THE VERTICAL SYNCH PULSE
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove v_synch
|
||||
v_synch <= 1'b0;
|
||||
|
||||
else if ((line_count == (`V_ACTIVE + `V_FRONT_PORCH - 1) &
|
||||
(pixel_count == `H_TOTAL - 1)))
|
||||
// start of v_synch
|
||||
v_synch <= 1'b1;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - `V_BACK_PORCH - 1)) &
|
||||
(pixel_count == (`H_TOTAL - 1)))
|
||||
// end of v_synch
|
||||
v_synch <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE HORIZONTAL BLANKING SIGNAL
|
||||
// the "-2" is used instead of "-1" because of the extra register delay
|
||||
// for the composite blanking signal
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove the h_blank
|
||||
h_blank <= 1'b0;
|
||||
|
||||
else if (pixel_count == (`H_ACTIVE -2))
|
||||
// start of HBI
|
||||
h_blank <= 1'b1;
|
||||
|
||||
else if (pixel_count == (`H_TOTAL -2))
|
||||
// end of HBI
|
||||
h_blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE VERTICAL BLANKING SIGNAL
|
||||
// the "-2" is used instead of "-1" in the horizontal factor because of the extra
|
||||
// register delay for the composite blanking signal
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove v_blank
|
||||
v_blank <= 1'b0;
|
||||
|
||||
else if ((line_count == (`V_ACTIVE - 1) &
|
||||
(pixel_count == `H_TOTAL - 2)))
|
||||
// start of VBI
|
||||
v_blank <= 1'b1;
|
||||
|
||||
else if ((line_count == (`V_TOTAL - 1)) &
|
||||
(pixel_count == (`H_TOTAL - 2)))
|
||||
// end of VBI
|
||||
v_blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
// CREATE THE COMPOSITE BANKING SIGNAL
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
// on reset remove blank
|
||||
blank <= 1'b0;
|
||||
|
||||
// blank during HBI or VBI
|
||||
else if (h_blank || v_blank)
|
||||
blank <= 1'b1;
|
||||
|
||||
else
|
||||
// active video do not blank
|
||||
blank <= 1'b0;
|
||||
end
|
||||
|
||||
|
||||
////////////////////////////////////////////////////
|
||||
// 以上部分内容相对固定，是VGA的控制信号和计数器 //
|
||||
////////////////////////////////////////////////////
|
||||
|
||||
|
||||
/*
|
||||
CREATE THE CHARACTER COUNTER.
|
||||
CHARACTERS ARE DEFINED WITHIN AN 8 x 8 PIXEL BLOCK.
|
||||
|
||||
A 640 x 480 video mode will display 80 characters on 60 lines.
|
||||
A 800 x 600 video mode will display 100 characters on 75 lines.
|
||||
A 1024 x 768 video mode will display 128 characters on 96 lines.
|
||||
|
||||
"subchar_line" identifies the row in the 8 x 8 block.
|
||||
"subchar_pixel" identifies the column in the 8 x 8 block.
|
||||
*/
|
||||
|
||||
// 8x12点阵 32x16个字符 256x192
|
||||
// 640x480 倍线 512x384 左右各空64个点，上下空 48 个点。
|
||||
// 需要生成四个数据：
|
||||
// 字符点阵 subchar_line subchar_pixel
|
||||
// 字符寻址 char_column char_line
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
show_pixel <= 1'b0;
|
||||
else if (pixel_count == (-1) + 64 - `SVGA_DECODE_DELAY)
|
||||
show_pixel <= 1'b1;
|
||||
else if (pixel_count == (`H_ACTIVE - 1) - 64 - `SVGA_DECODE_DELAY)
|
||||
show_pixel <= 1'b0;
|
||||
end
|
||||
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
show_line <= 1'b0;
|
||||
else if (line_count == (-1) + 48)
|
||||
show_line <= 1'b1;
|
||||
else if (line_count == (`V_ACTIVE - 1) - 48)
|
||||
show_line <= 1'b0;
|
||||
end
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
show_border <= 1'b1;
|
||||
else if (pixel_count == (-1) + 64)
|
||||
show_border <= ~show_line;
|
||||
else if (pixel_count == (`H_ACTIVE - 1) - 64)
|
||||
show_border <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// text 32x16
|
||||
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
subchar_pixel <= 4'b0000;
|
||||
char_column <= 7'd0;
|
||||
end
|
||||
else if (h_synch)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
subchar_pixel <= 4'b0000;
|
||||
char_column <= 7'd0;
|
||||
end
|
||||
else if(show_pixel)
|
||||
begin
|
||||
subchar_pixel <= subchar_pixel + 1;
|
||||
if(subchar_pixel == 4'b1111) // 8*2-1
|
||||
char_column <= char_column + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= 7'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= 7'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
if(subchar_line == 5'd23) // 12*2-1
|
||||
begin
|
||||
subchar_line <= 5'b00000;
|
||||
char_line <= char_line + 1;
|
||||
end
|
||||
else
|
||||
// increment line counter
|
||||
subchar_line <= subchar_line + 1;
|
||||
end
|
||||
|
||||
|
||||
// 为所有图形模式提供水平计数
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
graph_pixel <= 9'd0;
|
||||
end
|
||||
else if (h_synch)
|
||||
begin
|
||||
// reset to 5 so that the first character data can be latched
|
||||
graph_pixel <= 9'd0;
|
||||
end
|
||||
else if(show_pixel)
|
||||
begin
|
||||
graph_pixel <= graph_pixel + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// 为图形模式提供垂直计数
|
||||
// 64x64 4色
|
||||
// 128x64 2色
|
||||
// 128x64 4色
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
graph_line_3x <= 10'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
graph_line_3x <= 10'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
if(graph_line_3x[1:0] == 2'b10) // 3行为单位计数
|
||||
graph_line_3x <= graph_line_3x + 2;
|
||||
else
|
||||
// increment line counter
|
||||
graph_line_3x <= graph_line_3x + 1;
|
||||
end
|
||||
|
||||
// 为图形模式提供垂直计数
|
||||
// 128x96 2色
|
||||
// 128x96 4色
|
||||
// 128x192 2色
|
||||
// 128x192 4色
|
||||
// 256x192 2色
|
||||
always @ (posedge h_synch or posedge reset) begin
|
||||
if (reset)
|
||||
begin
|
||||
// on reset set line counter to 0
|
||||
graph_line_2x <= 10'd0;
|
||||
end
|
||||
else if(v_synch)
|
||||
begin
|
||||
// reset line counter
|
||||
graph_line_2x <= 10'd0;
|
||||
end
|
||||
else if(show_line)
|
||||
// increment line counter
|
||||
graph_line_2x <= graph_line_2x + 1;
|
||||
end
|
||||
|
||||
endmodule //SVGA_TIMING_GENERATION
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,371 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0247
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
|
||||
--
|
||||
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
|
||||
--
|
||||
-- 0240 : Added GB operations
|
||||
--
|
||||
-- 0242 : Cleanup
|
||||
--
|
||||
-- 0247 : Cleanup
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_ALU is
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_ALU;
|
||||
|
||||
architecture rtl of T80_ALU is
|
||||
|
||||
procedure AddSub(A : std_logic_vector;
|
||||
B : std_logic_vector;
|
||||
Sub : std_logic;
|
||||
Carry_In : std_logic;
|
||||
signal Res : out std_logic_vector;
|
||||
signal Carry : out std_logic) is
|
||||
|
||||
variable B_i : unsigned(A'length - 1 downto 0);
|
||||
variable Res_i : unsigned(A'length + 1 downto 0);
|
||||
begin
|
||||
if Sub = '1' then
|
||||
B_i := not unsigned(B);
|
||||
else
|
||||
B_i := unsigned(B);
|
||||
end if;
|
||||
|
||||
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
|
||||
Carry <= Res_i(A'length + 1);
|
||||
Res <= std_logic_vector(Res_i(A'length downto 1));
|
||||
end;
|
||||
|
||||
-- AddSub variables (temporary signals)
|
||||
signal UseCarry : std_logic;
|
||||
signal Carry7_v : std_logic;
|
||||
signal Overflow_v : std_logic;
|
||||
signal HalfCarry_v : std_logic;
|
||||
signal Carry_v : std_logic;
|
||||
signal Q_v : std_logic_vector(7 downto 0);
|
||||
|
||||
signal BitMask : std_logic_vector(7 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with IR(5 downto 3) select BitMask <= "00000001" when "000",
|
||||
"00000010" when "001",
|
||||
"00000100" when "010",
|
||||
"00001000" when "011",
|
||||
"00010000" when "100",
|
||||
"00100000" when "101",
|
||||
"01000000" when "110",
|
||||
"10000000" when others;
|
||||
|
||||
UseCarry <= not ALU_Op(2) and ALU_Op(0);
|
||||
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
|
||||
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
|
||||
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
|
||||
|
||||
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
|
||||
process (Carry_v, Carry7_v, Q_v)
|
||||
begin
|
||||
if(Mode=2) then
|
||||
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
|
||||
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
|
||||
OverFlow_v <= Carry_v xor Carry7_v;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
variable Q_t : std_logic_vector(7 downto 0);
|
||||
variable DAA_Q : unsigned(8 downto 0);
|
||||
begin
|
||||
Q_t := "--------";
|
||||
F_Out <= F_In;
|
||||
DAA_Q := "---------";
|
||||
case ALU_Op is
|
||||
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_C) <= '0';
|
||||
case ALU_OP(2 downto 0) is
|
||||
when "000" | "001" => -- ADD, ADC
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_C) <= Carry_v;
|
||||
F_Out(Flag_H) <= HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "010" | "011" | "111" => -- SUB, SBC, CP
|
||||
Q_t := Q_v;
|
||||
F_Out(Flag_N) <= '1';
|
||||
F_Out(Flag_C) <= not Carry_v;
|
||||
F_Out(Flag_H) <= not HalfCarry_v;
|
||||
F_Out(Flag_P) <= OverFlow_v;
|
||||
when "100" => -- AND
|
||||
Q_t(7 downto 0) := BusA and BusB;
|
||||
F_Out(Flag_H) <= '1';
|
||||
when "101" => -- XOR
|
||||
Q_t(7 downto 0) := BusA xor BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
when others => -- OR "110"
|
||||
Q_t(7 downto 0) := BusA or BusB;
|
||||
F_Out(Flag_H) <= '0';
|
||||
end case;
|
||||
if ALU_Op(2 downto 0) = "111" then -- CP
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
else
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
end if;
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
if Z16 = '1' then
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
|
||||
end if;
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
case ALU_Op(2 downto 0) is
|
||||
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
|
||||
when others =>
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
end case;
|
||||
if Arith16 = '1' then
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
end if;
|
||||
when "1100" =>
|
||||
-- DAA
|
||||
F_Out(Flag_H) <= F_In(Flag_H);
|
||||
F_Out(Flag_C) <= F_In(Flag_C);
|
||||
DAA_Q(7 downto 0) := unsigned(BusA);
|
||||
DAA_Q(8) := '0';
|
||||
if F_In(Flag_N) = '0' then
|
||||
-- After addition
|
||||
-- Alow > 9 or H = 1
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if (DAA_Q(3 downto 0) > 9) then
|
||||
F_Out(Flag_H) <= '1';
|
||||
else
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q := DAA_Q + 6;
|
||||
end if;
|
||||
-- new Ahigh > 9 or C = 1
|
||||
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q + 96; -- 0x60
|
||||
end if;
|
||||
else
|
||||
-- After subtraction
|
||||
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
|
||||
if DAA_Q(3 downto 0) > 5 then
|
||||
F_Out(Flag_H) <= '0';
|
||||
end if;
|
||||
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
|
||||
end if;
|
||||
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
|
||||
DAA_Q := DAA_Q - 352; -- 0x160
|
||||
end if;
|
||||
end if;
|
||||
F_Out(Flag_X) <= DAA_Q(3);
|
||||
F_Out(Flag_Y) <= DAA_Q(5);
|
||||
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
|
||||
Q_t := std_logic_vector(DAA_Q(7 downto 0));
|
||||
if DAA_Q(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= DAA_Q(7);
|
||||
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
|
||||
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
|
||||
when "1101" | "1110" =>
|
||||
-- RLD, RRD
|
||||
Q_t(7 downto 4) := BusA(7 downto 4);
|
||||
if ALU_Op(0) = '1' then
|
||||
Q_t(3 downto 0) := BusB(7 downto 4);
|
||||
else
|
||||
Q_t(3 downto 0) := BusB(3 downto 0);
|
||||
end if;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
when "1001" =>
|
||||
-- BIT
|
||||
Q_t(7 downto 0) := BusB and BitMask;
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
F_Out(Flag_P) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
F_Out(Flag_P) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_H) <= '1';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= '0';
|
||||
F_Out(Flag_Y) <= '0';
|
||||
if IR(2 downto 0) /= "110" then
|
||||
F_Out(Flag_X) <= BusB(3);
|
||||
F_Out(Flag_Y) <= BusB(5);
|
||||
end if;
|
||||
when "1010" =>
|
||||
-- SET
|
||||
Q_t(7 downto 0) := BusB or BitMask;
|
||||
when "1011" =>
|
||||
-- RES
|
||||
Q_t(7 downto 0) := BusB and not BitMask;
|
||||
when "1000" =>
|
||||
-- ROT
|
||||
case IR(5 downto 3) is
|
||||
when "000" => -- RLC
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "010" => -- RL
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "001" => -- RRC
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(0);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "011" => -- RR
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := F_In(Flag_C);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when "100" => -- SLA
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '0';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
when "110" => -- SLL (Undocumented) / SWAP
|
||||
if Mode = 3 then
|
||||
Q_t(7 downto 4) := BusA(3 downto 0);
|
||||
Q_t(3 downto 0) := BusA(7 downto 4);
|
||||
F_Out(Flag_C) <= '0';
|
||||
else
|
||||
Q_t(7 downto 1) := BusA(6 downto 0);
|
||||
Q_t(0) := '1';
|
||||
F_Out(Flag_C) <= BusA(7);
|
||||
end if;
|
||||
when "101" => -- SRA
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := BusA(7);
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
when others => -- SRL
|
||||
Q_t(6 downto 0) := BusA(7 downto 1);
|
||||
Q_t(7) := '0';
|
||||
F_Out(Flag_C) <= BusA(0);
|
||||
end case;
|
||||
F_Out(Flag_H) <= '0';
|
||||
F_Out(Flag_N) <= '0';
|
||||
F_Out(Flag_X) <= Q_t(3);
|
||||
F_Out(Flag_Y) <= Q_t(5);
|
||||
F_Out(Flag_S) <= Q_t(7);
|
||||
if Q_t(7 downto 0) = "00000000" then
|
||||
F_Out(Flag_Z) <= '1';
|
||||
else
|
||||
F_Out(Flag_Z) <= '0';
|
||||
end if;
|
||||
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
|
||||
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
|
||||
if ISet = "00" then
|
||||
F_Out(Flag_P) <= F_In(Flag_P);
|
||||
F_Out(Flag_S) <= F_In(Flag_S);
|
||||
F_Out(Flag_Z) <= F_In(Flag_Z);
|
||||
end if;
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
Q <= Q_t;
|
||||
end process;
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,217 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
--
|
||||
-- Z80 compatible microprocessor core
|
||||
--
|
||||
-- Version : 0242
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package T80_Pack is
|
||||
|
||||
component T80
|
||||
generic(
|
||||
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
IORQ : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DInst : in std_logic_vector(7 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0);
|
||||
MC : out std_logic_vector(2 downto 0);
|
||||
TS : out std_logic_vector(2 downto 0);
|
||||
IntCycle_n : out std_logic;
|
||||
IntE : out std_logic;
|
||||
Stop : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_Reg
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_MCode
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
IR : in std_logic_vector(7 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
MCycle : in std_logic_vector(2 downto 0);
|
||||
F : in std_logic_vector(7 downto 0);
|
||||
NMICycle : in std_logic;
|
||||
IntCycle : in std_logic;
|
||||
MCycles : out std_logic_vector(2 downto 0);
|
||||
TStates : out std_logic_vector(2 downto 0);
|
||||
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
|
||||
Inc_PC : out std_logic;
|
||||
Inc_WZ : out std_logic;
|
||||
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
|
||||
Read_To_Reg : out std_logic;
|
||||
Read_To_Acc : out std_logic;
|
||||
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
|
||||
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
|
||||
ALU_Op : out std_logic_vector(3 downto 0);
|
||||
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
|
||||
Save_ALU : out std_logic;
|
||||
PreserveC : out std_logic;
|
||||
Arith16 : out std_logic;
|
||||
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
|
||||
IORQ : out std_logic;
|
||||
Jump : out std_logic;
|
||||
JumpE : out std_logic;
|
||||
JumpXY : out std_logic;
|
||||
Call : out std_logic;
|
||||
RstP : out std_logic;
|
||||
LDZ : out std_logic;
|
||||
LDW : out std_logic;
|
||||
LDSPHL : out std_logic;
|
||||
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
|
||||
ExchangeDH : out std_logic;
|
||||
ExchangeRp : out std_logic;
|
||||
ExchangeAF : out std_logic;
|
||||
ExchangeRS : out std_logic;
|
||||
I_DJNZ : out std_logic;
|
||||
I_CPL : out std_logic;
|
||||
I_CCF : out std_logic;
|
||||
I_SCF : out std_logic;
|
||||
I_RETN : out std_logic;
|
||||
I_BT : out std_logic;
|
||||
I_BC : out std_logic;
|
||||
I_BTR : out std_logic;
|
||||
I_RLD : out std_logic;
|
||||
I_RRD : out std_logic;
|
||||
I_INRC : out std_logic;
|
||||
SetDI : out std_logic;
|
||||
SetEI : out std_logic;
|
||||
IMode : out std_logic_vector(1 downto 0);
|
||||
Halt : out std_logic;
|
||||
NoRead : out std_logic;
|
||||
Write : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
component T80_ALU
|
||||
generic(
|
||||
Mode : integer := 0;
|
||||
Flag_C : integer := 0;
|
||||
Flag_N : integer := 1;
|
||||
Flag_P : integer := 2;
|
||||
Flag_X : integer := 3;
|
||||
Flag_H : integer := 4;
|
||||
Flag_Y : integer := 5;
|
||||
Flag_Z : integer := 6;
|
||||
Flag_S : integer := 7
|
||||
);
|
||||
port(
|
||||
Arith16 : in std_logic;
|
||||
Z16 : in std_logic;
|
||||
ALU_Op : in std_logic_vector(3 downto 0);
|
||||
IR : in std_logic_vector(5 downto 0);
|
||||
ISet : in std_logic_vector(1 downto 0);
|
||||
BusA : in std_logic_vector(7 downto 0);
|
||||
BusB : in std_logic_vector(7 downto 0);
|
||||
F_In : in std_logic_vector(7 downto 0);
|
||||
Q : out std_logic_vector(7 downto 0);
|
||||
F_Out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
@@ -1,105 +0,0 @@
|
||||
--
|
||||
-- T80 Registers, technology independent
|
||||
--
|
||||
-- Version : 0244
|
||||
--
|
||||
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t51/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0242 : Initial release
|
||||
--
|
||||
-- 0244 : Changed to single register file
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
|
||||
entity T80_Reg is
|
||||
port(
|
||||
Clk : in std_logic;
|
||||
CEN : in std_logic;
|
||||
WEH : in std_logic;
|
||||
WEL : in std_logic;
|
||||
AddrA : in std_logic_vector(2 downto 0);
|
||||
AddrB : in std_logic_vector(2 downto 0);
|
||||
AddrC : in std_logic_vector(2 downto 0);
|
||||
DIH : in std_logic_vector(7 downto 0);
|
||||
DIL : in std_logic_vector(7 downto 0);
|
||||
DOAH : out std_logic_vector(7 downto 0);
|
||||
DOAL : out std_logic_vector(7 downto 0);
|
||||
DOBH : out std_logic_vector(7 downto 0);
|
||||
DOBL : out std_logic_vector(7 downto 0);
|
||||
DOCH : out std_logic_vector(7 downto 0);
|
||||
DOCL : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80_Reg;
|
||||
|
||||
architecture rtl of T80_Reg is
|
||||
|
||||
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
|
||||
signal RegsH : Register_Image(0 to 7);
|
||||
signal RegsL : Register_Image(0 to 7);
|
||||
|
||||
begin
|
||||
|
||||
process (Clk)
|
||||
begin
|
||||
if Clk'event and Clk = '1' then
|
||||
if CEN = '1' then
|
||||
if WEH = '1' then
|
||||
RegsH(to_integer(unsigned(AddrA))) <= DIH;
|
||||
end if;
|
||||
if WEL = '1' then
|
||||
RegsL(to_integer(unsigned(AddrA))) <= DIL;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DOAH <= RegsH(to_integer(unsigned(AddrA)));
|
||||
DOAL <= RegsL(to_integer(unsigned(AddrA)));
|
||||
DOBH <= RegsH(to_integer(unsigned(AddrB)));
|
||||
DOBL <= RegsL(to_integer(unsigned(AddrB)));
|
||||
DOCH <= RegsH(to_integer(unsigned(AddrC)));
|
||||
DOCL <= RegsL(to_integer(unsigned(AddrC)));
|
||||
|
||||
end;
|
||||
@@ -1,179 +0,0 @@
|
||||
-- ****
|
||||
-- T80(b) core. In an effort to merge and maintain bug fixes ....
|
||||
--
|
||||
--
|
||||
-- Ver 300 started tidyup
|
||||
-- MikeJ March 2005
|
||||
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
|
||||
--
|
||||
-- ****
|
||||
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
|
||||
--
|
||||
-- Z80 compatible microprocessor core, synchronous top level with clock enable
|
||||
-- Different timing than the original z80
|
||||
-- Inputs needs to be synchronous and outputs may glitch
|
||||
--
|
||||
-- Version : 0238
|
||||
--
|
||||
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-- The latest version of this file can be found at:
|
||||
-- http://www.opencores.org/cvsweb.shtml/t80/
|
||||
--
|
||||
-- Limitations :
|
||||
--
|
||||
-- File history :
|
||||
--
|
||||
-- 0235 : First release
|
||||
--
|
||||
-- 0236 : Added T2Write generic
|
||||
--
|
||||
-- 0237 : Fixed T2Write with wait state
|
||||
--
|
||||
-- 0238 : Updated for T80 interface change
|
||||
--
|
||||
-- 0242 : Updated for T80 interface change
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.T80_Pack.all;
|
||||
|
||||
entity T80sed is
|
||||
port(
|
||||
RESET_n : in std_logic;
|
||||
CLK_n : in std_logic;
|
||||
CLKEN : in std_logic;
|
||||
WAIT_n : in std_logic;
|
||||
INT_n : in std_logic;
|
||||
NMI_n : in std_logic;
|
||||
BUSRQ_n : in std_logic;
|
||||
M1_n : out std_logic;
|
||||
MREQ_n : out std_logic;
|
||||
IORQ_n : out std_logic;
|
||||
RD_n : out std_logic;
|
||||
WR_n : out std_logic;
|
||||
RFSH_n : out std_logic;
|
||||
HALT_n : out std_logic;
|
||||
BUSAK_n : out std_logic;
|
||||
A : out std_logic_vector(15 downto 0);
|
||||
DI : in std_logic_vector(7 downto 0);
|
||||
DO : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end T80sed;
|
||||
|
||||
architecture rtl of T80sed is
|
||||
|
||||
signal IntCycle_n : std_logic;
|
||||
signal NoRead : std_logic;
|
||||
signal Write : std_logic;
|
||||
signal IORQ : std_logic;
|
||||
signal DI_Reg : std_logic_vector(7 downto 0);
|
||||
signal MCycle : std_logic_vector(2 downto 0);
|
||||
signal TState : std_logic_vector(2 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
u0 : T80
|
||||
generic map(
|
||||
Mode => 0,
|
||||
IOWait => 1)
|
||||
port map(
|
||||
CEN => CLKEN,
|
||||
M1_n => M1_n,
|
||||
IORQ => IORQ,
|
||||
NoRead => NoRead,
|
||||
Write => Write,
|
||||
RFSH_n => RFSH_n,
|
||||
HALT_n => HALT_n,
|
||||
WAIT_n => Wait_n,
|
||||
INT_n => INT_n,
|
||||
NMI_n => NMI_n,
|
||||
RESET_n => RESET_n,
|
||||
BUSRQ_n => BUSRQ_n,
|
||||
BUSAK_n => BUSAK_n,
|
||||
CLK_n => CLK_n,
|
||||
A => A,
|
||||
DInst => DI,
|
||||
DI => DI_Reg,
|
||||
DO => DO,
|
||||
MC => MCycle,
|
||||
TS => TState,
|
||||
IntCycle_n => IntCycle_n);
|
||||
|
||||
process (RESET_n, CLK_n)
|
||||
begin
|
||||
if RESET_n = '0' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
DI_Reg <= "00000000";
|
||||
elsif CLK_n'event and CLK_n = '1' then
|
||||
if CLKEN = '1' then
|
||||
RD_n <= '1';
|
||||
WR_n <= '1';
|
||||
IORQ_n <= '1';
|
||||
MREQ_n <= '1';
|
||||
if MCycle = "001" then
|
||||
if TState = "001" or (TState = "010" and Wait_n = '0') then
|
||||
RD_n <= not IntCycle_n;
|
||||
MREQ_n <= not IntCycle_n;
|
||||
IORQ_n <= IntCycle_n;
|
||||
end if;
|
||||
if TState = "011" then
|
||||
MREQ_n <= '0';
|
||||
end if;
|
||||
else
|
||||
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
|
||||
RD_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
if ((TState = "001") or (TState = "010")) and Write = '1' then
|
||||
WR_n <= '0';
|
||||
IORQ_n <= not IORQ;
|
||||
MREQ_n <= IORQ;
|
||||
end if;
|
||||
end if;
|
||||
if TState = "010" and Wait_n = '1' then
|
||||
DI_Reg <= DI;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end;
|
||||
@@ -1,483 +0,0 @@
|
||||
|
||||
|
||||
|
||||
|
||||
// keyboard
|
||||
|
||||
/*****************************************************************************
|
||||
* Convert PS/2 keyboard to ASCII keyboard
|
||||
******************************************************************************/
|
||||
|
||||
/*
|
||||
KD5 KD4 KD3 KD2 KD1 KD0 扫描用地址
|
||||
A0 R Q E W T 68FEH 0
|
||||
A1 F A D CTRL S G 68FDH 8
|
||||
A2 V Z C SHFT X B 68FBH 16
|
||||
A3 4 1 3 2 5 68F7H 24
|
||||
A4 M 空格 ， . N 68EFH 32
|
||||
A5 7 0 8 - 9 6 68DFH 40
|
||||
A6 U P I RETN O Y 68BFH 48
|
||||
A7 J ； K : L H 687FH 56
|
||||
*/
|
||||
|
||||
// 7: 0
|
||||
// 15: 8
|
||||
// 23:16
|
||||
// 31:24
|
||||
// 39:32
|
||||
// 47:40
|
||||
// 55:48
|
||||
// 63:56
|
||||
|
||||
|
||||
|
||||
// 键盘检测的方法，就是循环地问每一行线发送低电平信号，也就是用该地址线为“0”的地址去读取数据。
|
||||
// 例如，检测第一行时，使A0为0，其余为1；加上选通IC4的高五位地址01101，成为01101***11111110B（A8~A10不起作用，
|
||||
// 可为任意值，故68FEH，69FEH，6AFEH，6BFEH，6CFEH，6DFEH，6EFEH，6FFEH均可）。
|
||||
// 读 6800H 判断是否有按键按下。
|
||||
|
||||
// The method of keyboard detection is to cyclically ask each line to send a low level signal,
|
||||
// that is, to read the data with the address line "0".
|
||||
// For example, when detecting the first line, make A0 0 and the rest 1; plus the high five-bit address 01101 of the strobe IC4,
|
||||
// become 01101***11111110B (A8~A10 does not work,
|
||||
// It can be any value, so 68FEH, 69FEH, 6AFEH, 6BFEH, 6CFEH, 6DFEH, 6EFEH, 6FFEH can be).
|
||||
// Read 6800H to determine if there is a button press.
|
||||
|
||||
// 键盘选通，整个竖列有一个选通的位置被按下，对应值为0。
|
||||
// The keyboard is strobed, and a strobe position is pressed in the entire vertical column, and the corresponding value is 0.
|
||||
|
||||
// 键盘扩展
|
||||
// 加入方向键盘
|
||||
// Keyboard extension
|
||||
|
||||
// left: ctrl M 37 KEY_EX[5]
|
||||
// right: ctrl , 35 KEY_EX[6]
|
||||
// up: ctrl . 33 KEY_EX[4]
|
||||
// down: ctrl space 36 KEY_EX[7]
|
||||
// esc: ctrl - 42 KEY_EX[3]
|
||||
// backspace: ctrl M 37 KEY_EX[8]
|
||||
|
||||
// R-Shift
|
||||
|
||||
|
||||
wire [63:0] KEY_C = EMU_KEY_EN?EMU_KEY:KEY;
|
||||
wire [9:0] KEY_EX_C = EMU_KEY_EN?EMU_KEY_EX:KEY_EX;
|
||||
|
||||
//wire KEY_CTRL_ULRD = (KEY_EX[7:4]==4'b1111);
|
||||
wire KEY_CTRL_ULRD_BRK = (KEY_EX[8:3]==6'b111111);
|
||||
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY_C[61], KEY_C[53], KEY_C[45], KEY_C[37]&KEY_EX_C[5]&KEY_EX_C[8], KEY_C[29], KEY_C[21], KEY_C[13], KEY_C[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY_C[60], KEY_C[52], KEY_C[44], KEY_C[36]&KEY_EX_C[7], KEY_C[28], KEY_C[20], KEY_C[12], KEY_C[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY_C[59], KEY_C[51], KEY_C[43], KEY_C[35]&KEY_EX_C[6], KEY_C[27], KEY_C[19], KEY_C[11], KEY_C[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY_C[58], KEY_C[50], KEY_C[42]&KEY_EX_C[3], KEY_C[34], KEY_C[26], KEY_C[18]&KEY_EX_C[0], KEY_C[10]&KEY_CTRL_ULRD_BRK, KEY_C[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY_C[57], KEY_C[49], KEY_C[41], KEY_C[33]&KEY_EX_C[4], KEY_C[25], KEY_C[17], KEY_C[ 9], KEY_C[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY_C[56], KEY_C[48], KEY_C[40], KEY_C[32], KEY_C[24], KEY_C[16], KEY_C[ 8], KEY_C[ 0]})==8'hff;
|
||||
|
||||
/*
|
||||
wire KEY_DATA_BIT5 = (CPU_A[7:0]|{KEY[61], KEY[53], KEY[45], KEY[37], KEY[29], KEY[21], KEY[13], KEY[ 5]})==8'hff;
|
||||
wire KEY_DATA_BIT4 = (CPU_A[7:0]|{KEY[60], KEY[52], KEY[44], KEY[36], KEY[28], KEY[20], KEY[12], KEY[ 4]})==8'hff;
|
||||
wire KEY_DATA_BIT3 = (CPU_A[7:0]|{KEY[59], KEY[51], KEY[43], KEY[35], KEY[27], KEY[19], KEY[11], KEY[ 3]})==8'hff;
|
||||
wire KEY_DATA_BIT2 = (CPU_A[7:0]|{KEY[58], KEY[50], KEY[42], KEY[34], KEY[26], KEY[18], KEY[10], KEY[ 2]})==8'hff;
|
||||
wire KEY_DATA_BIT1 = (CPU_A[7:0]|{KEY[57], KEY[49], KEY[41], KEY[33], KEY[25], KEY[17], KEY[ 9], KEY[ 1]})==8'hff;
|
||||
wire KEY_DATA_BIT0 = (CPU_A[7:0]|{KEY[56], KEY[48], KEY[40], KEY[32], KEY[24], KEY[16], KEY[ 8], KEY[ 0]})==8'hff;
|
||||
*/
|
||||
|
||||
wire KEY_DATA_BIT7 = 1'b1; // 没有空置，具体用途没有理解
|
||||
//wire KEY_DATA_BIT6 = CASS_IN;
|
||||
wire KEY_DATA_BIT6 = ~CASS_IN;
|
||||
|
||||
assign KEY_DATA = { KEY_DATA_BIT7, KEY_DATA_BIT6, KEY_DATA_BIT5, KEY_DATA_BIT4, KEY_DATA_BIT3, KEY_DATA_BIT2, KEY_DATA_BIT1, KEY_DATA_BIT0 };
|
||||
|
||||
/*
|
||||
assign KEY_DATA = (CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
8'hff;
|
||||
|
||||
assign KEY_DATA =
|
||||
(CPU_A[7]==1'b0) ? KEY[63:56] :
|
||||
(CPU_A[6]==1'b0) ? KEY[55:48] :
|
||||
(CPU_A[5]==1'b0) ? KEY[47:40] :
|
||||
(CPU_A[4]==1'b0) ? KEY[39:32] :
|
||||
(CPU_A[3]==1'b0) ? KEY[31:24] :
|
||||
(CPU_A[2]==1'b0) ? KEY[23:16] :
|
||||
(CPU_A[1]==1'b0) ? KEY[15: 8] :
|
||||
(CPU_A[0]==1'b0) ? KEY[ 7: 0] :
|
||||
8'hff;
|
||||
*/
|
||||
|
||||
|
||||
assign A_KEY_PRESSED = (KEY[63:0] == 64'hFFFFFFFFFFFFFFFF) ? 1'b0:1'b1;
|
||||
|
||||
always @(posedge KB_CLK[3] or negedge SYS_RESET_N)
|
||||
begin
|
||||
if(~SYS_RESET_N)
|
||||
begin
|
||||
KEY <= 64'hFFFFFFFFFFFFFFFF;
|
||||
KEY_EX <= 10'h3FF;
|
||||
KEY_Fxx <= 12'h000;
|
||||
// CAPS_CLK <= 1'b0;
|
||||
RESET_KEY_COUNT <= 17'h1FFFF;
|
||||
|
||||
BOOTROM_BANK <= 0;
|
||||
BOOTROM_EN <= 1'b0;
|
||||
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
//KEY[?] <= CAPS;
|
||||
if(RESET_KEY_COUNT[16]==1'b0)
|
||||
RESET_KEY_COUNT <= RESET_KEY_COUNT+1;
|
||||
|
||||
case(SCAN)
|
||||
8'h07:
|
||||
begin
|
||||
KEY_Fxx[11] <= PRESS; // F12 RESET
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b0;
|
||||
BOOTROM_BANK <= 0;
|
||||
AUTOSTARTROM_EN <= 1'b0;
|
||||
AUTOSTARTROM_BANK <= 0;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h78: KEY_Fxx[10] <= PRESS; // F11
|
||||
8'h09: KEY_Fxx[ 9] <= PRESS; // F10 CASS STOP
|
||||
8'h01: KEY_Fxx[ 8] <= PRESS; // F9 CASS PLAY
|
||||
8'h0A:
|
||||
begin
|
||||
KEY_Fxx[ 7] <= PRESS; // F8 Ctrl or L-Shift BOOT 8
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 39;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 23;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h83:
|
||||
begin
|
||||
KEY_Fxx[ 6] <= PRESS; // F7 Ctrl or L-Shift BOOT 7
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 38;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 22;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0B:
|
||||
begin
|
||||
KEY_Fxx[ 5] <= PRESS; // F6 Ctrl or L-Shift BOOT 6
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 37;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 21;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h03:
|
||||
begin
|
||||
KEY_Fxx[ 4] <= PRESS; // F5 Ctrl or L-Shift BOOT 5
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 36;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 20;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h0C:
|
||||
begin
|
||||
KEY_Fxx[ 3] <= PRESS; // F4 Ctrl or L-Shift BOOT 4
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 35;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 19;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h04:
|
||||
begin
|
||||
KEY_Fxx[ 2] <= PRESS; // F3 Ctrl or L-Shift BOOT 3
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 34;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 18;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h06:
|
||||
begin
|
||||
KEY_Fxx[ 1] <= PRESS; // F2 Ctrl or L-Shift BOOT 2
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 33;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 17;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
8'h05:
|
||||
begin
|
||||
KEY_Fxx[ 0] <= PRESS; // F1 Ctrl or L-Shift BOOT 1
|
||||
if(PRESS && (KEY[18]==PRESS_N))
|
||||
begin
|
||||
BOOTROM_EN <= 1'b1;
|
||||
BOOTROM_BANK <= 32;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
else
|
||||
if(PRESS && (KEY[10]==PRESS_N))
|
||||
begin
|
||||
AUTOSTARTROM_EN <= 1'b1;
|
||||
AUTOSTARTROM_BANK <= 16;
|
||||
RESET_KEY_COUNT <= 17'h0;
|
||||
end
|
||||
end
|
||||
|
||||
8'h16: KEY[28] <= PRESS_N; // 1 !
|
||||
8'h1E: KEY[25] <= PRESS_N; // 2 @
|
||||
8'h26: KEY[27] <= PRESS_N; // 3 #
|
||||
8'h25: KEY[29] <= PRESS_N; // 4 $
|
||||
8'h2E: KEY[24] <= PRESS_N; // 5 %
|
||||
8'h36: KEY[40] <= PRESS_N; // 6 ^
|
||||
8'h3D: KEY[45] <= PRESS_N; // 7 &
|
||||
// 8'h0D: KEY[?] <= PRESS_N; // TAB
|
||||
8'h3E: KEY[43] <= PRESS_N; // 8 *
|
||||
8'h46: KEY[41] <= PRESS_N; // 9 (
|
||||
8'h45: KEY[44] <= PRESS_N; // 0 )
|
||||
8'h4E: KEY[42] <= PRESS_N; // - _
|
||||
// 8'h55: KEY[?] <= PRESS_N; // = +
|
||||
8'h66: KEY_EX[8] <= PRESS_N; // backspace
|
||||
// 8'h0E: KEY[?] <= PRESS_N; // ` ~
|
||||
// 8'h5D: KEY[?] <= PRESS_N; // \ |
|
||||
8'h49: KEY[33] <= PRESS_N; // . >
|
||||
8'h4b: KEY[57] <= PRESS_N; // L
|
||||
8'h44: KEY[49] <= PRESS_N; // O
|
||||
// 8'h11 KEY[?] <= PRESS_N; // line feed (really right ALT (Extended) see below
|
||||
8'h5A: KEY[50] <= PRESS_N; // CR
|
||||
// 8'h54: KEY[?] <= PRESS_N; // [ {
|
||||
// 8'h5B: KEY[?] <= PRESS_N; // ] }
|
||||
8'h52: KEY[58] <= PRESS_N; // ' "
|
||||
8'h1D: KEY[ 1] <= PRESS_N; // W
|
||||
8'h24: KEY[ 3] <= PRESS_N; // E
|
||||
8'h2D: KEY[ 5] <= PRESS_N; // R
|
||||
8'h2C: KEY[ 0] <= PRESS_N; // T
|
||||
8'h35: KEY[48] <= PRESS_N; // Y
|
||||
8'h3C: KEY[53] <= PRESS_N; // U
|
||||
8'h43: KEY[51] <= PRESS_N; // I
|
||||
8'h1B: KEY[ 9] <= PRESS_N; // S
|
||||
8'h23: KEY[11] <= PRESS_N; // D
|
||||
8'h2B: KEY[13] <= PRESS_N; // F
|
||||
8'h34: KEY[ 8] <= PRESS_N; // G
|
||||
8'h33: KEY[56] <= PRESS_N; // H
|
||||
8'h3B: KEY[61] <= PRESS_N; // J
|
||||
8'h42: KEY[59] <= PRESS_N; // K
|
||||
8'h22: KEY[17] <= PRESS_N; // X
|
||||
8'h21: KEY[19] <= PRESS_N; // C
|
||||
8'h2a: KEY[21] <= PRESS_N; // V
|
||||
8'h32: KEY[16] <= PRESS_N; // B
|
||||
8'h31: KEY[32] <= PRESS_N; // N
|
||||
8'h3a: KEY[37] <= PRESS_N; // M
|
||||
8'h41: KEY[35] <= PRESS_N; // , <
|
||||
8'h15: KEY[ 4] <= PRESS_N; // Q
|
||||
8'h1C: KEY[12] <= PRESS_N; // A
|
||||
8'h1A: KEY[20] <= PRESS_N; // Z
|
||||
8'h29: KEY[36] <= PRESS_N; // Space
|
||||
// 8'h4A: KEY[?] <= PRESS_N; // / ?
|
||||
8'h4C: KEY[60] <= PRESS_N; // ; :
|
||||
8'h4D: KEY[52] <= PRESS_N; // P
|
||||
8'h14: KEY[10] <= PRESS_N; // Ctrl either left or right
|
||||
8'h12: KEY[18] <= PRESS_N; // L-Shift
|
||||
8'h59: KEY_EX[0] <= PRESS_N; // R-Shift
|
||||
8'h11:
|
||||
begin
|
||||
if(~EXTENDED)
|
||||
KEY_EX[1] <= PRESS_N; // Repeat really left ALT
|
||||
else
|
||||
KEY_EX[2] <= PRESS_N; // LF really right ALT
|
||||
end
|
||||
8'h76: KEY_EX[3] <= PRESS_N; // Esc
|
||||
8'h75: KEY_EX[4] <= PRESS_N; // up
|
||||
8'h6B: KEY_EX[5] <= PRESS_N; // left
|
||||
8'h74: KEY_EX[6] <= PRESS_N; // right
|
||||
8'h72: KEY_EX[7] <= PRESS_N; // down
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
|
||||
always @ (posedge CLK50MHZ) // 50MHz
|
||||
KB_CLK <= KB_CLK + 1'b1; // 50/32 = 1.5625 MHz
|
||||
|
||||
ps2_keyboard KEYBOARD(
|
||||
.RESET_N(RESET_N),
|
||||
.CLK(KB_CLK[4]),
|
||||
.PS2_CLK(PS2_KBCLK),
|
||||
.PS2_DATA(PS2_KBDAT),
|
||||
.RX_SCAN(SCAN),
|
||||
.RX_PRESSED(PRESS),
|
||||
.RX_EXTENDED(EXTENDED)
|
||||
);
|
||||
|
||||
assign PRESS_N = ~PRESS;
|
||||
|
||||
|
||||
`ifdef CASS_EMU
|
||||
|
||||
wire CASS_BUF_RD;
|
||||
wire [15:0] CASS_BUF_A;
|
||||
wire CASS_BUF_WR;
|
||||
wire [7:0] CASS_BUF_DAT;
|
||||
wire [7:0] CASS_BUF_Q;
|
||||
|
||||
// F9 CASS PLAY
|
||||
// F10 CASS STOP
|
||||
|
||||
EMU_CASS_KEY EMU_CASS_KEY(
|
||||
KEY_Fxx[8],
|
||||
KEY_Fxx[9],
|
||||
// cass emu
|
||||
CASS_BUF_RD,
|
||||
//
|
||||
CASS_BUF_A,
|
||||
CASS_BUF_WR,
|
||||
CASS_BUF_DAT,
|
||||
CASS_BUF_Q,
|
||||
// Control Signals
|
||||
EMU_CASS_EN,
|
||||
EMU_CASS_DAT,
|
||||
|
||||
// key emu
|
||||
EMU_KEY,
|
||||
EMU_KEY_EX,
|
||||
EMU_KEY_EN,
|
||||
/*
|
||||
* UART: 115200 bps, 8N1
|
||||
*/
|
||||
UART_RXD,
|
||||
UART_TXD,
|
||||
|
||||
// System
|
||||
TURBO_SPEED,
|
||||
// Clock: 10MHz
|
||||
CLK10MHZ,
|
||||
RESET_N
|
||||
);
|
||||
|
||||
|
||||
`ifdef CASS_EMU_16K
|
||||
|
||||
cass_ram_16k_altera cass_buf(
|
||||
.address(CASS_BUF_A[13:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_8K
|
||||
|
||||
cass_ram_8k_altera cass_buf(
|
||||
.address(CASS_BUF_A[12:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DI),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_4K
|
||||
|
||||
cass_ram_4k_altera cass_buf(
|
||||
.address(CASS_BUF_A[11:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
`ifdef CASS_EMU_2K
|
||||
|
||||
cass_ram_2k_altera cass_buf(
|
||||
.address(CASS_BUF_A[10:0]),
|
||||
.clock(CLK10MHZ),
|
||||
.data(CASS_BUF_DAT),
|
||||
.wren(CASS_BUF_WR),
|
||||
.q(CASS_BUF_Q)
|
||||
);
|
||||
|
||||
`endif
|
||||
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
assign CASS_OUT = EMU_CASS_EN ? EMU_CASS_DAT : {LATCHED_IO_DATA_WR[2], 1'b0};
|
||||
|
||||
(*keep*)wire trap = (CPU_RD|CPU_WR) && (CPU_A[15:12] == 4'h0);
|
||||
|
||||
@@ -1,70 +0,0 @@
|
||||
module VIDEO_OUT
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
vga_red_data,
|
||||
vga_green_data,
|
||||
vga_blue_data,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
input pixel_clock;
|
||||
input reset;
|
||||
input [7:0] vga_red_data;
|
||||
input [7:0] vga_green_data;
|
||||
input [7:0] vga_blue_data;
|
||||
input h_synch;
|
||||
input v_synch;
|
||||
input blank;
|
||||
|
||||
output VGA_OUT_HSYNC;
|
||||
output VGA_OUT_VSYNC;
|
||||
output [7:0] VGA_OUT_RED;
|
||||
output [7:0] VGA_OUT_GREEN;
|
||||
output [7:0] VGA_OUT_BLUE;
|
||||
|
||||
reg VGA_OUT_HSYNC;
|
||||
reg VGA_OUT_VSYNC;
|
||||
reg [7:0] VGA_OUT_RED;
|
||||
reg [7:0] VGA_OUT_GREEN;
|
||||
reg [7:0] VGA_OUT_BLUE;
|
||||
|
||||
// make the external video connections
|
||||
always @ (posedge pixel_clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
// shut down the video output during reset
|
||||
VGA_OUT_HSYNC <= 1'b1;
|
||||
VGA_OUT_VSYNC <= 1'b1;
|
||||
VGA_OUT_RED <= 8'b0;
|
||||
VGA_OUT_GREEN <= 8'b0;
|
||||
VGA_OUT_BLUE <= 8'b0;
|
||||
end
|
||||
|
||||
else if (blank) begin
|
||||
// output black during the blank signal
|
||||
VGA_OUT_HSYNC <= h_synch;
|
||||
VGA_OUT_VSYNC <= v_synch;
|
||||
VGA_OUT_RED <= 8'b0;
|
||||
VGA_OUT_GREEN <= 8'b0;
|
||||
VGA_OUT_BLUE <= 8'b0;
|
||||
end
|
||||
|
||||
else begin
|
||||
// output color data otherwise
|
||||
VGA_OUT_HSYNC <= h_synch;
|
||||
VGA_OUT_VSYNC <= v_synch;
|
||||
VGA_OUT_RED <= vga_red_data;
|
||||
VGA_OUT_GREEN <= vga_green_data;
|
||||
VGA_OUT_BLUE <= vga_blue_data;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule // VIDEO_OUT
|
||||
@@ -1,35 +0,0 @@
|
||||
# ================================================================================
|
||||
#
|
||||
# Build ID Verilog Module Script
|
||||
# Jeff Wiencrot - 8/1/2011
|
||||
#
|
||||
# Generates a Verilog module that contains a timestamp,
|
||||
# from the current build. These values are available from the build_date, build_time,
|
||||
# physical_address, and host_name output ports of the build_id module in the build_id.v
|
||||
# Verilog source file.
|
||||
#
|
||||
# ================================================================================
|
||||
|
||||
proc generateBuildID_Verilog {} {
|
||||
|
||||
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
|
||||
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
|
||||
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
|
||||
|
||||
# Create a Verilog file for output
|
||||
set outputFileName "rtl/build_id.v"
|
||||
set outputFile [open $outputFileName "w"]
|
||||
|
||||
# Output the Verilog source
|
||||
puts $outputFile "`define BUILD_DATE \"$buildDate\""
|
||||
puts $outputFile "`define BUILD_TIME \"$buildTime\""
|
||||
close $outputFile
|
||||
|
||||
# Send confirmation message to the Messages window
|
||||
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
|
||||
post_message "Date: $buildDate"
|
||||
post_message "Time: $buildTime"
|
||||
}
|
||||
|
||||
# Comment out this line to prevent the process from automatically executing when the file is sourced:
|
||||
generateBuildID_Verilog
|
||||
@@ -1,48 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Delta-Sigma DAC
|
||||
--
|
||||
-- Refer to Xilinx Application Note XAPP154.
|
||||
--
|
||||
-- This DAC requires an external RC low-pass filter:
|
||||
--
|
||||
-- dac_o 0---XXXXX---+---0 analog audio
|
||||
-- 3k3 |
|
||||
-- === 4n7
|
||||
-- |
|
||||
-- GND
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity dac is
|
||||
generic (
|
||||
C_bits : integer := 12
|
||||
);
|
||||
port (
|
||||
clk_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
dac_i : in std_logic_vector(C_bits-1 downto 0);
|
||||
dac_o : out std_logic
|
||||
);
|
||||
end dac;
|
||||
|
||||
architecture rtl of dac is
|
||||
signal sig_in: unsigned(C_bits downto 0);
|
||||
begin
|
||||
seq: process(clk_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
sig_in <= to_unsigned(2**C_bits, sig_in'length);
|
||||
dac_o <= '0';
|
||||
elsif rising_edge(clk_i) then
|
||||
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
|
||||
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
|
||||
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
|
||||
dac_o <= sig_in(C_bits);
|
||||
end if;
|
||||
end process seq;
|
||||
end rtl;
|
||||
@@ -1,58 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity dpram is
|
||||
|
||||
generic (
|
||||
addr_width_g : integer := 8;
|
||||
data_width_g : integer := 8
|
||||
);
|
||||
port (
|
||||
clk_a_i : in std_logic;
|
||||
en_a_i : in std_logic;
|
||||
we_i : in std_logic;
|
||||
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
|
||||
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
|
||||
clk_b_i : in std_logic;
|
||||
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
|
||||
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
|
||||
);
|
||||
|
||||
end dpram;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of dpram is
|
||||
|
||||
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of std_logic_vector(data_width_g-1 downto 0);
|
||||
signal ram_q : ram_t;
|
||||
|
||||
begin
|
||||
|
||||
mem_a: process (clk_a_i)
|
||||
begin
|
||||
if rising_edge(clk_a_i) then
|
||||
if we_i = '1' and en_a_i = '1' then
|
||||
ram_q(to_integer(unsigned(addr_a_i))) <= data_a_i;
|
||||
data_a_o <= data_a_i;
|
||||
else
|
||||
data_a_o <= ram_q(to_integer(unsigned(addr_a_i)));
|
||||
end if;
|
||||
end if;
|
||||
end process mem_a;
|
||||
|
||||
mem_b: process (clk_b_i)
|
||||
begin
|
||||
if rising_edge(clk_b_i) then
|
||||
data_b_o <= ram_q(to_integer(unsigned(addr_b_i)));
|
||||
end if;
|
||||
end process mem_b;
|
||||
|
||||
end rtl;
|
||||
@@ -1,967 +0,0 @@
|
||||
/*****************************************************************************
|
||||
* Floppy
|
||||
******************************************************************************/
|
||||
|
||||
// POLLING after Clock
|
||||
|
||||
// vz dsk Parameter
|
||||
// 154 * 16 * 40 = 98560 = 0x18100
|
||||
// 154 * 16 = 2464 = 0x9A0 = 0x4D0 * 2
|
||||
`define FD_MAX_LEN 17'h18100
|
||||
`define FD_TRACK_LEN 12'h9A0
|
||||
`define FD_TRACK_STEP 8'h4D
|
||||
|
||||
// 40*2 0 --- 78
|
||||
`define FD_MAX_TRACK_NO 8'd78
|
||||
|
||||
|
||||
module FDC_IF (
|
||||
FDC_CLK,
|
||||
RESET_N,
|
||||
SW,
|
||||
DBG,
|
||||
|
||||
FDC_RAM_R,
|
||||
FDC_RAM_W,
|
||||
FDC_RAM_ADDR_R,
|
||||
FDC_RAM_ADDR_W,
|
||||
FDC_RAM_DATA_R,
|
||||
FDC_RAM_DATA_W,
|
||||
|
||||
FDC_IO,
|
||||
FDC_IO_POLL,
|
||||
FDC_IO_DATA,
|
||||
FDC_IO_CT,
|
||||
|
||||
FDC_SIG,
|
||||
FDC_SIG_CLK,
|
||||
|
||||
FDC_CT,
|
||||
FDC_DATA,
|
||||
FDC_POLL,
|
||||
FDC_WP,
|
||||
|
||||
FLOPPY_SECTOR_BYTE,
|
||||
TRACK1_NO,
|
||||
TRACK2_NO,
|
||||
DRIVE1,
|
||||
DRIVE2,
|
||||
MOTOR
|
||||
);
|
||||
|
||||
|
||||
input FDC_CLK;
|
||||
input RESET_N;
|
||||
input [1:0] SW;
|
||||
input [3:0] DBG;
|
||||
|
||||
output [17:0] FDC_RAM_ADDR_R;
|
||||
output [17:0] FDC_RAM_ADDR_W;
|
||||
output reg FDC_RAM_R;
|
||||
output reg FDC_RAM_W;
|
||||
input [7:0] FDC_RAM_DATA_R;
|
||||
output [7:0] FDC_RAM_DATA_W;
|
||||
|
||||
|
||||
input FDC_IO;
|
||||
input FDC_IO_POLL;
|
||||
input FDC_IO_DATA;
|
||||
input FDC_IO_CT;
|
||||
|
||||
output FDC_SIG;
|
||||
output reg FDC_SIG_CLK;
|
||||
|
||||
input [7:0] FDC_CT;
|
||||
|
||||
output [7:0] FDC_DATA;
|
||||
output FDC_POLL;
|
||||
output FDC_WP;
|
||||
|
||||
|
||||
reg [11:0] FLOPPY_BYTE;
|
||||
output reg [7:0] FLOPPY_SECTOR_BYTE; // Count Sector Bytes
|
||||
|
||||
reg [6:0] CLK_CNT;
|
||||
reg [6:0] CLK_CNT_W;
|
||||
|
||||
reg [18:0] SYNC_CNT;
|
||||
reg [7:0] FLOPPY_SECTOR_DELAY; // Delay on Sector End
|
||||
|
||||
|
||||
reg FD_REC1;
|
||||
reg FDC_POLL1;
|
||||
reg FDC_REC_DATA_BIT1;
|
||||
reg FDC_DATA_BIT1;
|
||||
reg [7:0] FDC_DATA1;
|
||||
reg [7:0] LATCHED_FDC_DATA1;
|
||||
reg FDC_DATA_SET1;
|
||||
|
||||
reg FD_REC2;
|
||||
reg FDC_POLL2;
|
||||
reg FDC_REC_DATA_BIT2;
|
||||
reg FDC_DATA_BIT2;
|
||||
reg [7:0] FDC_DATA2;
|
||||
reg [7:0] LATCHED_FDC_DATA2;
|
||||
|
||||
reg [3:0] BIT_CNT_W;
|
||||
reg [2:0] BIT_CNT;
|
||||
|
||||
wire FDC_RAM_DATA_R_BIT;
|
||||
|
||||
|
||||
reg [1:0] STEPPER1;
|
||||
reg [1:0] STEPPER2;
|
||||
output reg [7:0] TRACK1_NO;
|
||||
output reg [7:0] TRACK2_NO;
|
||||
reg [12:0] TRACK1;
|
||||
reg [12:0] TRACK2;
|
||||
(*keep*)wire [13:0] TRACK;
|
||||
wire [12:0] TRACK1_UP;
|
||||
wire [12:0] TRACK1_DOWN;
|
||||
wire [12:0] TRACK2_UP;
|
||||
wire [12:0] TRACK2_DOWN;
|
||||
reg [17:0] FLOPPY_ADDRESS_R;
|
||||
reg [17:0] FLOPPY_ADDRESS_W;
|
||||
//reg [7:0] FLOPPY_WRITE_DATA;
|
||||
|
||||
reg WRITE_WAIT_FIRST_OP;
|
||||
reg WRITE_DATA_BIT_VAL;
|
||||
|
||||
reg [7:0] WRITE_DATA1;
|
||||
reg WRITE_DATA_MODI1;
|
||||
reg [7:0] WRITE_DATA2;
|
||||
reg WRITE_DATA2_MODI;
|
||||
|
||||
|
||||
(*keep*)wire [7:0] FLOPPY_RD_DATA;
|
||||
(*keep*)wire [7:0] FLOPPY_DATA;
|
||||
(*keep*)wire FLOPPY_READ;
|
||||
(*keep*)wire FLOPPY_WRITE;
|
||||
wire FLOPPY_WP_READ;
|
||||
reg PHASE0;
|
||||
reg PHASE0_1;
|
||||
reg PHASE0_2;
|
||||
reg PHASE1;
|
||||
reg PHASE1_1;
|
||||
reg PHASE1_2;
|
||||
reg PHASE2;
|
||||
reg PHASE2_1;
|
||||
reg PHASE2_2;
|
||||
reg PHASE3;
|
||||
reg PHASE3_1;
|
||||
reg PHASE3_2;
|
||||
output reg DRIVE1;
|
||||
output reg DRIVE2;
|
||||
output reg MOTOR;
|
||||
|
||||
reg WRITE_REQUEST_N;
|
||||
reg WRITE_DATA_BIT;
|
||||
|
||||
reg Q6;
|
||||
reg Q7;
|
||||
wire DRIVE1_EN;
|
||||
wire DRIVE2_EN;
|
||||
wire DRIVE1_X;
|
||||
wire DRIVE2_X;
|
||||
wire DRIVE_SWAP;
|
||||
wire DRIVE1_FLOPPY_WP;
|
||||
wire DRIVE2_FLOPPY_WP;
|
||||
|
||||
reg MODIFY_DRIVE1;
|
||||
reg MODIFY_DRIVE2;
|
||||
|
||||
assign FDC_RAM_ADDR_R = FLOPPY_ADDRESS_R;
|
||||
assign FDC_RAM_ADDR_W = FLOPPY_ADDRESS_W;
|
||||
|
||||
|
||||
(*preserve*)reg [7:0] FDC_CNT;
|
||||
(*preserve*)reg [7:0] FDC_CNT_POLL;
|
||||
(*preserve*)reg [7:0] FDC_CNT_DATA;
|
||||
(*preserve*)reg [19:0] FDC_CNT_CT;
|
||||
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
FDC_CNT <= 8'hFF;
|
||||
FDC_CNT_POLL <= 8'hFF;
|
||||
FDC_CNT_DATA <= 8'hFF;
|
||||
FDC_CNT_CT <= 20'hFFFFF;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(FDC_IO)
|
||||
FDC_CNT <= 0;
|
||||
else if(~FDC_CNT[7])
|
||||
FDC_CNT <= FDC_CNT + 1;
|
||||
|
||||
if(FDC_IO_POLL)
|
||||
FDC_CNT_POLL <= 0;
|
||||
else if(~FDC_CNT_POLL[7])
|
||||
FDC_CNT_POLL <= FDC_CNT_POLL + 1;
|
||||
|
||||
if(FDC_IO_DATA)
|
||||
FDC_CNT_DATA <= 0;
|
||||
else if(~FDC_CNT_DATA[7])
|
||||
FDC_CNT_DATA <= FDC_CNT_DATA + 1;
|
||||
|
||||
if(FDC_IO_CT)
|
||||
FDC_CNT_CT <= 0;
|
||||
else if(~FDC_CNT_CT[19])
|
||||
FDC_CNT_CT <= FDC_CNT_CT + 1;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
assign FDC_POLL = (DRIVE1_EN)?FDC_POLL1:
|
||||
(DRIVE2_EN)?FDC_POLL2:
|
||||
1'b0;
|
||||
|
||||
|
||||
assign FDC_DATA = (DRIVE1_EN)?FDC_DATA1:
|
||||
(DRIVE2_EN)?FDC_DATA2:
|
||||
8'hFF;
|
||||
|
||||
|
||||
|
||||
assign FDC_RAM_DATA_R_BIT = (BIT_CNT==3'd7)?FDC_RAM_DATA_R[7]:
|
||||
(BIT_CNT==3'd6)?FDC_RAM_DATA_R[6]:
|
||||
(BIT_CNT==3'd5)?FDC_RAM_DATA_R[5]:
|
||||
(BIT_CNT==3'd4)?FDC_RAM_DATA_R[4]:
|
||||
(BIT_CNT==3'd3)?FDC_RAM_DATA_R[3]:
|
||||
(BIT_CNT==3'd2)?FDC_RAM_DATA_R[2]:
|
||||
(BIT_CNT==3'd1)?FDC_RAM_DATA_R[1]:
|
||||
FDC_RAM_DATA_R[0];
|
||||
|
||||
|
||||
// 读取
|
||||
|
||||
reg LATCHED_FD_REC1;
|
||||
reg LATCHED_FDC_IO_DATA1;
|
||||
reg GET_FDC_POLLING;
|
||||
|
||||
reg [5:0] FDC_POLL1_CNT;
|
||||
|
||||
reg [5:0] GET_FDC_POLL1_CNT;
|
||||
|
||||
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
if(~RESET_N)
|
||||
begin
|
||||
FDC_DATA_BIT1 <= 1'b0;
|
||||
|
||||
LATCHED_FD_REC1 <= 1'b0;
|
||||
LATCHED_FDC_IO_DATA1 <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// 磁道记录信号上沿，翻转 DATA_BIT
|
||||
if({LATCHED_FD_REC1, FD_REC1}==2'b01)
|
||||
begin
|
||||
FDC_DATA_BIT1 <= FDC_POLL1;
|
||||
end
|
||||
|
||||
if(FDC_DATA_SET1)
|
||||
LATCHED_FDC_DATA1 <= {LATCHED_FDC_DATA1[6:0], FDC_DATA_BIT1};
|
||||
|
||||
// 读取DATA信号上沿
|
||||
if({LATCHED_FDC_IO_DATA1, FDC_IO_DATA}==2'b01)
|
||||
begin
|
||||
FDC_DATA1 <= LATCHED_FDC_DATA1;
|
||||
end
|
||||
|
||||
LATCHED_FD_REC1 <= FD_REC1;
|
||||
LATCHED_FDC_IO_DATA1 <= FDC_IO_DATA;
|
||||
end
|
||||
|
||||
////////////////////////////////////////
|
||||
// 物理软驱模拟
|
||||
////////////////////////////////////////
|
||||
|
||||
//WRITE_REQUEST_N
|
||||
(*preserve*)reg [9:0] WRITE_DATA_CNT;
|
||||
|
||||
assign FDC_RAM_DATA_W = WRITE_DATA1;
|
||||
|
||||
// 对写入操作计数
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
WRITE_DATA_CNT <= 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if( (~FDC_CT[6]) && (FDC_CT[5]==LATCHED_FDC_CT[5]) )
|
||||
begin
|
||||
if(~WRITE_DATA_CNT[9])
|
||||
WRITE_DATA_CNT <= WRITE_DATA_CNT+1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
WRITE_DATA_CNT <= 0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// 模拟磁道信号
|
||||
|
||||
// 等待第1个写入数据变化
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
if(~RESET_N)
|
||||
begin
|
||||
WRITE_WAIT_FIRST_OP <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if( LATCHED_FDC_CT[6]!=FDC_CT[6] )
|
||||
begin
|
||||
// 信号下拉，开始写入，并等待第1个写入数据变化。
|
||||
WRITE_WAIT_FIRST_OP <= ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b10);
|
||||
end
|
||||
else
|
||||
begin
|
||||
// 找到第1个写入数据变化
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
|
||||
WRITE_WAIT_FIRST_OP <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// 判断是否有写入数据产生
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
if(~RESET_N)
|
||||
begin
|
||||
WRITE_DATA_MODI1 <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// 写入信号变化
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
|
||||
begin
|
||||
WRITE_DATA_MODI1 <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(FDC_RAM_W)
|
||||
WRITE_DATA_MODI1 <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// 判断写入的值
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
if(~RESET_N)
|
||||
begin
|
||||
WRITE_DATA_BIT_VAL <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// 写入信号变化
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) )
|
||||
begin
|
||||
// 9'h01B 9'h056 9'h072
|
||||
if(WRITE_DATA_CNT==10'h01B)
|
||||
begin
|
||||
WRITE_DATA_BIT_VAL <= 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
WRITE_DATA_BIT_VAL <= 1'b0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// 模拟磁盘数据位
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
SYNC_CNT <= 19'b0;
|
||||
|
||||
BIT_CNT <= 3'd0;
|
||||
|
||||
FDC_RAM_R <= 1'b0;
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
FDC_DATA_SET1 <= 1'b0;
|
||||
|
||||
FDC_POLL1 <= 1'b0;
|
||||
FDC_POLL2 <= 1'b0;
|
||||
|
||||
FLOPPY_BYTE <= 12'h000;
|
||||
FLOPPY_SECTOR_BYTE <= 8'h00;
|
||||
FLOPPY_SECTOR_DELAY <= 8'h00;
|
||||
FLOPPY_ADDRESS_R <= 18'b0;
|
||||
FLOPPY_ADDRESS_W <= 18'b0;
|
||||
|
||||
WRITE_DATA1 <= 8'b0;
|
||||
|
||||
FD_REC1 <= 1'b0;
|
||||
CLK_CNT <= 7'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
begin
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT[9] )
|
||||
begin
|
||||
// INIT 磁道空白区，约1/10圈空白。
|
||||
// 找到第1个时钟位
|
||||
BIT_CNT <= 3'd7;
|
||||
|
||||
// 下一个需要读取的位置
|
||||
FLOPPY_BYTE <= 12'h001;
|
||||
FLOPPY_SECTOR_BYTE <= 8'h00;
|
||||
|
||||
FLOPPY_ADDRESS_R <= {TRACK, 4'b0};
|
||||
SYNC_CNT <= 19'b0;
|
||||
FDC_RAM_R <= 1'b1;
|
||||
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
FDC_DATA_SET1 <= 1'b0;
|
||||
|
||||
FD_REC1 <= 1'b1;
|
||||
FDC_POLL1 <= 1'b0;
|
||||
FDC_POLL2 <= 1'b0;
|
||||
CLK_CNT <= 7'h03;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && (FDC_CT[5]!=LATCHED_FDC_CT[5]) && WRITE_DATA_CNT==10'h02F )
|
||||
begin
|
||||
// 格式化时，数据区之前无空白。数据存盘时，写入数据区留有50个左右的时钟周期空白。
|
||||
// 写入扇区定位，写入扇区前有约0x28个时钟周期的空白。
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
FDC_DATA_SET1 <= 1'b0;
|
||||
|
||||
FD_REC1 <= 1'b1;
|
||||
FDC_POLL1 <= 1'b0;
|
||||
FDC_POLL2 <= 1'b0;
|
||||
CLK_CNT <= 7'h03;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(CLK_CNT)
|
||||
7'h00: // 同步信号 324 * 8 * 0x70 = 290304
|
||||
begin
|
||||
FD_REC1 <= 1'b0;
|
||||
SYNC_CNT <= SYNC_CNT+1;
|
||||
|
||||
FDC_RAM_R <= 1'b0;
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
if(SYNC_CNT[18])
|
||||
//if(SYNC_CNT[10])
|
||||
begin
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
end
|
||||
|
||||
7'h01:
|
||||
begin
|
||||
FDC_RAM_R <= 1'b0;
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
// 如果是写入，等待时钟沿的变化
|
||||
if( ({LATCHED_FDC_CT[6],FDC_CT[6]}==2'b00) && ({LATCHED_FDC_CT[5],FDC_CT[5]}==2'b01) )
|
||||
begin
|
||||
CLK_CNT <= CLK_CNT;
|
||||
end
|
||||
else
|
||||
begin
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// CLOCK DOMAIN
|
||||
7'h02:
|
||||
begin
|
||||
BIT_CNT <= BIT_CNT-1;
|
||||
|
||||
// 读取
|
||||
if(BIT_CNT==3'd0)
|
||||
begin
|
||||
begin
|
||||
FLOPPY_BYTE <= FLOPPY_BYTE + 1'b1;
|
||||
|
||||
FLOPPY_ADDRESS_R <= {TRACK, 4'b0} + {6'b000000, FLOPPY_BYTE};
|
||||
end
|
||||
|
||||
FDC_RAM_R <= 1'b1;
|
||||
end
|
||||
|
||||
FD_REC1 <= 1'b1;
|
||||
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
|
||||
// POOLING
|
||||
// 从读取POLLING成功（值为1），到读取DATA中间间隔了0x43 个时钟周期。
|
||||
7'h03:
|
||||
begin
|
||||
FDC_RAM_R <= 1'b0;
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
FDC_POLL1 <= 1'b1;
|
||||
FDC_POLL2 <= 1'b1;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h06: // 1us
|
||||
begin
|
||||
FD_REC1 <= 1'b0;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
// DATA DOMAIN
|
||||
7'h1E:
|
||||
begin
|
||||
FD_REC1 <= FDC_RAM_DATA_R_BIT;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h1F:
|
||||
begin
|
||||
FDC_DATA_SET1 <= 1'b1;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h20:
|
||||
begin
|
||||
FDC_DATA_SET1 <= 1'b0;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h22:
|
||||
begin
|
||||
FD_REC1 <= 1'b0;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h25:
|
||||
begin
|
||||
FDC_POLL1 <= 1'b0;
|
||||
FDC_POLL2 <= 1'b0;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
// 扇区结束延时
|
||||
7'h70:
|
||||
begin
|
||||
// 写入
|
||||
WRITE_DATA1 <= {WRITE_DATA1[6:0],WRITE_DATA_BIT_VAL};
|
||||
|
||||
if(BIT_CNT==3'd0)
|
||||
begin
|
||||
FLOPPY_ADDRESS_W <= FLOPPY_ADDRESS_R;
|
||||
FDC_RAM_W <= WRITE_DATA_MODI1;
|
||||
end
|
||||
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
7'h71:
|
||||
begin
|
||||
// 写入结束
|
||||
FDC_RAM_W <= 1'b0;
|
||||
|
||||
FDC_SIG_CLK <= WRITE_DATA_MODI1;
|
||||
|
||||
// 扇区结束时的延时
|
||||
if(BIT_CNT==3'd0 && FLOPPY_SECTOR_BYTE==8'h99)
|
||||
begin
|
||||
FLOPPY_SECTOR_DELAY <= 8'hA5;
|
||||
end
|
||||
else
|
||||
begin
|
||||
FLOPPY_SECTOR_DELAY <= 8'h00;
|
||||
end
|
||||
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
|
||||
// 扇区结束时的延时
|
||||
7'h72:
|
||||
begin
|
||||
FDC_SIG_CLK <= 1'b0;
|
||||
|
||||
// 扇区结束时的延时
|
||||
if(FLOPPY_SECTOR_DELAY==8'h00)
|
||||
begin
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
FLOPPY_SECTOR_DELAY <= FLOPPY_SECTOR_DELAY-1;
|
||||
end
|
||||
end
|
||||
|
||||
7'h73:
|
||||
begin
|
||||
if(BIT_CNT==3'd0)
|
||||
begin
|
||||
if(FLOPPY_BYTE==`FD_TRACK_LEN||FLOPPY_SECTOR_BYTE==8'h99)
|
||||
begin
|
||||
FLOPPY_SECTOR_BYTE <= 8'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
FLOPPY_SECTOR_BYTE <= FLOPPY_SECTOR_BYTE+1;
|
||||
end
|
||||
end
|
||||
|
||||
if(BIT_CNT==3'd0 && FLOPPY_BYTE==`FD_TRACK_LEN)
|
||||
begin
|
||||
FLOPPY_BYTE <= 12'h000;
|
||||
//FLOPPY_SECTOR_BYTE <= 8'h00;
|
||||
|
||||
FLOPPY_ADDRESS_R <= {TRACK, 4'b0};
|
||||
SYNC_CNT <= 19'b0;
|
||||
|
||||
CLK_CNT <= 7'h00;
|
||||
end
|
||||
else
|
||||
begin
|
||||
CLK_CNT <= 7'h01;
|
||||
end
|
||||
end
|
||||
|
||||
default:
|
||||
begin
|
||||
FDC_RAM_R <= 1'b0;
|
||||
FDC_RAM_W <= 1'b0;
|
||||
CLK_CNT <= CLK_CNT + 1;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
PHASE0 <= 1'b0;
|
||||
PHASE1 <= 1'b0;
|
||||
PHASE2 <= 1'b0;
|
||||
PHASE3 <= 1'b0;
|
||||
MOTOR <= 1'b0;
|
||||
DRIVE1 <= 1'b0;
|
||||
DRIVE2 <= 1'b0;
|
||||
WRITE_REQUEST_N <= 1'b1;
|
||||
WRITE_DATA_BIT <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
PHASE0 <= FDC_CT[0];
|
||||
PHASE1 <= FDC_CT[1];
|
||||
PHASE2 <= FDC_CT[2];
|
||||
PHASE3 <= FDC_CT[3];
|
||||
DRIVE1 <= FDC_CT[4];
|
||||
DRIVE2 <= FDC_CT[7];
|
||||
MOTOR <= (FDC_CT[4])|(FDC_CT[7]);
|
||||
WRITE_REQUEST_N <= FDC_CT[6];
|
||||
WRITE_DATA_BIT <= FDC_CT[5];
|
||||
end
|
||||
end
|
||||
|
||||
//assign DRIVE1_X = DRIVE1 & MOTOR;
|
||||
//assign DRIVE2_X = !DRIVE1 & MOTOR;
|
||||
|
||||
assign DRIVE1_X = DRIVE1 & MOTOR;
|
||||
assign DRIVE2_X = DRIVE2 & MOTOR;
|
||||
|
||||
assign DRIVE1_FLOPPY_WP = ~SW[0];
|
||||
assign DRIVE2_FLOPPY_WP = ~SW[1];
|
||||
|
||||
assign FDC_WP = DRIVE1?DRIVE1_FLOPPY_WP:
|
||||
DRIVE2?DRIVE2_FLOPPY_WP:
|
||||
1'b1;
|
||||
|
||||
|
||||
assign DRIVE1_EN = (DRIVE1) & MOTOR;
|
||||
assign DRIVE2_EN = (DRIVE2) & MOTOR;
|
||||
|
||||
|
||||
assign TRACK = (DRIVE1_EN) ? {1'b0,TRACK1}:
|
||||
(DRIVE2_EN) ? {1'b1,TRACK2}:
|
||||
14'b0;
|
||||
|
||||
assign TRACK1_UP = TRACK1 + `FD_TRACK_STEP;
|
||||
assign TRACK1_DOWN = TRACK1 - `FD_TRACK_STEP;
|
||||
assign TRACK2_UP = TRACK2 + `FD_TRACK_STEP;
|
||||
assign TRACK2_DOWN = TRACK2 - `FD_TRACK_STEP;
|
||||
|
||||
|
||||
//assign FLOPPY_ADDRESS_R = {TRACK, 4'b0} + {5'b00000, FLOPPY_BYTE};
|
||||
|
||||
|
||||
//always @ (posedge PH_2)
|
||||
always @(negedge FDC_CLK)
|
||||
begin
|
||||
PHASE0_1 <= PHASE0;
|
||||
PHASE0_2 <= PHASE0_1; // Delay 2 clock cycles
|
||||
PHASE1_1 <= PHASE1;
|
||||
PHASE1_2 <= PHASE1_1; // Delay 2 clock cycles
|
||||
PHASE2_1 <= PHASE2;
|
||||
PHASE2_2 <= PHASE2_1; // Delay 2 clock cycles
|
||||
PHASE3_1 <= PHASE3;
|
||||
PHASE3_2 <= PHASE3_1; // Delay 2 clock cycles
|
||||
end
|
||||
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
STEPPER1 <= 2'b00;
|
||||
STEPPER2 <= 2'b00;
|
||||
TRACK1 <= 13'd0;
|
||||
TRACK2 <= 13'd0;
|
||||
|
||||
TRACK1_NO <= 8'd0;
|
||||
TRACK2_NO <= 8'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
// if(DRIVE1^DRIVE_SWAP)
|
||||
if(DRIVE1)
|
||||
begin
|
||||
case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2})
|
||||
4'b1000:
|
||||
begin
|
||||
if(STEPPER1 == 2'b11)
|
||||
begin
|
||||
//if(TRACK1 != `FD_MAX_LEN)
|
||||
if(TRACK1_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK1 <= TRACK1_UP;
|
||||
TRACK1_NO <= TRACK1_NO+1;
|
||||
STEPPER1 <= 2'b00;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER1 == 2'b01)
|
||||
begin
|
||||
//if(TRACK1 != 17'h0)
|
||||
if(TRACK1_NO != 8'd0)
|
||||
begin
|
||||
TRACK1 <= TRACK1_DOWN;
|
||||
TRACK1_NO <= TRACK1_NO-1;
|
||||
STEPPER1 <= 2'b00;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0100:
|
||||
begin
|
||||
if(STEPPER1 == 2'b00)
|
||||
begin
|
||||
//if(TRACK1 != `FD_MAX_LEN)
|
||||
if(TRACK1_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK1 <= TRACK1_UP;
|
||||
TRACK1_NO <= TRACK1_NO+1;
|
||||
STEPPER1 <= 2'b01;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER1 == 2'b10)
|
||||
begin
|
||||
//if(TRACK1 != 17'h0)
|
||||
if(TRACK1_NO != 8'd0)
|
||||
begin
|
||||
TRACK1 <= TRACK1_DOWN;
|
||||
TRACK1_NO <= TRACK1_NO-1;
|
||||
STEPPER1 <= 2'b01;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0010:
|
||||
begin
|
||||
if(STEPPER1 == 2'b01)
|
||||
begin
|
||||
//if(TRACK1 != `FD_MAX_LEN)
|
||||
if(TRACK1_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK1 <= TRACK1_UP;
|
||||
TRACK1_NO <= TRACK1_NO+1;
|
||||
STEPPER1 <= 2'b10;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER1 == 2'b11)
|
||||
begin
|
||||
//if(TRACK1 != 17'h0)
|
||||
if(TRACK1_NO != 8'd0)
|
||||
begin
|
||||
TRACK1 <= TRACK1_DOWN;
|
||||
TRACK1_NO <= TRACK1_NO-1;
|
||||
STEPPER1 <= 2'b10;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0001:
|
||||
begin
|
||||
if(STEPPER1 == 2'b10)
|
||||
begin
|
||||
//if(TRACK1 != `FD_MAX_LEN)
|
||||
if(TRACK1_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK1 <= TRACK1_UP;
|
||||
TRACK1_NO <= TRACK1_NO+1;
|
||||
STEPPER1 <= 2'b11;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER1 == 2'b00)
|
||||
begin
|
||||
//if(TRACK1 != 17'h0)
|
||||
if(TRACK1_NO != 8'd0)
|
||||
begin
|
||||
TRACK1 <= TRACK1_DOWN;
|
||||
TRACK1_NO <= TRACK1_NO-1;
|
||||
STEPPER1 <= 2'b11;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
else
|
||||
|
||||
begin
|
||||
case ({PHASE0_2, PHASE1_2, PHASE2_2, PHASE3_2})
|
||||
4'b1000:
|
||||
begin
|
||||
if(STEPPER2 == 2'b11)
|
||||
begin
|
||||
//if(TRACK2 != `FD_MAX_LEN)
|
||||
if(TRACK2_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK2 <= TRACK2_UP;
|
||||
TRACK2_NO <= TRACK2_NO+1;
|
||||
STEPPER2 <= 2'b00;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER2 == 2'b01)
|
||||
begin
|
||||
//if(TRACK2 != 17'h0)
|
||||
if(TRACK2_NO != 8'd0)
|
||||
begin
|
||||
TRACK2 <= TRACK2_DOWN;
|
||||
TRACK2_NO <= TRACK2_NO-1;
|
||||
STEPPER2 <= 2'b00;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0100:
|
||||
begin
|
||||
if(STEPPER2 == 2'b00)
|
||||
begin
|
||||
//if(TRACK2 != `FD_MAX_LEN)
|
||||
if(TRACK2_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK2 <= TRACK2_UP;
|
||||
TRACK2_NO <= TRACK2_NO+1;
|
||||
STEPPER2 <= 2'b01;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER2 == 2'b10)
|
||||
begin
|
||||
//if(TRACK2 != 17'h0)
|
||||
if(TRACK2_NO != 8'd0)
|
||||
begin
|
||||
TRACK2 <= TRACK2_DOWN;
|
||||
TRACK2_NO <= TRACK2_NO-1;
|
||||
STEPPER2 <= 2'b01;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0010:
|
||||
begin
|
||||
if(STEPPER2 == 2'b01)
|
||||
begin
|
||||
//if(TRACK2 != `FD_MAX_LEN)
|
||||
if(TRACK2_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK2 <= TRACK2_UP;
|
||||
TRACK2_NO <= TRACK2_NO+1;
|
||||
STEPPER2 <= 2'b10;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER2 == 2'b11)
|
||||
begin
|
||||
//if(TRACK2 != 17'h0)
|
||||
if(TRACK2_NO != 8'd0)
|
||||
begin
|
||||
TRACK2 <= TRACK2_DOWN;
|
||||
TRACK2_NO <= TRACK2_NO-1;
|
||||
STEPPER2 <= 2'b10;
|
||||
end
|
||||
end
|
||||
end
|
||||
4'b0001:
|
||||
begin
|
||||
if(STEPPER2 == 2'b10)
|
||||
begin
|
||||
//if(TRACK2 != `FD_MAX_LEN)
|
||||
if(TRACK2_NO != `FD_MAX_TRACK_NO)
|
||||
begin
|
||||
TRACK2 <= TRACK2_UP;
|
||||
TRACK2_NO <= TRACK2_NO+1;
|
||||
STEPPER2 <= 2'b11;
|
||||
end
|
||||
end
|
||||
else
|
||||
if(STEPPER2 == 2'b00)
|
||||
begin
|
||||
//if(TRACK2 != 17'h0)
|
||||
if(TRACK2_NO != 8'd0)
|
||||
begin
|
||||
TRACK2 <= TRACK2_DOWN;
|
||||
TRACK2_NO <= TRACK2_NO-1;
|
||||
STEPPER2 <= 2'b11;
|
||||
end
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
|
||||
reg [19:0] LATCHED_FDC_CNT_CT;
|
||||
reg [7:0] LATCHED_FDC_CT;
|
||||
|
||||
|
||||
always @(posedge FDC_CLK or negedge RESET_N)
|
||||
begin
|
||||
if(~RESET_N)
|
||||
begin
|
||||
LATCHED_FDC_CT <= 8'hFF;
|
||||
//FDC_SIG_CLK <= 1'b0;
|
||||
LATCHED_FDC_CNT_CT <= 20'hFFFFF;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LATCHED_FDC_CT <= FDC_CT;
|
||||
LATCHED_FDC_CNT_CT <= FDC_CNT_CT;
|
||||
//FDC_SIG_CLK <= (LATCHED_FDC_CT!=FDC_CT);
|
||||
end
|
||||
end
|
||||
|
||||
assign FDC_SIG = (FDC_CNT[7]|FDC_CNT_POLL[7]|FDC_CNT_DATA[7]|FDC_CNT_CT[19]|(LATCHED_FDC_CNT_CT==0));
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -1,199 +0,0 @@
|
||||
// LASER310 VZ200
|
||||
// mc6847
|
||||
|
||||
module MC6847_VGA(
|
||||
PIX_CLK,
|
||||
RESET_N,
|
||||
|
||||
RD,
|
||||
DD,
|
||||
DA,
|
||||
|
||||
AG,
|
||||
AS,
|
||||
EXT,
|
||||
INV,
|
||||
GM,
|
||||
CSS,
|
||||
|
||||
// vga
|
||||
blank,
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
input PIX_CLK;
|
||||
input RESET_N;
|
||||
|
||||
output wire RD;
|
||||
output wire [12:0] DA; // 8KB
|
||||
input [7:0] DD;
|
||||
input AG;
|
||||
input AS;
|
||||
input EXT;
|
||||
input INV;
|
||||
input CSS;
|
||||
input [2:0] GM;
|
||||
output wire blank;
|
||||
output wire VGA_OUT_HSYNC;
|
||||
output wire VGA_OUT_VSYNC;
|
||||
output wire [7:0] VGA_OUT_RED;
|
||||
output wire [7:0] VGA_OUT_GREEN;
|
||||
output wire [7:0] VGA_OUT_BLUE;
|
||||
|
||||
|
||||
reg LATCHED_AG;
|
||||
reg LATCHED_AS;
|
||||
reg LATCHED_EXT;
|
||||
reg LATCHED_INV;
|
||||
reg [2:0] LATCHED_GM;
|
||||
reg LATCHED_CSS;
|
||||
|
||||
wire pixel_clock; // generated from SYSTEM CLOCK
|
||||
wire reset; // reset asserted when DCMs are NOT LOCKED
|
||||
|
||||
wire [7:0] vga_red; // red video data
|
||||
wire [7:0] vga_green; // green video data
|
||||
wire [7:0] vga_blue; // blue video data
|
||||
|
||||
// internal video timing signals
|
||||
wire h_synch; // horizontal synch for VGA connector
|
||||
wire v_synch; // vertical synch for VGA connector
|
||||
//wire blank; // composite blanking
|
||||
wire [10:0] pixel_count; // bit mapped pixel position within the line
|
||||
wire [9:0] line_count; // bit mapped line number in a frame lines within the frame
|
||||
|
||||
wire show_border;
|
||||
|
||||
// text
|
||||
wire [3:0] subchar_pixel; // pixel position within the character
|
||||
wire [4:0] subchar_line; // identifies the line number within a character block
|
||||
wire [6:0] char_column; // character number on the current line
|
||||
wire [6:0] char_line; // line number on the screen
|
||||
|
||||
// graph
|
||||
wire [8:0] graph_pixel; // pixel number on the current line
|
||||
wire [9:0] graph_line_2x; // line number on the screen
|
||||
wire [9:0] graph_line_3x; // line number on the screen
|
||||
|
||||
/*
|
||||
wire [11:0] ROM_ADDRESS;
|
||||
wire [7:0] ROM_DATA;
|
||||
*/
|
||||
|
||||
assign reset = ~RESET_N;
|
||||
assign pixel_clock = PIX_CLK;
|
||||
|
||||
//assign vga_red = 8'hff;
|
||||
//assign vga_green = 8'h7f;
|
||||
//assign vga_blue = 8'h7f;
|
||||
|
||||
// Character generator
|
||||
/*
|
||||
char_rom_4k_altera char_rom(
|
||||
.address(ROM_ADDRESS),
|
||||
.clock(pixel_clock),
|
||||
.q(ROM_DATA)
|
||||
);
|
||||
*/
|
||||
|
||||
// 为了防止闪屏，再垂直回扫信号产生时，锁存模式信号。
|
||||
|
||||
always @ (posedge v_synch or negedge RESET_N)
|
||||
begin
|
||||
if(!RESET_N)
|
||||
begin
|
||||
LATCHED_AG <= 1'b0;
|
||||
LATCHED_AS <= 1'b0;
|
||||
LATCHED_EXT <= 1'b0;
|
||||
LATCHED_INV <= 1'b0;
|
||||
LATCHED_GM <= 3'b0;
|
||||
LATCHED_CSS <= 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
LATCHED_AG <= AG;
|
||||
LATCHED_AS <= AS;
|
||||
LATCHED_EXT <= EXT;
|
||||
LATCHED_INV <= INV;
|
||||
LATCHED_GM <= GM;
|
||||
LATCHED_CSS <= CSS;
|
||||
end
|
||||
end
|
||||
|
||||
// instantiate the character generator
|
||||
PIXEL_DISPLAY PIXEL_DISPLAY(
|
||||
.pixel_clock(pixel_clock),
|
||||
.reset(reset),
|
||||
.show_border(show_border),
|
||||
// mode
|
||||
.ag(LATCHED_AG),
|
||||
.gm(LATCHED_GM),
|
||||
.css(LATCHED_CSS),
|
||||
// text
|
||||
.char_column(char_column),
|
||||
.char_line(char_line),
|
||||
.subchar_line(subchar_line),
|
||||
.subchar_pixel(subchar_pixel),
|
||||
// graph
|
||||
.graph_pixel(graph_pixel),
|
||||
.graph_line_2x(graph_line_2x),
|
||||
.graph_line_3x(graph_line_3x),
|
||||
// vram
|
||||
.vram_rd_enable(RD),
|
||||
.vram_addr(DA),
|
||||
.vram_data(DD),
|
||||
// vga
|
||||
.vga_red(vga_red),
|
||||
.vga_green(vga_green),
|
||||
.vga_blue(vga_blue)
|
||||
);
|
||||
|
||||
// instantiate the video timing generator
|
||||
SVGA_TIMING_GENERATION SVGA_TIMING_GENERATION
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
pixel_count,
|
||||
line_count,
|
||||
|
||||
show_border,
|
||||
|
||||
// text
|
||||
subchar_pixel,
|
||||
subchar_line,
|
||||
char_column,
|
||||
char_line,
|
||||
|
||||
// graph
|
||||
graph_pixel,
|
||||
graph_line_2x,
|
||||
graph_line_3x
|
||||
);
|
||||
|
||||
// instantiate the video output mux
|
||||
VIDEO_OUT VIDEO_OUT
|
||||
(
|
||||
pixel_clock,
|
||||
reset,
|
||||
vga_red,
|
||||
vga_green,
|
||||
vga_blue,
|
||||
h_synch,
|
||||
v_synch,
|
||||
blank,
|
||||
|
||||
VGA_OUT_HSYNC,
|
||||
VGA_OUT_VSYNC,
|
||||
VGA_OUT_RED,
|
||||
VGA_OUT_GREEN,
|
||||
VGA_OUT_BLUE
|
||||
);
|
||||
|
||||
endmodule
|
||||
@@ -1,4 +0,0 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
|
||||
@@ -1,451 +0,0 @@
|
||||
-- megafunction wizard: %ALTPLL%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: altpll
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: pll.vhd
|
||||
-- Megafunction Name(s):
|
||||
-- altpll
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
-- altera_mf
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY pll IS
|
||||
PORT
|
||||
(
|
||||
areset : IN STD_LOGIC := '0';
|
||||
inclk0 : IN STD_LOGIC := '0';
|
||||
c0 : OUT STD_LOGIC ;
|
||||
c1 : OUT STD_LOGIC ;
|
||||
c2 : OUT STD_LOGIC ;
|
||||
c3 : OUT STD_LOGIC
|
||||
);
|
||||
END pll;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF pll IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
SIGNAL sub_wire1 : STD_LOGIC ;
|
||||
SIGNAL sub_wire2 : STD_LOGIC ;
|
||||
SIGNAL sub_wire3 : STD_LOGIC ;
|
||||
SIGNAL sub_wire4 : STD_LOGIC ;
|
||||
SIGNAL sub_wire5 : STD_LOGIC ;
|
||||
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
|
||||
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altpll
|
||||
GENERIC (
|
||||
bandwidth_type : STRING;
|
||||
clk0_divide_by : NATURAL;
|
||||
clk0_duty_cycle : NATURAL;
|
||||
clk0_multiply_by : NATURAL;
|
||||
clk0_phase_shift : STRING;
|
||||
clk1_divide_by : NATURAL;
|
||||
clk1_duty_cycle : NATURAL;
|
||||
clk1_multiply_by : NATURAL;
|
||||
clk1_phase_shift : STRING;
|
||||
clk2_divide_by : NATURAL;
|
||||
clk2_duty_cycle : NATURAL;
|
||||
clk2_multiply_by : NATURAL;
|
||||
clk2_phase_shift : STRING;
|
||||
clk3_divide_by : NATURAL;
|
||||
clk3_duty_cycle : NATURAL;
|
||||
clk3_multiply_by : NATURAL;
|
||||
clk3_phase_shift : STRING;
|
||||
compensate_clock : STRING;
|
||||
inclk0_input_frequency : NATURAL;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
operation_mode : STRING;
|
||||
pll_type : STRING;
|
||||
port_activeclock : STRING;
|
||||
port_areset : STRING;
|
||||
port_clkbad0 : STRING;
|
||||
port_clkbad1 : STRING;
|
||||
port_clkloss : STRING;
|
||||
port_clkswitch : STRING;
|
||||
port_configupdate : STRING;
|
||||
port_fbin : STRING;
|
||||
port_inclk0 : STRING;
|
||||
port_inclk1 : STRING;
|
||||
port_locked : STRING;
|
||||
port_pfdena : STRING;
|
||||
port_phasecounterselect : STRING;
|
||||
port_phasedone : STRING;
|
||||
port_phasestep : STRING;
|
||||
port_phaseupdown : STRING;
|
||||
port_pllena : STRING;
|
||||
port_scanaclr : STRING;
|
||||
port_scanclk : STRING;
|
||||
port_scanclkena : STRING;
|
||||
port_scandata : STRING;
|
||||
port_scandataout : STRING;
|
||||
port_scandone : STRING;
|
||||
port_scanread : STRING;
|
||||
port_scanwrite : STRING;
|
||||
port_clk0 : STRING;
|
||||
port_clk1 : STRING;
|
||||
port_clk2 : STRING;
|
||||
port_clk3 : STRING;
|
||||
port_clk4 : STRING;
|
||||
port_clk5 : STRING;
|
||||
port_clkena0 : STRING;
|
||||
port_clkena1 : STRING;
|
||||
port_clkena2 : STRING;
|
||||
port_clkena3 : STRING;
|
||||
port_clkena4 : STRING;
|
||||
port_clkena5 : STRING;
|
||||
port_extclk0 : STRING;
|
||||
port_extclk1 : STRING;
|
||||
port_extclk2 : STRING;
|
||||
port_extclk3 : STRING;
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
areset : IN STD_LOGIC ;
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
sub_wire7_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire2 <= sub_wire0(3);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
c3 <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
sub_wire5 <= inclk0;
|
||||
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
|
||||
|
||||
altpll_component : altpll
|
||||
GENERIC MAP (
|
||||
bandwidth_type => "AUTO",
|
||||
clk0_divide_by => 27,
|
||||
clk0_duty_cycle => 50,
|
||||
clk0_multiply_by => 50,
|
||||
clk0_phase_shift => "0",
|
||||
clk1_divide_by => 27,
|
||||
clk1_duty_cycle => 50,
|
||||
clk1_multiply_by => 25,
|
||||
clk1_phase_shift => "0",
|
||||
clk2_divide_by => 27,
|
||||
clk2_duty_cycle => 50,
|
||||
clk2_multiply_by => 10,
|
||||
clk2_phase_shift => "0",
|
||||
clk3_divide_by => 108,
|
||||
clk3_duty_cycle => 50,
|
||||
clk3_multiply_by => 25,
|
||||
clk3_phase_shift => "0",
|
||||
compensate_clock => "CLK0",
|
||||
inclk0_input_frequency => 37037,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "CBX_MODULE_PREFIX=pll",
|
||||
lpm_type => "altpll",
|
||||
operation_mode => "NORMAL",
|
||||
pll_type => "AUTO",
|
||||
port_activeclock => "PORT_UNUSED",
|
||||
port_areset => "PORT_USED",
|
||||
port_clkbad0 => "PORT_UNUSED",
|
||||
port_clkbad1 => "PORT_UNUSED",
|
||||
port_clkloss => "PORT_UNUSED",
|
||||
port_clkswitch => "PORT_UNUSED",
|
||||
port_configupdate => "PORT_UNUSED",
|
||||
port_fbin => "PORT_UNUSED",
|
||||
port_inclk0 => "PORT_USED",
|
||||
port_inclk1 => "PORT_UNUSED",
|
||||
port_locked => "PORT_UNUSED",
|
||||
port_pfdena => "PORT_UNUSED",
|
||||
port_phasecounterselect => "PORT_UNUSED",
|
||||
port_phasedone => "PORT_UNUSED",
|
||||
port_phasestep => "PORT_UNUSED",
|
||||
port_phaseupdown => "PORT_UNUSED",
|
||||
port_pllena => "PORT_UNUSED",
|
||||
port_scanaclr => "PORT_UNUSED",
|
||||
port_scanclk => "PORT_UNUSED",
|
||||
port_scanclkena => "PORT_UNUSED",
|
||||
port_scandata => "PORT_UNUSED",
|
||||
port_scandataout => "PORT_UNUSED",
|
||||
port_scandone => "PORT_UNUSED",
|
||||
port_scanread => "PORT_UNUSED",
|
||||
port_scanwrite => "PORT_UNUSED",
|
||||
port_clk0 => "PORT_USED",
|
||||
port_clk1 => "PORT_USED",
|
||||
port_clk2 => "PORT_USED",
|
||||
port_clk3 => "PORT_USED",
|
||||
port_clk4 => "PORT_UNUSED",
|
||||
port_clk5 => "PORT_UNUSED",
|
||||
port_clkena0 => "PORT_UNUSED",
|
||||
port_clkena1 => "PORT_UNUSED",
|
||||
port_clkena2 => "PORT_UNUSED",
|
||||
port_clkena3 => "PORT_UNUSED",
|
||||
port_clkena4 => "PORT_UNUSED",
|
||||
port_clkena5 => "PORT_UNUSED",
|
||||
port_extclk0 => "PORT_UNUSED",
|
||||
port_extclk1 => "PORT_UNUSED",
|
||||
port_extclk2 => "PORT_UNUSED",
|
||||
port_extclk3 => "PORT_UNUSED",
|
||||
width_clock => 5
|
||||
)
|
||||
PORT MAP (
|
||||
areset => areset,
|
||||
inclk => sub_wire6,
|
||||
clk => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
|
||||
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
|
||||
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "27"
|
||||
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "108"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "10.000000"
|
||||
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "6.250000"
|
||||
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
|
||||
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
|
||||
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
|
||||
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
|
||||
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
|
||||
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "50"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "10"
|
||||
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "25"
|
||||
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "10.00000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "6.25000000"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
|
||||
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
|
||||
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
|
||||
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
|
||||
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
|
||||
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
|
||||
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
|
||||
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
|
||||
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
|
||||
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
|
||||
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
|
||||
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "10"
|
||||
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "108"
|
||||
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
|
||||
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "25"
|
||||
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
|
||||
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
|
||||
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
|
||||
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
|
||||
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
|
||||
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
|
||||
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
|
||||
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
|
||||
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
|
||||
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
|
||||
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
|
||||
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
||||
@@ -1,59 +0,0 @@
|
||||
module RESET_DE(
|
||||
CLK, // 50MHz
|
||||
SYS_RESET_N,
|
||||
RESET_N, // 50MHz/32/65536
|
||||
RESET_AHEAD_N // 提前恢复，可以接 FLASH_RESET_N
|
||||
);
|
||||
|
||||
|
||||
input CLK;
|
||||
input SYS_RESET_N;
|
||||
output RESET_N;
|
||||
output RESET_AHEAD_N;
|
||||
|
||||
|
||||
wire RESET_N;
|
||||
wire RESET_AHEAD_N;
|
||||
|
||||
reg [5:0] CLK_CNT;
|
||||
reg [16:0] RESET_COUNT;
|
||||
|
||||
wire RESET_COUNT_CLK;
|
||||
wire RESET_DE_N;
|
||||
wire RESET_AHEAD_DE_N;
|
||||
|
||||
assign RESET_COUNT_CLK = CLK_CNT[5];
|
||||
|
||||
assign RESET_DE_N = RESET_COUNT[16]!=1'b0;
|
||||
assign RESET_N = SYS_RESET_N && RESET_DE_N;
|
||||
|
||||
assign RESET_AHEAD_DE_N = RESET_COUNT[16:15]!=2'b00;
|
||||
assign RESET_AHEAD_N = SYS_RESET_N && RESET_AHEAD_DE_N;
|
||||
|
||||
`ifdef SIMULATE
|
||||
initial
|
||||
begin
|
||||
CLK_CNT = 6'b0;
|
||||
end
|
||||
`endif
|
||||
|
||||
// 50MHz/32 = 1.5625MHz
|
||||
always @ (posedge CLK)
|
||||
CLK_CNT <= CLK_CNT+1;
|
||||
|
||||
// 50MHz/32/65536 = 23.84HZ
|
||||
always @ (posedge RESET_COUNT_CLK or negedge SYS_RESET_N)
|
||||
begin
|
||||
if(~SYS_RESET_N)
|
||||
begin
|
||||
RESET_COUNT <= 17'h00000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if(RESET_COUNT!=17'h10000)
|
||||
RESET_COUNT <= RESET_COUNT+1;
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@@ -1,122 +0,0 @@
|
||||
DEPTH = 115;
|
||||
WIDTH = 8;
|
||||
ADDRESS_RADIX = HEX;
|
||||
DATA_RADIX = HEX;
|
||||
CONTENT
|
||||
BEGIN
|
||||
0000:AA;
|
||||
0001:55;
|
||||
0002:E7;
|
||||
0003:18;
|
||||
0004:AF;
|
||||
0005:2A;
|
||||
0006:00;
|
||||
0007:C0;
|
||||
0008:11;
|
||||
0009:00;
|
||||
000A:80;
|
||||
000B:ED;
|
||||
000C:52;
|
||||
000D:30;
|
||||
000E:63;
|
||||
000F:3A;
|
||||
0010:02;
|
||||
0011:C0;
|
||||
0012:FE;
|
||||
0013:56;
|
||||
0014:20;
|
||||
0015:18;
|
||||
0016:3A;
|
||||
0017:03;
|
||||
0018:C0;
|
||||
0019:FE;
|
||||
001A:5A;
|
||||
001B:20;
|
||||
001C:55;
|
||||
001D:3A;
|
||||
001E:04;
|
||||
001F:C0;
|
||||
0020:FE;
|
||||
0021:46;
|
||||
0022:20;
|
||||
0023:4E;
|
||||
0024:3A;
|
||||
0025:05;
|
||||
0026:C0;
|
||||
0027:FE;
|
||||
0028:20;
|
||||
0029:20;
|
||||
002A:47;
|
||||
002B:C3;
|
||||
002C:B7;
|
||||
002D:17;
|
||||
002E:FE;
|
||||
002F:20;
|
||||
0030:20;
|
||||
0031:40;
|
||||
0032:3A;
|
||||
0033:03;
|
||||
0034:C0;
|
||||
0035:FE;
|
||||
0036:20;
|
||||
0037:20;
|
||||
0038:39;
|
||||
0039:3A;
|
||||
003A:04;
|
||||
003B:C0;
|
||||
003C:FE;
|
||||
003D:00;
|
||||
003E:20;
|
||||
003F:32;
|
||||
0040:3A;
|
||||
0041:05;
|
||||
0042:C0;
|
||||
0043:FE;
|
||||
0044:00;
|
||||
0045:20;
|
||||
0046:2B;
|
||||
0047:3A;
|
||||
0048:17;
|
||||
0049:C0;
|
||||
004A:FE;
|
||||
004B:F0;
|
||||
004C:28;
|
||||
004D:07;
|
||||
004E:3A;
|
||||
004F:17;
|
||||
0050:C0;
|
||||
0051:FE;
|
||||
0052:F1;
|
||||
0053:20;
|
||||
0054:1D;
|
||||
0055:AF;
|
||||
0056:2A;
|
||||
0057:00;
|
||||
0058:C0;
|
||||
0059:11;
|
||||
005A:18;
|
||||
005B:00;
|
||||
005C:ED;
|
||||
005D:52;
|
||||
005E:44;
|
||||
005F:4D;
|
||||
0060:21;
|
||||
0061:1A;
|
||||
0062:C0;
|
||||
0063:ED;
|
||||
0064:5B;
|
||||
0065:18;
|
||||
0066:C0;
|
||||
0067:ED;
|
||||
0068:B0;
|
||||
0069:AF;
|
||||
006A:3E;
|
||||
006B:00;
|
||||
006C:D3;
|
||||
006D:70;
|
||||
006E:2A;
|
||||
006F:18;
|
||||
0070:C0;
|
||||
0071:E9;
|
||||
0072:76;
|
||||
END;
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,340 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 2, June 1991
|
||||
|
||||
Copyright (C) 1989, 1991 Free Software Foundation, Inc.
|
||||
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The licenses for most software are designed to take away your
|
||||
freedom to share and change it. By contrast, the GNU General Public
|
||||
License is intended to guarantee your freedom to share and change free
|
||||
software--to make sure the software is free for all its users. This
|
||||
General Public License applies to most of the Free Software
|
||||
Foundation's software and to any other program whose authors commit to
|
||||
using it. (Some other Free Software Foundation software is covered by
|
||||
the GNU Library General Public License instead.) You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
this service if you wish), that you receive source code or can get it
|
||||
if you want it, that you can change the software or use pieces of it
|
||||
in new free programs; and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to make restrictions that forbid
|
||||
anyone to deny you these rights or to ask you to surrender the rights.
|
||||
These restrictions translate to certain responsibilities for you if you
|
||||
distribute copies of the software, or if you modify it.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must give the recipients all the rights that
|
||||
you have. You must make sure that they, too, receive or can get the
|
||||
source code. And you must show them these terms so they know their
|
||||
rights.
|
||||
|
||||
We protect your rights with two steps: (1) copyright the software, and
|
||||
(2) offer you this license which gives you legal permission to copy,
|
||||
distribute and/or modify the software.
|
||||
|
||||
Also, for each author's protection and ours, we want to make certain
|
||||
that everyone understands that there is no warranty for this free
|
||||
software. If the software is modified by someone else and passed on, we
|
||||
want its recipients to know that what they have is not the original, so
|
||||
that any problems introduced by others will not reflect on the original
|
||||
authors' reputations.
|
||||
|
||||
Finally, any free program is threatened constantly by software
|
||||
patents. We wish to avoid the danger that redistributors of a free
|
||||
program will individually obtain patent licenses, in effect making the
|
||||
program proprietary. To prevent this, we have made it clear that any
|
||||
patent must be licensed for everyone's free use or not licensed at all.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
|
||||
|
||||
0. This License applies to any program or other work which contains
|
||||
a notice placed by the copyright holder saying it may be distributed
|
||||
under the terms of this General Public License. The "Program", below,
|
||||
refers to any such program or work, and a "work based on the Program"
|
||||
means either the Program or any derivative work under copyright law:
|
||||
that is to say, a work containing the Program or a portion of it,
|
||||
either verbatim or with modifications and/or translated into another
|
||||
language. (Hereinafter, translation is included without limitation in
|
||||
the term "modification".) Each licensee is addressed as "you".
|
||||
|
||||
Activities other than copying, distribution and modification are not
|
||||
covered by this License; they are outside its scope. The act of
|
||||
running the Program is not restricted, and the output from the Program
|
||||
is covered only if its contents constitute a work based on the
|
||||
Program (independent of having been made by running the Program).
|
||||
Whether that is true depends on what the Program does.
|
||||
|
||||
1. You may copy and distribute verbatim copies of the Program's
|
||||
source code as you receive it, in any medium, provided that you
|
||||
conspicuously and appropriately publish on each copy an appropriate
|
||||
copyright notice and disclaimer of warranty; keep intact all the
|
||||
notices that refer to this License and to the absence of any warranty;
|
||||
and give any other recipients of the Program a copy of this License
|
||||
along with the Program.
|
||||
|
||||
You may charge a fee for the physical act of transferring a copy, and
|
||||
you may at your option offer warranty protection in exchange for a fee.
|
||||
|
||||
2. You may modify your copy or copies of the Program or any portion
|
||||
of it, thus forming a work based on the Program, and copy and
|
||||
distribute such modifications or work under the terms of Section 1
|
||||
above, provided that you also meet all of these conditions:
|
||||
|
||||
a) You must cause the modified files to carry prominent notices
|
||||
stating that you changed the files and the date of any change.
|
||||
|
||||
b) You must cause any work that you distribute or publish, that in
|
||||
whole or in part contains or is derived from the Program or any
|
||||
part thereof, to be licensed as a whole at no charge to all third
|
||||
parties under the terms of this License.
|
||||
|
||||
c) If the modified program normally reads commands interactively
|
||||
when run, you must cause it, when started running for such
|
||||
interactive use in the most ordinary way, to print or display an
|
||||
announcement including an appropriate copyright notice and a
|
||||
notice that there is no warranty (or else, saying that you provide
|
||||
a warranty) and that users may redistribute the program under
|
||||
these conditions, and telling the user how to view a copy of this
|
||||
License. (Exception: if the Program itself is interactive but
|
||||
does not normally print such an announcement, your work based on
|
||||
the Program is not required to print an announcement.)
|
||||
|
||||
These requirements apply to the modified work as a whole. If
|
||||
identifiable sections of that work are not derived from the Program,
|
||||
and can be reasonably considered independent and separate works in
|
||||
themselves, then this License, and its terms, do not apply to those
|
||||
sections when you distribute them as separate works. But when you
|
||||
distribute the same sections as part of a whole which is a work based
|
||||
on the Program, the distribution of the whole must be on the terms of
|
||||
this License, whose permissions for other licensees extend to the
|
||||
entire whole, and thus to each and every part regardless of who wrote it.
|
||||
|
||||
Thus, it is not the intent of this section to claim rights or contest
|
||||
your rights to work written entirely by you; rather, the intent is to
|
||||
exercise the right to control the distribution of derivative or
|
||||
collective works based on the Program.
|
||||
|
||||
In addition, mere aggregation of another work not based on the Program
|
||||
with the Program (or with a work based on the Program) on a volume of
|
||||
a storage or distribution medium does not bring the other work under
|
||||
the scope of this License.
|
||||
|
||||
3. You may copy and distribute the Program (or a work based on it,
|
||||
under Section 2) in object code or executable form under the terms of
|
||||
Sections 1 and 2 above provided that you also do one of the following:
|
||||
|
||||
a) Accompany it with the complete corresponding machine-readable
|
||||
source code, which must be distributed under the terms of Sections
|
||||
1 and 2 above on a medium customarily used for software interchange; or,
|
||||
|
||||
b) Accompany it with a written offer, valid for at least three
|
||||
years, to give any third party, for a charge no more than your
|
||||
cost of physically performing source distribution, a complete
|
||||
machine-readable copy of the corresponding source code, to be
|
||||
distributed under the terms of Sections 1 and 2 above on a medium
|
||||
customarily used for software interchange; or,
|
||||
|
||||
c) Accompany it with the information you received as to the offer
|
||||
to distribute corresponding source code. (This alternative is
|
||||
allowed only for noncommercial distribution and only if you
|
||||
received the program in object code or executable form with such
|
||||
an offer, in accord with Subsection b above.)
|
||||
|
||||
The source code for a work means the preferred form of the work for
|
||||
making modifications to it. For an executable work, complete source
|
||||
code means all the source code for all modules it contains, plus any
|
||||
associated interface definition files, plus the scripts used to
|
||||
control compilation and installation of the executable. However, as a
|
||||
special exception, the source code distributed need not include
|
||||
anything that is normally distributed (in either source or binary
|
||||
form) with the major components (compiler, kernel, and so on) of the
|
||||
operating system on which the executable runs, unless that component
|
||||
itself accompanies the executable.
|
||||
|
||||
If distribution of executable or object code is made by offering
|
||||
access to copy from a designated place, then offering equivalent
|
||||
access to copy the source code from the same place counts as
|
||||
distribution of the source code, even though third parties are not
|
||||
compelled to copy the source along with the object code.
|
||||
|
||||
4. You may not copy, modify, sublicense, or distribute the Program
|
||||
except as expressly provided under this License. Any attempt
|
||||
otherwise to copy, modify, sublicense or distribute the Program is
|
||||
void, and will automatically terminate your rights under this License.
|
||||
However, parties who have received copies, or rights, from you under
|
||||
this License will not have their licenses terminated so long as such
|
||||
parties remain in full compliance.
|
||||
|
||||
5. You are not required to accept this License, since you have not
|
||||
signed it. However, nothing else grants you permission to modify or
|
||||
distribute the Program or its derivative works. These actions are
|
||||
prohibited by law if you do not accept this License. Therefore, by
|
||||
modifying or distributing the Program (or any work based on the
|
||||
Program), you indicate your acceptance of this License to do so, and
|
||||
all its terms and conditions for copying, distributing or modifying
|
||||
the Program or works based on it.
|
||||
|
||||
6. Each time you redistribute the Program (or any work based on the
|
||||
Program), the recipient automatically receives a license from the
|
||||
original licensor to copy, distribute or modify the Program subject to
|
||||
these terms and conditions. You may not impose any further
|
||||
restrictions on the recipients' exercise of the rights granted herein.
|
||||
You are not responsible for enforcing compliance by third parties to
|
||||
this License.
|
||||
|
||||
7. If, as a consequence of a court judgment or allegation of patent
|
||||
infringement or for any other reason (not limited to patent issues),
|
||||
conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot
|
||||
distribute so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you
|
||||
may not distribute the Program at all. For example, if a patent
|
||||
license would not permit royalty-free redistribution of the Program by
|
||||
all those who receive copies directly or indirectly through you, then
|
||||
the only way you could satisfy both it and this License would be to
|
||||
refrain entirely from distribution of the Program.
|
||||
|
||||
If any portion of this section is held invalid or unenforceable under
|
||||
any particular circumstance, the balance of the section is intended to
|
||||
apply and the section as a whole is intended to apply in other
|
||||
circumstances.
|
||||
|
||||
It is not the purpose of this section to induce you to infringe any
|
||||
patents or other property right claims or to contest validity of any
|
||||
such claims; this section has the sole purpose of protecting the
|
||||
integrity of the free software distribution system, which is
|
||||
implemented by public license practices. Many people have made
|
||||
generous contributions to the wide range of software distributed
|
||||
through that system in reliance on consistent application of that
|
||||
system; it is up to the author/donor to decide if he or she is willing
|
||||
to distribute software through any other system and a licensee cannot
|
||||
impose that choice.
|
||||
|
||||
This section is intended to make thoroughly clear what is believed to
|
||||
be a consequence of the rest of this License.
|
||||
|
||||
8. If the distribution and/or use of the Program is restricted in
|
||||
certain countries either by patents or by copyrighted interfaces, the
|
||||
original copyright holder who places the Program under this License
|
||||
may add an explicit geographical distribution limitation excluding
|
||||
those countries, so that distribution is permitted only in or among
|
||||
countries not thus excluded. In such case, this License incorporates
|
||||
the limitation as if written in the body of this License.
|
||||
|
||||
9. The Free Software Foundation may publish revised and/or new versions
|
||||
of the General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the Program
|
||||
specifies a version number of this License which applies to it and "any
|
||||
later version", you have the option of following the terms and conditions
|
||||
either of that version or of any later version published by the Free
|
||||
Software Foundation. If the Program does not specify a version number of
|
||||
this License, you may choose any version ever published by the Free Software
|
||||
Foundation.
|
||||
|
||||
10. If you wish to incorporate parts of the Program into other free
|
||||
programs whose distribution conditions are different, write to the author
|
||||
to ask for permission. For software which is copyrighted by the Free
|
||||
Software Foundation, write to the Free Software Foundation; we sometimes
|
||||
make exceptions for this. Our decision will be guided by the two goals
|
||||
of preserving the free status of all derivatives of our free software and
|
||||
of promoting the sharing and reuse of software generally.
|
||||
|
||||
NO WARRANTY
|
||||
|
||||
11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
|
||||
FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
|
||||
OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
|
||||
PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
|
||||
OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
|
||||
TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
|
||||
PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
|
||||
REPAIR OR CORRECTION.
|
||||
|
||||
12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
|
||||
REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
|
||||
INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
|
||||
OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
|
||||
TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
|
||||
YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
|
||||
PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGES.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
convey the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) 19yy <name of author>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program is interactive, make it output a short notice like this
|
||||
when it starts in an interactive mode:
|
||||
|
||||
Gnomovision version 69, Copyright (C) 19yy name of author
|
||||
Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, the commands you use may
|
||||
be called something other than `show w' and `show c'; they could even be
|
||||
mouse-clicks or menu items--whatever suits your program.
|
||||
|
||||
You should also get your employer (if you work as a programmer) or your
|
||||
school, if any, to sign a "copyright disclaimer" for the program, if
|
||||
necessary. Here is a sample; alter the names:
|
||||
|
||||
Yoyodyne, Inc., hereby disclaims all copyright interest in the program
|
||||
`Gnomovision' (which makes passes at compilers) written by James Hacker.
|
||||
|
||||
<signature of Ty Coon>, 1 April 1989
|
||||
Ty Coon, President of Vice
|
||||
|
||||
This General Public License does not permit incorporating your program into
|
||||
proprietary programs. If your program is a subroutine library, you may
|
||||
consider it more useful to permit linking proprietary applications with the
|
||||
library. If this is what you want to do, use the GNU Library General
|
||||
Public License instead of this License.
|
||||
@@ -1,143 +0,0 @@
|
||||
|
||||
An SN76489AN Compatible Implementation in VHDL
|
||||
==============================================
|
||||
Version: $Date: 2006/06/18 19:28:40 $
|
||||
|
||||
Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
See the file COPYING.
|
||||
|
||||
|
||||
Integration
|
||||
-----------
|
||||
|
||||
The sn76489 design exhibits all interface signals as the original chip. It
|
||||
only differs in the audio data output which is provided as an 8 bit signed
|
||||
vector instead of an analog output pin.
|
||||
|
||||
generic (
|
||||
clock_div_16_g : integer := 1
|
||||
-- Set to '1' when operating the design in SN76489 mode. The primary clock
|
||||
-- input is divided by 16 in this variant. The data sheet mentions the
|
||||
-- SN76494 which contains a divide-by-2 clock input stage. Set the generic
|
||||
-- to '0' to enable this mode.
|
||||
);
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
-- Primary clock input
|
||||
-- Drive with the target frequency or any integer multiple of it.
|
||||
|
||||
clock_en_i : in std_logic;
|
||||
-- Clock enable
|
||||
-- A '1' on this input qualifies a valid rising edge on clock_i. A '0'
|
||||
-- disables the next rising clock edge, effectivley halting the design
|
||||
-- until the next enabled rising clock edge.
|
||||
-- Can be used to run the core at lower frequencies than applied on
|
||||
-- clock_i.
|
||||
|
||||
res_n_i : in std_logic;
|
||||
-- Asynchronous low active reset input.
|
||||
-- Sets all sequential elements to a known state.
|
||||
|
||||
ce_n_i : in std_logic;
|
||||
-- Chip enable, low active.
|
||||
|
||||
we_n_i : in std_logic;
|
||||
-- Write enable, low active.
|
||||
|
||||
ready_o : out std_logic;
|
||||
-- Ready indication to microprocessor.
|
||||
|
||||
d_i : in std_logic_vector(0 to 7);
|
||||
-- Data input
|
||||
-- MSB 0 ... 7 LSB
|
||||
|
||||
aout_o : out signed(0 to 7)
|
||||
-- Audio output, signed vector
|
||||
-- MSB/SIGN 0 ... 7 LSB
|
||||
);
|
||||
|
||||
|
||||
Both 8 bit vector ports are defined (0 to 7) which declares bit 0 to be the
|
||||
MSB and bit 7 to be the LSB. This has been implemented according to TI's data
|
||||
sheet, thus all register/data format figures apply 1:1 for this design.
|
||||
Many systems will flip the system data bus bit wise before it is connected to
|
||||
this PSG. This is simply achieved with the following VHDL construct:
|
||||
|
||||
signal data_s : std_logic_vector(7 downto 0);
|
||||
|
||||
...
|
||||
d_i => data_s,
|
||||
...
|
||||
|
||||
d_i and data_s will be assigned from left to right, resulting in the expected
|
||||
bit assignment:
|
||||
|
||||
d_i data_s
|
||||
0 7
|
||||
1 6
|
||||
...
|
||||
6 1
|
||||
7 0
|
||||
|
||||
|
||||
As this design is fully synchronous, care has to be taken when the design
|
||||
replaces an SN76489 in asynchronous mode. No problems are expected when
|
||||
interfacing the code to other synchronous components.
|
||||
|
||||
|
||||
Design Hierarchy
|
||||
----------------
|
||||
|
||||
sn76489_top
|
||||
|
|
||||
+-- sn76489_latch_ctrl
|
||||
|
|
||||
+-- sn76489_clock_div
|
||||
|
|
||||
+-- sn76489_tone
|
||||
| |
|
||||
| \-- sn76489_attentuator
|
||||
|
|
||||
+-- sn76489_tone
|
||||
| |
|
||||
| \-- sn76489_attentuator
|
||||
|
|
||||
+-- sn76489_tone
|
||||
| |
|
||||
| \-- sn76489_attentuator
|
||||
|
|
||||
\-- sn76489_noise
|
||||
|
|
||||
\-- sn76489_attentuator
|
||||
|
||||
Resulting compilation sequence:
|
||||
|
||||
sn76489_comp_pack-p.vhd
|
||||
sn76489_top.vhd
|
||||
sn76489_latch_ctrl.vhd
|
||||
sn76489_latch_ctrl-c.vhd
|
||||
sn76489_clock_div.vhd
|
||||
sn76489_clock_div-c.vhd
|
||||
sn76489_attenuator.vhd
|
||||
sn76489_attenuator-c.vhd
|
||||
sn76489_tone.vhd
|
||||
sn76489_tone-c.vhd
|
||||
sn76489_noise.vhd
|
||||
sn76489_noise-c.vhd
|
||||
sn76489_top-c.vhd
|
||||
|
||||
Skip the files containing VHDL configurations when analyzing the code for
|
||||
synthesis.
|
||||
|
||||
|
||||
References
|
||||
----------
|
||||
|
||||
* TI Data sheet SN76489.pdf
|
||||
ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
|
||||
|
||||
* John Kortink's article on the SN76489:
|
||||
http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
|
||||
|
||||
* Maxim's "SN76489 notes" in
|
||||
http://www.smspower.org/maxim/docs/SN76489.txt
|
||||
@@ -1,114 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_attenuator.vhd,v 1.7 2006/02/27 20:30:10 arnim Exp $
|
||||
--
|
||||
-- Attenuator Module
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity sn76489_attenuator is
|
||||
|
||||
port (
|
||||
attenuation_i : in std_logic_vector(0 to 3);
|
||||
factor_i : in signed(0 to 1);
|
||||
product_o : out signed(0 to 7)
|
||||
);
|
||||
|
||||
end sn76489_attenuator;
|
||||
|
||||
|
||||
architecture rtl of sn76489_attenuator is
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process attenuate
|
||||
--
|
||||
-- Purpose:
|
||||
-- Determine the attenuation and generate the resulting product.
|
||||
--
|
||||
-- The maximum attenuation value is 31 which corresponds to volume off.
|
||||
-- As described in the data sheet, the maximum "playing" attenuation is
|
||||
-- 28 = 16 + 8 + 4
|
||||
--
|
||||
-- The table for the volume constants is derived from the following
|
||||
-- formula (each step is 2dB voltage):
|
||||
-- v(0) = 31
|
||||
-- v(n+1) = v(n) * 0.79432823
|
||||
--
|
||||
attenuate: process (attenuation_i,
|
||||
factor_i)
|
||||
|
||||
type volume_t is array (natural range 0 to 15) of natural;
|
||||
constant volume_c : volume_t :=
|
||||
(31, 25, 20, 16, 12, 10, 8, 6, 5, 4, 3, 2, 2, 2, 1, 0);
|
||||
|
||||
variable attenuation_v : unsigned(attenuation_i'range);
|
||||
variable volume_v : signed(product_o'range);
|
||||
|
||||
begin
|
||||
|
||||
attenuation_v := unsigned(attenuation_i);
|
||||
|
||||
-- volume look-up table
|
||||
volume_v := to_signed(volume_c(to_integer(attenuation_v)),
|
||||
product_o'length);
|
||||
|
||||
-- this replaces a multiplier and consumes a bit fewer
|
||||
-- resources
|
||||
case to_integer(factor_i) is
|
||||
when +1 =>
|
||||
product_o <= volume_v;
|
||||
when -1 =>
|
||||
product_o <= -volume_v;
|
||||
when others =>
|
||||
product_o <= (others => '0');
|
||||
end case;
|
||||
|
||||
end process attenuate;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
end rtl;
|
||||
@@ -1,134 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_clock_div.vhd,v 1.4 2005/10/10 21:51:27 arnim Exp $
|
||||
--
|
||||
-- Clock Divider Circuit
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity sn76489_clock_div is
|
||||
|
||||
generic (
|
||||
clock_div_16_g : integer := 1
|
||||
);
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
clock_en_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
clk_en_o : out boolean
|
||||
);
|
||||
|
||||
end sn76489_clock_div;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of sn76489_clock_div is
|
||||
|
||||
signal cnt_s,
|
||||
cnt_q : unsigned(3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process seq
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the sequential counter element.
|
||||
--
|
||||
seq: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
cnt_q <= (others => '0');
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
cnt_q <= cnt_s;
|
||||
end if;
|
||||
end process seq;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process comb
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the combinational counter logic.
|
||||
--
|
||||
comb: process (clock_en_i,
|
||||
cnt_q)
|
||||
begin
|
||||
-- default assignments
|
||||
cnt_s <= cnt_q;
|
||||
clk_en_o <= false;
|
||||
|
||||
if clock_en_i = '1' then
|
||||
|
||||
if cnt_q = 0 then
|
||||
clk_en_o <= true;
|
||||
|
||||
if clock_div_16_g = 1 then
|
||||
cnt_s <= to_unsigned(15, cnt_q'length);
|
||||
elsif clock_div_16_g = 0 then
|
||||
cnt_s <= to_unsigned( 1, cnt_q'length);
|
||||
else
|
||||
-- pragma translate_off
|
||||
assert false
|
||||
report "Generic clock_div_16_g must be either 0 or 1."
|
||||
severity failure;
|
||||
-- pragma translate_on
|
||||
end if;
|
||||
|
||||
else
|
||||
cnt_s <= cnt_q - 1;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end process comb;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
end rtl;
|
||||
@@ -1,138 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_latch_ctrl.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
|
||||
--
|
||||
-- Latch Control Unit
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
|
||||
entity sn76489_latch_ctrl is
|
||||
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
clk_en_i : in boolean;
|
||||
res_n_i : in std_logic;
|
||||
ce_n_i : in std_logic;
|
||||
we_n_i : in std_logic;
|
||||
d_i : in std_logic_vector(0 to 7);
|
||||
ready_o : out std_logic;
|
||||
tone1_we_o : out boolean;
|
||||
tone2_we_o : out boolean;
|
||||
tone3_we_o : out boolean;
|
||||
noise_we_o : out boolean;
|
||||
r2_o : out std_logic
|
||||
);
|
||||
|
||||
end sn76489_latch_ctrl;
|
||||
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
architecture rtl of sn76489_latch_ctrl is
|
||||
|
||||
signal reg_q : std_logic_vector(0 to 2);
|
||||
signal we_q : boolean;
|
||||
signal ready_q : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process seq
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the sequential elements.
|
||||
--
|
||||
seq: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
reg_q <= (others => '0');
|
||||
we_q <= false;
|
||||
ready_q <= '0';
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
-- READY Flag Output ----------------------------------------------------
|
||||
if ready_q = '0' and we_q then
|
||||
if clk_en_i then
|
||||
-- assert READY when write access happened
|
||||
ready_q <= '1';
|
||||
end if;
|
||||
elsif ce_n_i = '1' then
|
||||
-- deassert READY when access has finished
|
||||
ready_q <= '0';
|
||||
end if;
|
||||
|
||||
-- Register Selection ---------------------------------------------------
|
||||
if ce_n_i = '0' and we_n_i = '0' then
|
||||
if clk_en_i then
|
||||
if d_i(0) = '1' then
|
||||
reg_q <= d_i(1 to 3);
|
||||
end if;
|
||||
we_q <= true;
|
||||
end if;
|
||||
else
|
||||
we_q <= false;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end process seq;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Output mapping
|
||||
-----------------------------------------------------------------------------
|
||||
tone1_we_o <= reg_q(0 to 1) = "00" and we_q;
|
||||
tone2_we_o <= reg_q(0 to 1) = "01" and we_q;
|
||||
tone3_we_o <= reg_q(0 to 1) = "10" and we_q;
|
||||
noise_we_o <= reg_q(0 to 1) = "11" and we_q;
|
||||
|
||||
r2_o <= reg_q(2);
|
||||
|
||||
ready_o <= ready_q
|
||||
when ce_n_i = '0' else
|
||||
'1';
|
||||
|
||||
end rtl;
|
||||
@@ -1,278 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_noise.vhd,v 1.6 2006/02/27 20:30:10 arnim Exp $
|
||||
--
|
||||
-- Noise Generator
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity sn76489_noise is
|
||||
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
clk_en_i : in boolean;
|
||||
res_n_i : in std_logic;
|
||||
we_i : in boolean;
|
||||
d_i : in std_logic_vector(0 to 7);
|
||||
r2_i : in std_logic;
|
||||
tone3_ff_i : in std_logic;
|
||||
noise_o : out signed(0 to 7)
|
||||
);
|
||||
|
||||
end sn76489_noise;
|
||||
|
||||
architecture rtl of sn76489_noise is
|
||||
|
||||
signal nf_q : std_logic_vector(0 to 1);
|
||||
signal fb_q : std_logic;
|
||||
signal a_q : std_logic_vector(0 to 3);
|
||||
signal freq_cnt_q : unsigned(0 to 6);
|
||||
signal freq_ff_q : std_logic;
|
||||
|
||||
signal shift_source_s,
|
||||
shift_source_q : std_logic;
|
||||
signal shift_rise_edge_s : boolean;
|
||||
|
||||
signal lfsr_q : std_logic_vector(0 to 15);
|
||||
|
||||
signal freq_s : signed(0 to 1);
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process cpu_regs
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the registers writable by the CPU.
|
||||
--
|
||||
cpu_regs: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
nf_q <= (others => '0');
|
||||
fb_q <= '0';
|
||||
a_q <= (others => '1');
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i and we_i then
|
||||
if r2_i = '0' then
|
||||
-- access to control register
|
||||
-- both access types can write to the control register!
|
||||
nf_q <= d_i(6 to 7);
|
||||
fb_q <= d_i(5);
|
||||
|
||||
else
|
||||
-- access to attenuator register
|
||||
-- both access types can write to the attenuator register!
|
||||
a_q <= d_i(4 to 7);
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process cpu_regs;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process freq_gen
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the frequency generation components.
|
||||
--
|
||||
freq_gen: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
freq_cnt_q <= (others => '0');
|
||||
freq_ff_q <= '0';
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i then
|
||||
if freq_cnt_q = 0 then
|
||||
-- reload frequency counter according to NF setting
|
||||
case nf_q is
|
||||
when "00" =>
|
||||
freq_cnt_q <= to_unsigned(16 * 2 - 1, freq_cnt_q'length);
|
||||
when "01" =>
|
||||
freq_cnt_q <= to_unsigned(16 * 4 - 1, freq_cnt_q'length);
|
||||
when "10" =>
|
||||
freq_cnt_q <= to_unsigned(16 * 8 - 1, freq_cnt_q'length);
|
||||
when others =>
|
||||
null;
|
||||
end case;
|
||||
|
||||
freq_ff_q <= not freq_ff_q;
|
||||
|
||||
else
|
||||
-- decrement frequency counter
|
||||
freq_cnt_q <= freq_cnt_q - 1;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process freq_gen;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Multiplex the source of the LFSR's shift enable
|
||||
-----------------------------------------------------------------------------
|
||||
shift_source_s <= tone3_ff_i
|
||||
when nf_q = "11" else
|
||||
freq_ff_q;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process rise_edge
|
||||
--
|
||||
-- Purpose:
|
||||
-- Detect the rising edge of the selected LFSR shift source.
|
||||
--
|
||||
rise_edge: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
shift_source_q <= '0';
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i then
|
||||
shift_source_q <= shift_source_s;
|
||||
end if;
|
||||
end if;
|
||||
end process rise_edge;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
-- detect rising edge on shift source
|
||||
shift_rise_edge_s <= shift_source_q = '0' and shift_source_s = '1';
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process lfsr
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the LFSR that generates noise.
|
||||
-- Note: This implementation shifts the register right, i.e. from index
|
||||
-- 15 towards 0 => bit 15 is the input, bit 0 is the output
|
||||
--
|
||||
-- Tapped bits according to MAME's sn76496.c, implemented in function
|
||||
-- lfsr_tapped_f.
|
||||
--
|
||||
lfsr: process (clock_i, res_n_i)
|
||||
|
||||
function lfsr_tapped_f(lfsr : in std_logic_vector) return std_logic is
|
||||
constant tapped_bits_c : std_logic_vector(0 to 15)
|
||||
-- tapped bits are 0, 2, 15
|
||||
:= "1010000000000001";
|
||||
variable parity_v : std_logic;
|
||||
begin
|
||||
parity_v := '0';
|
||||
|
||||
for idx in lfsr'low to lfsr'high loop
|
||||
parity_v := parity_v xor (lfsr(idx) and tapped_bits_c(idx));
|
||||
end loop;
|
||||
|
||||
return parity_v;
|
||||
end;
|
||||
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
-- reset LFSR to "0000000000000001"
|
||||
lfsr_q <= (others => '0');
|
||||
lfsr_q(lfsr_q'right) <= '1';
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i then
|
||||
if we_i and r2_i = '0' then
|
||||
-- write to noise register
|
||||
-- -> reset LFSR
|
||||
lfsr_q <= (others => '0');
|
||||
lfsr_q(lfsr_q'right) <= '1';
|
||||
|
||||
elsif shift_rise_edge_s then
|
||||
|
||||
-- shift LFSR left towards MSB
|
||||
for idx in lfsr_q'right-1 downto lfsr_q'left loop
|
||||
lfsr_q(idx) <= lfsr_q(idx+1);
|
||||
end loop;
|
||||
|
||||
-- determine input bit
|
||||
if fb_q = '0' then
|
||||
-- "Periodic" Noise
|
||||
-- -> input to LFSR is output
|
||||
lfsr_q(lfsr_q'right) <= lfsr_q(lfsr_q'left);
|
||||
else
|
||||
-- "White" Noise
|
||||
-- -> input to LFSR is parity of tapped bits
|
||||
lfsr_q(lfsr_q'right) <= lfsr_tapped_f(lfsr_q);
|
||||
end if;
|
||||
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end process lfsr;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Map output of LFSR to signed value for attenuator.
|
||||
-----------------------------------------------------------------------------
|
||||
freq_s <= to_signed(+1, 2)
|
||||
when lfsr_q(0) = '1' else
|
||||
to_signed( 0, 2);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- The attenuator itself
|
||||
-----------------------------------------------------------------------------
|
||||
attenuator_b : entity work.sn76489_attenuator
|
||||
port map (
|
||||
attenuation_i => a_q,
|
||||
factor_i => freq_s,
|
||||
product_o => noise_o
|
||||
);
|
||||
|
||||
end rtl;
|
||||
@@ -1,188 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_tone.vhd,v 1.5 2006/02/27 20:30:10 arnim Exp $
|
||||
--
|
||||
-- Tone Generator
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity sn76489_tone is
|
||||
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
clk_en_i : in boolean;
|
||||
res_n_i : in std_logic;
|
||||
we_i : in boolean;
|
||||
d_i : in std_logic_vector(0 to 7);
|
||||
r2_i : in std_logic;
|
||||
ff_o : out std_logic;
|
||||
tone_o : out signed(0 to 7)
|
||||
);
|
||||
|
||||
end sn76489_tone;
|
||||
|
||||
architecture rtl of sn76489_tone is
|
||||
|
||||
signal f_q : std_logic_vector(0 to 9);
|
||||
signal a_q : std_logic_vector(0 to 3);
|
||||
signal freq_cnt_q : unsigned(0 to 9);
|
||||
signal freq_ff_q : std_logic;
|
||||
|
||||
signal freq_s : signed(0 to 1);
|
||||
|
||||
function all_zero(a : in std_logic_vector) return boolean is
|
||||
variable result_v : boolean;
|
||||
begin
|
||||
result_v := true;
|
||||
|
||||
for idx in a'low to a'high loop
|
||||
if a(idx) /= '0' then
|
||||
result_v := false;
|
||||
end if;
|
||||
end loop;
|
||||
|
||||
return result_v;
|
||||
end;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process cpu_regs
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the registers writable by the CPU.
|
||||
--
|
||||
cpu_regs: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
f_q <= (others => '0');
|
||||
a_q <= (others => '1');
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i and we_i then
|
||||
if r2_i = '0' then
|
||||
-- access to frequency register
|
||||
if d_i(0) = '0' then
|
||||
f_q(0 to 5) <= d_i(2 to 7);
|
||||
else
|
||||
f_q(6 to 9) <= d_i(4 to 7);
|
||||
end if;
|
||||
|
||||
else
|
||||
-- access to attenuator register
|
||||
-- both access types can write to the attenuator register!
|
||||
a_q <= d_i(4 to 7);
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process cpu_regs;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Process freq_gen
|
||||
--
|
||||
-- Purpose:
|
||||
-- Implements the frequency generation components.
|
||||
--
|
||||
freq_gen: process (clock_i, res_n_i)
|
||||
begin
|
||||
if res_n_i = '0' then
|
||||
freq_cnt_q <= (others => '0');
|
||||
freq_ff_q <= '0';
|
||||
|
||||
elsif clock_i'event and clock_i = '1' then
|
||||
if clk_en_i then
|
||||
if freq_cnt_q = 0 then
|
||||
-- update counter from frequency register
|
||||
freq_cnt_q <= unsigned(f_q);
|
||||
|
||||
-- and toggle the frequency flip-flop if enabled
|
||||
if not all_zero(f_q) then
|
||||
freq_ff_q <= not freq_ff_q;
|
||||
else
|
||||
-- if frequency setting is 0, then keep flip-flop at +1
|
||||
freq_ff_q <= '1';
|
||||
end if;
|
||||
|
||||
else
|
||||
-- decrement frequency counter
|
||||
freq_cnt_q <= freq_cnt_q - 1;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process freq_gen;
|
||||
--
|
||||
-----------------------------------------------------------------------------
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Map frequency flip-flop to signed value for attenuator.
|
||||
-----------------------------------------------------------------------------
|
||||
freq_s <= to_signed(+1, 2)
|
||||
when freq_ff_q = '1' else
|
||||
to_signed(-1, 2);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- The attenuator itself
|
||||
-----------------------------------------------------------------------------
|
||||
attenuator_b : entity work.sn76489_attenuator
|
||||
port map (
|
||||
attenuation_i => a_q,
|
||||
factor_i => freq_s,
|
||||
product_o => tone_o
|
||||
);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Output mapping
|
||||
-----------------------------------------------------------------------------
|
||||
ff_o <= freq_ff_q;
|
||||
|
||||
end rtl;
|
||||
@@ -1,200 +0,0 @@
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Synthesizable model of TI's SN76489AN.
|
||||
--
|
||||
-- $Id: sn76489_top.vhd,v 1.9 2006/02/27 20:30:10 arnim Exp $
|
||||
--
|
||||
-- Chip Toplevel
|
||||
--
|
||||
-- References:
|
||||
--
|
||||
-- * TI Data sheet SN76489.pdf
|
||||
-- ftp://ftp.whtech.com/datasheets%20&%20manuals/SN76489.pdf
|
||||
--
|
||||
-- * John Kortink's article on the SN76489:
|
||||
-- http://web.inter.nl.net/users/J.Kortink/home/articles/sn76489/
|
||||
--
|
||||
-- * Maxim's "SN76489 notes" in
|
||||
-- http://www.smspower.org/maxim/docs/SN76489.txt
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
--
|
||||
-- Copyright (c) 2005, 2006, Arnim Laeuger (arnim.laeuger@gmx.net)
|
||||
--
|
||||
-- All rights reserved
|
||||
--
|
||||
-- Redistribution and use in source and synthezised forms, with or without
|
||||
-- modification, are permitted provided that the following conditions are met:
|
||||
--
|
||||
-- Redistributions of source code must retain the above copyright notice,
|
||||
-- this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- Redistributions in synthesized form must reproduce the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer in the
|
||||
-- documentation and/or other materials provided with the distribution.
|
||||
--
|
||||
-- Neither the name of the author nor the names of other contributors may
|
||||
-- be used to endorse or promote products derived from this software without
|
||||
-- specific prior written permission.
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
|
||||
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
-- Please report bugs to the author, but before you do so, please
|
||||
-- make sure that this is not a derivative work and that
|
||||
-- you have the latest version of this file.
|
||||
--
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
library ieee;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity sn76489_top is
|
||||
|
||||
generic (
|
||||
clock_div_16_g : integer := 1
|
||||
);
|
||||
port (
|
||||
clock_i : in std_logic;
|
||||
clock_en_i : in std_logic;
|
||||
res_n_i : in std_logic;
|
||||
ce_n_i : in std_logic;
|
||||
we_n_i : in std_logic;
|
||||
ready_o : out std_logic;
|
||||
d_i : in std_logic_vector(0 to 7);
|
||||
aout_o : out signed(0 to 7)
|
||||
);
|
||||
|
||||
end sn76489_top;
|
||||
|
||||
architecture struct of sn76489_top is
|
||||
|
||||
signal clk_en_s : boolean;
|
||||
|
||||
signal tone1_we_s,
|
||||
tone2_we_s,
|
||||
tone3_we_s,
|
||||
noise_we_s : boolean;
|
||||
signal r2_s : std_logic;
|
||||
|
||||
signal tone1_s,
|
||||
tone2_s,
|
||||
tone3_s,
|
||||
noise_s : signed(0 to 7);
|
||||
|
||||
signal tone3_ff_s : std_logic;
|
||||
|
||||
begin
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Clock Divider
|
||||
-----------------------------------------------------------------------------
|
||||
clock_div_b : entity work.sn76489_clock_div
|
||||
generic map (
|
||||
clock_div_16_g => clock_div_16_g
|
||||
)
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clock_en_i => clock_en_i,
|
||||
res_n_i => res_n_i,
|
||||
clk_en_o => clk_en_s
|
||||
);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Latch Control = CPU Interface
|
||||
-----------------------------------------------------------------------------
|
||||
latch_ctrl_b : entity work.sn76489_latch_ctrl
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clk_en_i => clk_en_s,
|
||||
res_n_i => res_n_i,
|
||||
ce_n_i => ce_n_i,
|
||||
we_n_i => we_n_i,
|
||||
d_i => d_i,
|
||||
ready_o => ready_o,
|
||||
tone1_we_o => tone1_we_s,
|
||||
tone2_we_o => tone2_we_s,
|
||||
tone3_we_o => tone3_we_s,
|
||||
noise_we_o => noise_we_s,
|
||||
r2_o => r2_s
|
||||
);
|
||||
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Tone Channel 1
|
||||
-----------------------------------------------------------------------------
|
||||
tone1_b : entity work.sn76489_tone
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clk_en_i => clk_en_s,
|
||||
res_n_i => res_n_i,
|
||||
we_i => tone1_we_s,
|
||||
d_i => d_i,
|
||||
r2_i => r2_s,
|
||||
ff_o => open,
|
||||
tone_o => tone1_s
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Tone Channel 2
|
||||
-----------------------------------------------------------------------------
|
||||
tone2_b : entity work.sn76489_tone
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clk_en_i => clk_en_s,
|
||||
res_n_i => res_n_i,
|
||||
we_i => tone2_we_s,
|
||||
d_i => d_i,
|
||||
r2_i => r2_s,
|
||||
ff_o => open,
|
||||
tone_o => tone2_s
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Tone Channel 3
|
||||
-----------------------------------------------------------------------------
|
||||
tone3_b : entity work.sn76489_tone
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clk_en_i => clk_en_s,
|
||||
res_n_i => res_n_i,
|
||||
we_i => tone3_we_s,
|
||||
d_i => d_i,
|
||||
r2_i => r2_s,
|
||||
ff_o => tone3_ff_s,
|
||||
tone_o => tone3_s
|
||||
);
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Noise Channel
|
||||
-----------------------------------------------------------------------------
|
||||
noise_b : entity work.sn76489_noise
|
||||
port map (
|
||||
clock_i => clock_i,
|
||||
clk_en_i => clk_en_s,
|
||||
res_n_i => res_n_i,
|
||||
we_i => noise_we_s,
|
||||
d_i => d_i,
|
||||
r2_i => r2_s,
|
||||
tone3_ff_i => tone3_ff_s,
|
||||
noise_o => noise_s
|
||||
);
|
||||
|
||||
|
||||
aout_o <= tone1_s + tone2_s + tone3_s + noise_s;
|
||||
|
||||
end struct;
|
||||
@@ -1,55 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.altera_mf_components.all;
|
||||
|
||||
ENTITY spram IS
|
||||
generic (
|
||||
addr_width_g : integer := 8;
|
||||
data_width_g : integer := 8
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
|
||||
clken : IN STD_LOGIC := '1';
|
||||
clock : IN STD_LOGIC := '1';
|
||||
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
|
||||
wren : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
|
||||
);
|
||||
END spram;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF spram IS
|
||||
|
||||
BEGIN
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
clock_enable_input_a => "NORMAL",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**addr_width_g,
|
||||
operation_mode => "SINGLE_PORT",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => "UNREGISTERED",
|
||||
power_up_uninitialized => "FALSE",
|
||||
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
|
||||
widthad_a => addr_width_g,
|
||||
width_a => data_width_g,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
address_a => address,
|
||||
clock0 => clock,
|
||||
clocken0 => clken,
|
||||
data_a => data,
|
||||
wren_a => wren,
|
||||
q_a => q
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@@ -1,82 +0,0 @@
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.all;
|
||||
|
||||
LIBRARY altera_mf;
|
||||
USE altera_mf.all;
|
||||
|
||||
ENTITY sprom IS
|
||||
GENERIC
|
||||
(
|
||||
init_file : string := "";
|
||||
widthad_a : natural;
|
||||
width_a : natural := 8;
|
||||
outdata_reg_a : string := "UNREGISTERED"
|
||||
);
|
||||
PORT
|
||||
(
|
||||
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
clock : IN STD_LOGIC ;
|
||||
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END sprom;
|
||||
|
||||
|
||||
ARCHITECTURE SYN OF sprom IS
|
||||
|
||||
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
|
||||
|
||||
|
||||
|
||||
COMPONENT altsyncram
|
||||
GENERIC (
|
||||
address_aclr_a : STRING;
|
||||
clock_enable_input_a : STRING;
|
||||
clock_enable_output_a : STRING;
|
||||
init_file : STRING;
|
||||
intended_device_family : STRING;
|
||||
lpm_hint : STRING;
|
||||
lpm_type : STRING;
|
||||
numwords_a : NATURAL;
|
||||
operation_mode : STRING;
|
||||
outdata_aclr_a : STRING;
|
||||
outdata_reg_a : STRING;
|
||||
widthad_a : NATURAL;
|
||||
width_a : NATURAL;
|
||||
width_byteena_a : NATURAL
|
||||
);
|
||||
PORT (
|
||||
clock0 : IN STD_LOGIC ;
|
||||
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
|
||||
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
BEGIN
|
||||
q <= sub_wire0(width_a-1 DOWNTO 0);
|
||||
|
||||
altsyncram_component : altsyncram
|
||||
GENERIC MAP (
|
||||
address_aclr_a => "NONE",
|
||||
clock_enable_input_a => "BYPASS",
|
||||
clock_enable_output_a => "BYPASS",
|
||||
init_file => init_file,
|
||||
intended_device_family => "Cyclone III",
|
||||
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
|
||||
lpm_type => "altsyncram",
|
||||
numwords_a => 2**widthad_a,
|
||||
operation_mode => "ROM",
|
||||
outdata_aclr_a => "NONE",
|
||||
outdata_reg_a => outdata_reg_a,
|
||||
widthad_a => widthad_a,
|
||||
width_a => width_a,
|
||||
width_byteena_a => 1
|
||||
)
|
||||
PORT MAP (
|
||||
clock0 => clock,
|
||||
address_a => address,
|
||||
q_a => sub_wire0
|
||||
);
|
||||
|
||||
|
||||
|
||||
END SYN;
|
||||
@@ -1,442 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
module tv80_alu (/*AUTOARG*/
|
||||
// Outputs
|
||||
Q, F_Out,
|
||||
// Inputs
|
||||
Arith16, Z16, ALU_Op, IR, ISet, BusA, BusB, F_In
|
||||
);
|
||||
|
||||
parameter Mode = 0;
|
||||
parameter Flag_C = 0;
|
||||
parameter Flag_N = 1;
|
||||
parameter Flag_P = 2;
|
||||
parameter Flag_X = 3;
|
||||
parameter Flag_H = 4;
|
||||
parameter Flag_Y = 5;
|
||||
parameter Flag_Z = 6;
|
||||
parameter Flag_S = 7;
|
||||
|
||||
input Arith16;
|
||||
input Z16;
|
||||
input [3:0] ALU_Op ;
|
||||
input [5:0] IR;
|
||||
input [1:0] ISet;
|
||||
input [7:0] BusA;
|
||||
input [7:0] BusB;
|
||||
input [7:0] F_In;
|
||||
output [7:0] Q;
|
||||
output [7:0] F_Out;
|
||||
reg [7:0] Q;
|
||||
reg [7:0] F_Out;
|
||||
|
||||
function [4:0] AddSub4;
|
||||
input [3:0] A;
|
||||
input [3:0] B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub4 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {4'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
function [3:0] AddSub3;
|
||||
input [2:0] A;
|
||||
input [2:0] B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub3 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {3'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
function [1:0] AddSub1;
|
||||
input A;
|
||||
input B;
|
||||
input Sub;
|
||||
input Carry_In;
|
||||
begin
|
||||
AddSub1 = { 1'b0, A } + { 1'b0, (Sub)?~B:B } + {1'h0,Carry_In};
|
||||
end
|
||||
endfunction // AddSub4
|
||||
|
||||
// AddSub variables (temporary signals)
|
||||
reg UseCarry;
|
||||
reg Carry7_v;
|
||||
reg OverFlow_v;
|
||||
reg HalfCarry_v;
|
||||
reg Carry_v;
|
||||
reg [7:0] Q_v;
|
||||
|
||||
reg [7:0] BitMask;
|
||||
|
||||
|
||||
always @(/*AUTOSENSE*/ALU_Op or BusA or BusB or F_In or IR)
|
||||
begin
|
||||
case (IR[5:3])
|
||||
3'b000 : BitMask = 8'b00000001;
|
||||
3'b001 : BitMask = 8'b00000010;
|
||||
3'b010 : BitMask = 8'b00000100;
|
||||
3'b011 : BitMask = 8'b00001000;
|
||||
3'b100 : BitMask = 8'b00010000;
|
||||
3'b101 : BitMask = 8'b00100000;
|
||||
3'b110 : BitMask = 8'b01000000;
|
||||
default: BitMask = 8'b10000000;
|
||||
endcase // case(IR[5:3])
|
||||
|
||||
UseCarry = ~ ALU_Op[2] && ALU_Op[0];
|
||||
{ HalfCarry_v, Q_v[3:0] } = AddSub4(BusA[3:0], BusB[3:0], ALU_Op[1], ALU_Op[1] ^ (UseCarry && F_In[Flag_C]) );
|
||||
{ Carry7_v, Q_v[6:4] } = AddSub3(BusA[6:4], BusB[6:4], ALU_Op[1], HalfCarry_v);
|
||||
{ Carry_v, Q_v[7] } = AddSub1(BusA[7], BusB[7], ALU_Op[1], Carry7_v);
|
||||
OverFlow_v = Carry_v ^ Carry7_v;
|
||||
end // always @ *
|
||||
|
||||
reg [7:0] Q_t;
|
||||
reg [8:0] DAA_Q;
|
||||
|
||||
always @ (/*AUTOSENSE*/ALU_Op or Arith16 or BitMask or BusA or BusB
|
||||
or Carry_v or F_In or HalfCarry_v or IR or ISet
|
||||
or OverFlow_v or Q_v or Z16)
|
||||
begin
|
||||
Q_t = 8'hxx;
|
||||
DAA_Q = {9{1'bx}};
|
||||
|
||||
F_Out = F_In;
|
||||
case (ALU_Op)
|
||||
4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111 :
|
||||
begin
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_C] = 1'b0;
|
||||
|
||||
case (ALU_Op[2:0])
|
||||
|
||||
3'b000, 3'b001 : // ADD, ADC
|
||||
begin
|
||||
Q_t = Q_v;
|
||||
F_Out[Flag_C] = Carry_v;
|
||||
F_Out[Flag_H] = HalfCarry_v;
|
||||
F_Out[Flag_P] = OverFlow_v;
|
||||
end
|
||||
|
||||
3'b010, 3'b011, 3'b111 : // SUB, SBC, CP
|
||||
begin
|
||||
Q_t = Q_v;
|
||||
F_Out[Flag_N] = 1'b1;
|
||||
F_Out[Flag_C] = ~ Carry_v;
|
||||
F_Out[Flag_H] = ~ HalfCarry_v;
|
||||
F_Out[Flag_P] = OverFlow_v;
|
||||
end
|
||||
|
||||
3'b100 : // AND
|
||||
begin
|
||||
Q_t[7:0] = BusA & BusB;
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
end
|
||||
|
||||
3'b101 : // XOR
|
||||
begin
|
||||
Q_t[7:0] = BusA ^ BusB;
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
|
||||
default : // OR 3'b110
|
||||
begin
|
||||
Q_t[7:0] = BusA | BusB;
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
|
||||
endcase // case(ALU_OP[2:0])
|
||||
|
||||
if (ALU_Op[2:0] == 3'b111 )
|
||||
begin // CP
|
||||
F_Out[Flag_X] = BusB[3];
|
||||
F_Out[Flag_Y] = BusB[5];
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
end
|
||||
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
if (Z16 == 1'b1 )
|
||||
begin
|
||||
F_Out[Flag_Z] = F_In[Flag_Z]; // 16 bit ADC,SBC
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end // else: !if(Q_t[7:0] == 8'b00000000 )
|
||||
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
case (ALU_Op[2:0])
|
||||
3'b000, 3'b001, 3'b010, 3'b011, 3'b111 : // ADD, ADC, SUB, SBC, CP
|
||||
;
|
||||
|
||||
default :
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
endcase // case(ALU_Op[2:0])
|
||||
|
||||
if (Arith16 == 1'b1 )
|
||||
begin
|
||||
F_Out[Flag_S] = F_In[Flag_S];
|
||||
F_Out[Flag_Z] = F_In[Flag_Z];
|
||||
F_Out[Flag_P] = F_In[Flag_P];
|
||||
end
|
||||
end // case: 4'b0000, 4'b0001, 4'b0010, 4'b0011, 4'b0100, 4'b0101, 4'b0110, 4'b0111
|
||||
|
||||
4'b1100 :
|
||||
begin
|
||||
// DAA
|
||||
F_Out[Flag_H] = F_In[Flag_H];
|
||||
F_Out[Flag_C] = F_In[Flag_C];
|
||||
DAA_Q[7:0] = BusA;
|
||||
DAA_Q[8] = 1'b0;
|
||||
if (F_In[Flag_N] == 1'b0 )
|
||||
begin
|
||||
// After addition
|
||||
// Alow > 9 || H == 1
|
||||
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
begin
|
||||
if ((DAA_Q[3:0] > 9) )
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
DAA_Q = DAA_Q + 6;
|
||||
end // if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
|
||||
// new Ahigh > 9 || C == 1
|
||||
if (DAA_Q[8:4] > 9 || F_In[Flag_C] == 1'b1 )
|
||||
begin
|
||||
DAA_Q = DAA_Q + 96; // 0x60
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
// After subtraction
|
||||
if (DAA_Q[3:0] > 9 || F_In[Flag_H] == 1'b1 )
|
||||
begin
|
||||
if (DAA_Q[3:0] > 5 )
|
||||
begin
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
end
|
||||
DAA_Q[7:0] = DAA_Q[7:0] - 6;
|
||||
end
|
||||
if (BusA > 153 || F_In[Flag_C] == 1'b1 )
|
||||
begin
|
||||
DAA_Q = DAA_Q - 352; // 0x160
|
||||
end
|
||||
end // else: !if(F_In[Flag_N] == 1'b0 )
|
||||
|
||||
F_Out[Flag_X] = DAA_Q[3];
|
||||
F_Out[Flag_Y] = DAA_Q[5];
|
||||
F_Out[Flag_C] = F_In[Flag_C] || DAA_Q[8];
|
||||
Q_t = DAA_Q[7:0];
|
||||
|
||||
if (DAA_Q[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
|
||||
F_Out[Flag_S] = DAA_Q[7];
|
||||
F_Out[Flag_P] = ~ (^DAA_Q);
|
||||
end // case: 4'b1100
|
||||
|
||||
4'b1101, 4'b1110 :
|
||||
begin
|
||||
// RLD, RRD
|
||||
Q_t[7:4] = BusA[7:4];
|
||||
if (ALU_Op[0] == 1'b1 )
|
||||
begin
|
||||
Q_t[3:0] = BusB[7:4];
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q_t[3:0] = BusB[3:0];
|
||||
end
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
end // case: when 4'b1101, 4'b1110
|
||||
|
||||
4'b1001 :
|
||||
begin
|
||||
// BIT
|
||||
Q_t[7:0] = BusB & BitMask;
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
F_Out[Flag_P] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
F_Out[Flag_P] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_H] = 1'b1;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = 1'b0;
|
||||
F_Out[Flag_Y] = 1'b0;
|
||||
if (IR[2:0] != 3'b110 )
|
||||
begin
|
||||
F_Out[Flag_X] = BusB[3];
|
||||
F_Out[Flag_Y] = BusB[5];
|
||||
end
|
||||
end // case: when 4'b1001
|
||||
|
||||
4'b1010 :
|
||||
// SET
|
||||
Q_t[7:0] = BusB | BitMask;
|
||||
|
||||
4'b1011 :
|
||||
// RES
|
||||
Q_t[7:0] = BusB & ~ BitMask;
|
||||
|
||||
4'b1000 :
|
||||
begin
|
||||
// ROT
|
||||
case (IR[5:3])
|
||||
3'b000 : // RLC
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = BusA[7];
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b010 : // RL
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = F_In[Flag_C];
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b001 : // RRC
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = BusA[0];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
3'b011 : // RR
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = F_In[Flag_C];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
3'b100 : // SLA
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = 1'b0;
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end
|
||||
|
||||
3'b110 : // SLL (Undocumented) / SWAP
|
||||
begin
|
||||
if (Mode == 3 )
|
||||
begin
|
||||
Q_t[7:4] = BusA[3:0];
|
||||
Q_t[3:0] = BusA[7:4];
|
||||
F_Out[Flag_C] = 1'b0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
Q_t[7:1] = BusA[6:0];
|
||||
Q_t[0] = 1'b1;
|
||||
F_Out[Flag_C] = BusA[7];
|
||||
end // else: !if(Mode == 3 )
|
||||
end // case: 3'b110
|
||||
|
||||
3'b101 : // SRA
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = BusA[7];
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
|
||||
default : // SRL
|
||||
begin
|
||||
Q_t[6:0] = BusA[7:1];
|
||||
Q_t[7] = 1'b0;
|
||||
F_Out[Flag_C] = BusA[0];
|
||||
end
|
||||
endcase // case(IR[5:3])
|
||||
|
||||
F_Out[Flag_H] = 1'b0;
|
||||
F_Out[Flag_N] = 1'b0;
|
||||
F_Out[Flag_X] = Q_t[3];
|
||||
F_Out[Flag_Y] = Q_t[5];
|
||||
F_Out[Flag_S] = Q_t[7];
|
||||
if (Q_t[7:0] == 8'b00000000 )
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
F_Out[Flag_Z] = 1'b0;
|
||||
end
|
||||
F_Out[Flag_P] = ~(^Q_t);
|
||||
|
||||
if (ISet == 2'b00 )
|
||||
begin
|
||||
F_Out[Flag_P] = F_In[Flag_P];
|
||||
F_Out[Flag_S] = F_In[Flag_S];
|
||||
F_Out[Flag_Z] = F_In[Flag_Z];
|
||||
end
|
||||
end // case: 4'b1000
|
||||
|
||||
|
||||
default :
|
||||
;
|
||||
|
||||
endcase // case(ALU_Op)
|
||||
|
||||
Q = Q_t;
|
||||
end // always @ (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
|
||||
|
||||
endmodule // T80_ALU
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,77 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
module tv80_reg (/*AUTOARG*/
|
||||
// Outputs
|
||||
DOBH, DOAL, DOCL, DOBL, DOCH, DOAH,
|
||||
// Inputs
|
||||
AddrC, AddrA, AddrB, DIH, DIL, clk, CEN, WEH, WEL
|
||||
);
|
||||
input [2:0] AddrC;
|
||||
output [7:0] DOBH;
|
||||
input [2:0] AddrA;
|
||||
input [2:0] AddrB;
|
||||
input [7:0] DIH;
|
||||
output [7:0] DOAL;
|
||||
output [7:0] DOCL;
|
||||
input [7:0] DIL;
|
||||
output [7:0] DOBL;
|
||||
output [7:0] DOCH;
|
||||
output [7:0] DOAH;
|
||||
input clk, CEN, WEH, WEL;
|
||||
|
||||
reg [7:0] RegsH [0:7];
|
||||
reg [7:0] RegsL [0:7];
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (CEN)
|
||||
begin
|
||||
if (WEH) RegsH[AddrA] <= DIH;
|
||||
if (WEL) RegsL[AddrA] <= DIL;
|
||||
end
|
||||
end
|
||||
|
||||
assign DOAH = RegsH[AddrA];
|
||||
assign DOAL = RegsL[AddrA];
|
||||
assign DOBH = RegsH[AddrB];
|
||||
assign DOBL = RegsL[AddrB];
|
||||
assign DOCH = RegsH[AddrC];
|
||||
assign DOCL = RegsL[AddrC];
|
||||
|
||||
// break out ram bits for waveform debug
|
||||
// synopsys translate_off
|
||||
wire [7:0] B = RegsH[0];
|
||||
wire [7:0] C = RegsL[0];
|
||||
wire [7:0] D = RegsH[1];
|
||||
wire [7:0] E = RegsL[1];
|
||||
wire [7:0] H = RegsH[2];
|
||||
wire [7:0] L = RegsL[2];
|
||||
|
||||
wire [15:0] IX = { RegsH[3], RegsL[3] };
|
||||
wire [15:0] IY = { RegsH[7], RegsL[7] };
|
||||
// synopsys translate_on
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,182 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
// Negative-edge based wrapper allows memory wait_n signal to work
|
||||
// correctly without resorting to asynchronous logic.
|
||||
|
||||
module tv80n (/*AUTOARG*/
|
||||
// Outputs
|
||||
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
|
||||
// Inputs
|
||||
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
|
||||
);
|
||||
|
||||
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
parameter T2Write = 0; // 0 => wr_n active in T3, /=0 => wr_n active in T2
|
||||
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
|
||||
|
||||
input reset_n;
|
||||
input clk;
|
||||
input wait_n;
|
||||
input int_n;
|
||||
input nmi_n;
|
||||
input busrq_n;
|
||||
output m1_n;
|
||||
output mreq_n;
|
||||
output iorq_n;
|
||||
output rd_n;
|
||||
output wr_n;
|
||||
output rfsh_n;
|
||||
output halt_n;
|
||||
output busak_n;
|
||||
output [15:0] A;
|
||||
input [7:0] di;
|
||||
output [7:0] dout;
|
||||
|
||||
reg mreq_n;
|
||||
reg iorq_n;
|
||||
reg rd_n;
|
||||
reg wr_n;
|
||||
reg nxt_mreq_n;
|
||||
reg nxt_iorq_n;
|
||||
reg nxt_rd_n;
|
||||
reg nxt_wr_n;
|
||||
|
||||
wire cen;
|
||||
wire intcycle_n;
|
||||
wire no_read;
|
||||
wire write;
|
||||
wire iorq;
|
||||
reg [7:0] di_reg;
|
||||
wire [6:0] mcycle;
|
||||
wire [6:0] tstate;
|
||||
|
||||
assign cen = 1;
|
||||
|
||||
tv80_core #(Mode, IOWait) i_tv80_core
|
||||
(
|
||||
.cen (cen),
|
||||
.m1_n (m1_n),
|
||||
.iorq (iorq),
|
||||
.no_read (no_read),
|
||||
.write (write),
|
||||
.rfsh_n (rfsh_n),
|
||||
.halt_n (halt_n),
|
||||
.wait_n (wait_n),
|
||||
.int_n (int_n),
|
||||
.nmi_n (nmi_n),
|
||||
.reset_n (reset_n),
|
||||
.busrq_n (busrq_n),
|
||||
.busak_n (busak_n),
|
||||
.clk (clk),
|
||||
.IntE (),
|
||||
.stop (),
|
||||
.A (A),
|
||||
.dinst (di),
|
||||
.di (di_reg),
|
||||
.dout (dout),
|
||||
.mc (mcycle),
|
||||
.ts (tstate),
|
||||
.intcycle_n (intcycle_n)
|
||||
);
|
||||
|
||||
always @*
|
||||
begin
|
||||
nxt_mreq_n = 1;
|
||||
nxt_rd_n = 1;
|
||||
nxt_iorq_n = 1;
|
||||
nxt_wr_n = 1;
|
||||
|
||||
if (mcycle[0])
|
||||
begin
|
||||
if (tstate[1] || tstate[2])
|
||||
begin
|
||||
nxt_rd_n = ~ intcycle_n;
|
||||
nxt_mreq_n = ~ intcycle_n;
|
||||
nxt_iorq_n = intcycle_n;
|
||||
end
|
||||
end // if (mcycle[0])
|
||||
else
|
||||
begin
|
||||
if ((tstate[1] || tstate[2]) && !no_read && !write)
|
||||
begin
|
||||
nxt_rd_n = 1'b0;
|
||||
nxt_iorq_n = ~ iorq;
|
||||
nxt_mreq_n = iorq;
|
||||
end
|
||||
if (T2Write == 0)
|
||||
begin
|
||||
if (tstate[2] && write)
|
||||
begin
|
||||
nxt_wr_n = 1'b0;
|
||||
nxt_iorq_n = ~ iorq;
|
||||
nxt_mreq_n = iorq;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((tstate[1] || (tstate[2] && !wait_n)) && write)
|
||||
begin
|
||||
nxt_wr_n = 1'b0;
|
||||
nxt_iorq_n = ~ iorq;
|
||||
nxt_mreq_n = iorq;
|
||||
end
|
||||
end // else: !if(T2write == 0)
|
||||
end // else: !if(mcycle[0])
|
||||
end // always @ *
|
||||
|
||||
always @(negedge clk)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
rd_n <= #1 1'b1;
|
||||
wr_n <= #1 1'b1;
|
||||
iorq_n <= #1 1'b1;
|
||||
mreq_n <= #1 1'b1;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rd_n <= #1 nxt_rd_n;
|
||||
wr_n <= #1 nxt_wr_n;
|
||||
iorq_n <= #1 nxt_iorq_n;
|
||||
mreq_n <= #1 nxt_mreq_n;
|
||||
end // else: !if(!reset_n)
|
||||
end // always @ (posedge clk or negedge reset_n)
|
||||
|
||||
always @(posedge clk)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
di_reg <= #1 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if (tstate[2] && wait_n == 1'b1)
|
||||
di_reg <= #1 di;
|
||||
end // else: !if(!reset_n)
|
||||
end // always @ (posedge clk)
|
||||
|
||||
endmodule // t80n
|
||||
|
||||
@@ -1,162 +0,0 @@
|
||||
//
|
||||
// TV80 8-Bit Microprocessor Core
|
||||
// Based on the VHDL T80 core by Daniel Wallner (jesus@opencores.org)
|
||||
//
|
||||
// Copyright (c) 2004 Guy Hutchison (ghutchis@opencores.org)
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a
|
||||
// copy of this software and associated documentation files (the "Software"),
|
||||
// to deal in the Software without restriction, including without limitation
|
||||
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
// and/or sell copies of the Software, and to permit persons to whom the
|
||||
// Software is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included
|
||||
// in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
|
||||
module tv80s (/*AUTOARG*/
|
||||
// Outputs
|
||||
m1_n, mreq_n, iorq_n, rd_n, wr_n, rfsh_n, halt_n, busak_n, A, dout,
|
||||
// Inputs
|
||||
reset_n, clk, wait_n, int_n, nmi_n, busrq_n, di
|
||||
);
|
||||
|
||||
parameter Mode = 0; // 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
|
||||
parameter T2Write = 1; // 0 => wr_n active in T3, /=0 => wr_n active in T2
|
||||
parameter IOWait = 1; // 0 => Single cycle I/O, 1 => Std I/O cycle
|
||||
|
||||
|
||||
input reset_n;
|
||||
input clk;
|
||||
input wait_n;
|
||||
input int_n;
|
||||
input nmi_n;
|
||||
input busrq_n;
|
||||
output m1_n;
|
||||
output mreq_n;
|
||||
output iorq_n;
|
||||
output rd_n;
|
||||
output wr_n;
|
||||
output rfsh_n;
|
||||
output halt_n;
|
||||
output busak_n;
|
||||
output [15:0] A;
|
||||
input [7:0] di;
|
||||
output [7:0] dout;
|
||||
|
||||
reg mreq_n;
|
||||
reg iorq_n;
|
||||
reg rd_n;
|
||||
reg wr_n;
|
||||
|
||||
wire cen;
|
||||
wire intcycle_n;
|
||||
wire no_read;
|
||||
wire write;
|
||||
wire iorq;
|
||||
reg [7:0] di_reg;
|
||||
wire [6:0] mcycle;
|
||||
wire [6:0] tstate;
|
||||
|
||||
assign cen = 1;
|
||||
|
||||
tv80_core #(Mode, IOWait) i_tv80_core
|
||||
(
|
||||
.cen (cen),
|
||||
.m1_n (m1_n),
|
||||
.iorq (iorq),
|
||||
.no_read (no_read),
|
||||
.write (write),
|
||||
.rfsh_n (rfsh_n),
|
||||
.halt_n (halt_n),
|
||||
.wait_n (wait_n),
|
||||
.int_n (int_n),
|
||||
.nmi_n (nmi_n),
|
||||
.reset_n (reset_n),
|
||||
.busrq_n (busrq_n),
|
||||
.busak_n (busak_n),
|
||||
.clk (clk),
|
||||
.IntE (),
|
||||
.stop (),
|
||||
.A (A),
|
||||
.dinst (di),
|
||||
.di (di_reg),
|
||||
.dout (dout),
|
||||
.mc (mcycle),
|
||||
.ts (tstate),
|
||||
.intcycle_n (intcycle_n)
|
||||
);
|
||||
|
||||
always @(posedge clk or negedge reset_n)
|
||||
begin
|
||||
if (!reset_n)
|
||||
begin
|
||||
rd_n <= #1 1'b1;
|
||||
wr_n <= #1 1'b1;
|
||||
iorq_n <= #1 1'b1;
|
||||
mreq_n <= #1 1'b1;
|
||||
di_reg <= #1 0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
rd_n <= #1 1'b1;
|
||||
wr_n <= #1 1'b1;
|
||||
iorq_n <= #1 1'b1;
|
||||
mreq_n <= #1 1'b1;
|
||||
if (mcycle[0])
|
||||
begin
|
||||
if (tstate[1] || (tstate[2] && wait_n == 1'b0))
|
||||
begin
|
||||
rd_n <= #1 ~ intcycle_n;
|
||||
mreq_n <= #1 ~ intcycle_n;
|
||||
iorq_n <= #1 intcycle_n;
|
||||
end
|
||||
`ifdef TV80_REFRESH
|
||||
if (tstate[3])
|
||||
mreq_n <= #1 1'b0;
|
||||
`endif
|
||||
end // if (mcycle[0])
|
||||
else
|
||||
begin
|
||||
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && no_read == 1'b0 && write == 1'b0)
|
||||
begin
|
||||
rd_n <= #1 1'b0;
|
||||
iorq_n <= #1 ~ iorq;
|
||||
mreq_n <= #1 iorq;
|
||||
end
|
||||
if (T2Write == 0)
|
||||
begin
|
||||
if (tstate[2] && write == 1'b1)
|
||||
begin
|
||||
wr_n <= #1 1'b0;
|
||||
iorq_n <= #1 ~ iorq;
|
||||
mreq_n <= #1 iorq;
|
||||
end
|
||||
end
|
||||
else
|
||||
begin
|
||||
if ((tstate[1] || (tstate[2] && wait_n == 1'b0)) && write == 1'b1)
|
||||
begin
|
||||
wr_n <= #1 1'b0;
|
||||
iorq_n <= #1 ~ iorq;
|
||||
mreq_n <= #1 iorq;
|
||||
end
|
||||
end // else: !if(T2write == 0)
|
||||
|
||||
end // else: !if(mcycle[0])
|
||||
|
||||
if (tstate[2] && wait_n == 1'b1)
|
||||
di_reg <= #1 di;
|
||||
end // else: !if(!reset_n)
|
||||
end // always @ (posedge clk or negedge reset_n)
|
||||
|
||||
endmodule // t80s
|
||||
|
||||
Reference in New Issue
Block a user