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Acorn System 1 WIP

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Marcel
2019-08-18 22:38:49 +02:00
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31
Computer_MiST/Acorn - System1/Acorn_System1.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 11:17:10 October 25, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "16.1"
DATE = "11:17:10 October 25, 2017"
# Revisions
PROJECT_REVISION = "Acorn_System1"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 16:10:44 August 12, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Acorn_System1_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 15.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:45:13 JUNE 17,2016"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name TOP_LEVEL_ENTITY System1_MiST
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
# ----------------------
# start ENTITY(SNES_top)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(SNES_top)
# --------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/System1_MiST.sv
set_global_assignment -name VERILOG_FILE rtl/System1.v
set_global_assignment -name VERILOG_FILE rtl/cpu.v
set_global_assignment -name VERILOG_FILE rtl/ALU.v
set_global_assignment -name VERILOG_FILE rtl/m6522.v
set_global_assignment -name VHDL_FILE rtl/roms/acrnsys1.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VERILOG_FILE rtl/vga.v
set_global_assignment -name QIP_FILE ../../Mist_FPGA/common/mist/mist.qip
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VHDL_FILE rtl/ps2_mouse.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Computer_MiST/Acorn - System1/Acorn_System1.srf Normal file
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{ "" "" "" "Verilog HDL or VHDL warning at cpu.v(148): object \"brk\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at cpu.v(720): truncated value with size 32 to match size of target (1)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at cpu.v(717): truncated value with size 32 to match size of target (1)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at cpu.v(661): truncated value with size 32 to match size of target (8)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at ALU.v(50): truncated value with size 32 to match size of target (1)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at ALU.v(73): truncated value with size 9 to match size of target (8)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}

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Computer_MiST/Acorn - System1/README.txt Normal file
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Acorn System 1 - Port to MiST
ToDo: Mouse and Keyboard
This is a port of Acorn System 1 inspired by the work of David Banks.
This version has a huge 512 bytes of rom
and a massive 1024 bytes of memory. The display is the latest 9 digit (only 8 used )7 segment plus dp.
The keyboard is 25 soft touch positive click switches.
My first computer was a system 1. I could spend hours entering one machine
code instruction at a time, then more hours debugging my mistakes.
Then switch off and it was all lost.
Ahh those were the days.
I would think that this port will be of limited interest but I could not find any other
port of this machine.
The mouse is the yellow dot on the screen. Left click to press switch.
At present this is a basic system 1 there are no bells or whistles.
No input (tape) or output as yet.
You will have to forgive the vga output, all hand drawn using several hundred 'if' statements.
The quickest way to test is after load, press the rst key. Press 'm' key.
Enter '0015' and press 'm' again.
The address 0015 is the 3rd character from the right. The value shouls read 80.
type any hex character to change the value and the character will change.
Dave Wood (oldgit)

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Computer_MiST/Acorn - System1/Snapshot/Acorn_System1.rbf Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

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Computer_MiST/Acorn - System1/rtl/ALU.v Normal file
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/*
* ALU.
*
* AI and BI are 8 bit inputs. Result in OUT.
* CI is Carry In.
* CO is Carry Out.
*
* op[3:0] is defined as follows:
*
* 0011 AI + BI
* 0111 AI - BI
* 1011 AI + AI
* 1100 AI | BI
* 1101 AI & BI
* 1110 AI ^ BI
* 1111 AI
*
*/
module ALU( clk, op, right, AI, BI, CI, CO, BCD, OUT, V, Z, N, HC, RDY );
input clk;
input right;
input [3:0] op; // operation
input [7:0] AI;
input [7:0] BI;
input CI;
input BCD; // BCD style carry
output [7:0] OUT;
output CO;
output V;
output Z;
output N;
output HC;
input RDY;
reg [7:0] OUT;
reg CO;
wire V;
wire Z;
reg N;
reg HC;
reg AI7;
reg BI7;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
wire [8:0] temp = { temp_h, temp_l[3:0] };
wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// calculate the logic operations. The 'case' can be done in 1 LUT per
// bit. The 'right' shift is a simple mux that can be implemented by
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
// This stage can be done in 1 LUT per bit, using carry chain logic.
always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
// HC9 is the half carry bit when doing BCD add
wire HC9 = BCD & (temp_l[3:1] >= 3'd5);
// CO9 is the carry-out bit when doing BCD add
wire CO9 = BCD & (temp_h[3:1] >= 3'd5);
// combined half carry bit
wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags
always @(posedge clk)
if( RDY ) begin
AI7 <= AI[7];
BI7 <= temp_BI[7];
OUT <= temp[7:0];
CO <= temp[8] | CO9;
N <= temp[7];
HC <= temp_HC;
end
assign V = AI7 ^ BI7 ^ CO ^ N;
assign Z = ~|OUT;
endmodule

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// =======================================================================
//
//
// An Acorn System1 implementation for the Mister
//
// Copyright (C) 2019 Dave Wood
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see http://www.gnu.org/licenses/.
// =======================================================================
module System1(
input clk25,
input reset,
output reg[8:0]ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7,
input sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,sw8,sw9,swa,swb,swc,swd,swe,swf,swrst,swm,swl,swg,swr,swp,swU,sws,swD,
// Cassette / Sound
input cas_in,
output cas_out
);
wire rom_cs;
wire [7:0] rom_dout;
acrnsys1 MONROM(
.clk(clk25 & rom_cs),
.addr(address[8:0]),
.data(rom_dout)
);
wire ram_cs;
wire ram_wr = (!rnw & ram_cs);
wire [7:0] ram_dout;
gen_ram #(
.dWidth(8),
.aWidth(10))
MRAM (
.clk(clk25 & ram_cs),
.we(ram_wr),
.addr(address[9:0]),
.d(cpu_dout),
.q(ram_dout)
);
// ===============================================================
// Wires/Reg definitions
// TODO: reorganize so all defined here
// ===============================================================
reg rnw;
reg [15:0] address;
reg [7:0] cpu_dout;
wire [7:0] via_dout;
wire via_irq_n;
wire [1:0] turbo = 2'b00;
reg lock;
reg [2:0] phase = 3'b000;
reg [2:0] scan = 3'b111;
wire [7:0] PA_out;
reg [7:0] PA_tmp = 8'b00000000;
// ===============================================================
// Clock Enable Generation
// ===============================================================
reg cpu_clken;
reg via1_clken;
reg via4_clken;
reg [4:0] clkdiv = 5'b00000; // divider, from 25MHz down to 1, 2, 4 or 8MHz
always @(posedge clk25) begin
if (clkdiv == 24)
clkdiv <= 0;
else
clkdiv <= clkdiv + 1;
case (turbo)
2'b00: // 1MHz
begin
cpu_clken <= (clkdiv[3:0] == 0) & (clkdiv[4] == 0);
via1_clken <= (clkdiv[3:0] == 0) & (clkdiv[4] == 0);
via4_clken <= (clkdiv[1:0] == 0) & (clkdiv[4] == 0);
end
2'b01: // 2MHz
begin
cpu_clken <= (clkdiv[2:0] == 0) & (clkdiv[4] == 0);
via1_clken <= (clkdiv[2:0] == 0) & (clkdiv[4] == 0);
via4_clken <= (clkdiv[0] == 0) & (clkdiv[4] == 0);
end
default: // 4MHz
begin
cpu_clken <= (clkdiv[1:0] == 0) & (clkdiv[4] == 0);
via1_clken <= (clkdiv[1:0] == 0) & (clkdiv[4] == 0);
via4_clken <= (clkdiv[4] == 0);
end
endcase
end
// ===============================================================
// Cassette
// ===============================================================
// The Atom drives cas_tone from 4MHz / 16 / 13 / 8
// 208 = 16 * 13, and start with 1MHz and toggle
// so it's basically the same
reg cas_tone = 1'b0;
reg [7:0] cas_div = 0;
always @(posedge clk25) begin
if (cpu_clken)
begin
if (cas_div == 207)
begin
cas_div <= 0;
cas_tone <= !cas_tone;
end
else
cas_div <= cas_div + 1;
end
end
// this is a direct translation of the logic in the atom
// (two NAND gates and an inverter)
// assign cas_out = !(!(!cas_tone & pia_pc[1]) & pia_pc[0]);
// assign PB_in[7] = cas_in;
// ===============================================================
// 6502 CPU
// ===============================================================
wire [7:0] cpu_din;
wire [7:0] cpu_dout_c;
wire [15:0] address_c;
wire rnw_c;
// Arlet's 6502 core is one of the smallest available
cpu CPU
(
.clk(clk25),
.reset(swrst | reset),
.AB(address_c),
.DI(cpu_din),
.DO(cpu_dout_c),
.WE(rnw_c),
.IRQ(1'b0), //(!via_irq_n),
.NMI(1'b0),
.RDY(cpu_clken)
);
// The outputs of Arlets's 6502 core need registing
always @(posedge clk25)
begin
if (cpu_clken)
begin
address <= address_c;
cpu_dout <= cpu_dout_c;
rnw <= !rnw_c;
end
end
// ===============================================================
// Address decoding logic and data in multiplexor
// ===============================================================
// 0000-3FFF RAM
// 0Exx-0Fxx 6522 VIA
// FExx-FFxx Monitor Prom
assign rom_cs = (address[15:9] == 7'b1111111); //FE00 - FFFF
wire via_cs = (address[15:9] == 7'b0000111); //0Exx
assign ram_cs = (address[15:10] == 6'b000000); //0000 - 003F
assign cpu_din = via_cs ? via_dout :
ram_cs ? ram_dout :
rom_cs ? rom_dout :
8'b11111111;
// ===============================================================
// 6522 VIA at 0x0Exx
// ===============================================================
wire [7:0] PB_out;
wire [7:0] PB_oe,PA_oe;
reg [7:0] PB_in;
wire pressed = (~sw0 & ~sw1 & ~sw2 & ~sw3 & ~sw4 & ~sw5 & ~sw6 & ~sw7 & ~sw8 & ~sw9 & ~swa & ~swb & ~swc & ~swd & ~swe & ~swf & ~swm & ~swl & ~swg & ~swr & ~swp & ~swU & ~sws & ~swD);
always @(posedge via1_clken) begin
if (pressed) PB_in <= 8'b00111111;
if (phase == 3'b000 && PB_out[2:0] == 3'b111) begin
ch0 <= PA_out;
phase = 3'b001;
if (sw7) PB_in <= 8'b00011111;
if (swD) PB_in <= 8'b00101111;
if (swf) PB_in <= 8'b00110111;
end
if (phase == 3'b001 && PB_out[2:0] == 3'b110) begin
ch1 <= PA_out;
phase = 3'b010;
if (sw6) PB_in <= 8'b00011111;
if (swU) PB_in <= 8'b00101111;
if (swe) PB_in <= 8'b00110111;
end
if (phase == 3'b010 && PB_out[2:0] == 3'b101) begin
ch2 <= PA_out;
phase = 3'b011;
if (sw5) PB_in <= 8'b00011111;
if (swr) PB_in <= 8'b00101111;
if (swd) PB_in <= 8'b00110111;
end
if (phase == 3'b011 && PB_out[2:0] == 3'b100) begin
ch3 <= PA_out;
phase = 3'b100;
if (sw4) PB_in <= 8'b00011111;
if (swl) PB_in <= 8'b00101111;
if (swc) PB_in <= 8'b00110111;
end
if (phase == 3'b100 && PB_out[2:0] == 3'b011) begin
ch4 <= PA_out;
phase = 3'b101;
if (sw3) PB_in <= 8'b00011111;
if (sws) PB_in <= 8'b00101111;
if (swb) PB_in <= 8'b00110111;
end
if (phase == 3'b101 && PB_out[2:0] == 3'b010) begin
ch5 <= PA_out;
phase = 3'b110;
if (sw2) PB_in <= 8'b00011111;
if (swp) PB_in <= 8'b00101111;
if (swa) PB_in <= 8'b00110111;
end
if (phase == 3'b110 && PB_out[2:0] == 3'b001) begin
ch6 <= PA_out;
phase = 3'b111;
if (sw1) PB_in <= 8'b00011111;
if (swg) PB_in <= 8'b00101111;
if (sw9) PB_in <= 8'b00110111;
end
if (phase == 3'b111 && PB_out[2:0] == 3'b000) begin
ch7 <= PA_out;
phase = 3'b000;
if (sw0) PB_in <= 8'b00011111;
if (swm) PB_in <= 8'b00101111;
if (sw8) PB_in <= 8'b00110111;
end
end
m6522 VIA
(
.I_RS(address[3:0]),
.I_DATA(cpu_dout),
.O_DATA(via_dout),
.O_DATA_OE_L(),
.I_RW_L(rnw),
.I_CS1(via_cs),
.I_CS2_L(1'b0),
.O_IRQ_L(via_irq_n),
.I_CA1(1'b0),
.I_CA2(1'b0),
.O_CA2(),
.O_CA2_OE_L(),
.I_PA(8'b0),
.O_PA(PA_out),
.O_PA_OE_L(PA_oe),
.I_CB1(1'b0),
.O_CB1(),
.O_CB1_OE_L(),
.I_CB2(1'b0),
.O_CB2(),
.O_CB2_OE_L(),
.I_PB(PB_in),
.O_PB(PB_out),
.O_PB_OE_L(PB_oe),
.I_P2_H(via1_clken),
.RESET_L(!reset),
.ENA_4(via4_clken),
.CLK(clk25)
);
/*
wire [7:0] digit_0 = 8'h3F;
wire [7:0] digit_1 = 8'h06;
wire [7:0] digit_2 = 8'h5B;
wire [7:0] digit_3 = 8'h4F;
wire [7:0] digit_4 = 8'h66;
wire [7:0] digit_5 = 8'h6D;
wire [7:0] digit_6 = 8'h7D;
wire [7:0] digit_7 = 8'h07;
wire [7:0] digit_8 = 8'h7F;
wire [7:0] digit_9 = 8'h6F;
wire [7:0] digit_A = 8'h77;
wire [7:0] digit_B = 8'h7C;
wire [7:0] digit_C = 8'h58;
wire [7:0] digit_D = 8'h5E;
wire [7:0] digit_E = 8'h79;
wire [7:0] digit_F = 8'h71;
*/
endmodule

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module System1_MiST(
input CLOCK_27,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output LED,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0
);
`include "build_id.v"
localparam CONF_STR = {
"System1;;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire clk_sys;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire key_extended;
wire [8:0] mouse_x,mouse_y;
wire [7:0] mouse_flags;
wire [7:0] r, g, b;
wire hs, vs, hb, vb;
wire blankn = ~(hb | vb);
wire [1:0] buttons, switches;
wire ypbpr;
wire scandoublerD;
wire [31:0] status;
assign LED = 1'b1;
pll pll (
.inclk0 (CLOCK_27 ),
.c0 (clk_sys )//25
);
user_io #(
.STRLEN (($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_extended (key_extended ),
.key_code (key_code ),
.mouse_x (mouse_x ),
.mouse_y (mouse_y ),
.status (status )
);
mist_video #(.COLOR_DEPTH(6)) mist_video(
.clk_sys (clk_sys ),
.SPI_SCK (SPI_SCK ),
.SPI_SS3 (SPI_SS3 ),
.SPI_DI (SPI_DI ),
.R (blankn ? r[7:2] : 0),
.G (blankn ? g[7:2] : 0),
.B (blankn ? b[7:2] : 0),
.HSync (hs ),
.VSync (vs ),
.VGA_R (VGA_R ),
.VGA_G (VGA_G ),
.VGA_B (VGA_B ),
.VGA_VS (VGA_VS ),
.VGA_HS (VGA_HS ),
.scandoubler_disable(1'b1 ),
.ypbpr (ypbpr )
);
wire reset = (status[0] | status[6] | buttons[1]);
wire [8:0] ch0,ch1,ch2,ch3,ch4,ch5,ch6,ch7;
wire sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,sw8,sw9,swa,swb,swc,swd,swe,swf,swrst,swm,swl,swg,swr,swp,swUP,sws,swDW;
System1 System1(
.clk25(clk_sys),
.reset(reset),
.ch0(ch0),
.ch1(ch1),
.ch2(ch2),
.ch3(ch3),
.ch4(ch4),
.ch5(ch5),
.ch6(ch6),
.ch7(ch7),
.sw0(sw0 | tsw0),
.sw1(sw1 | tsw1),
.sw2(sw2 | tsw2),
.sw3(sw3 | tsw3),
.sw4(sw4 | tsw4),
.sw5(sw5 | tsw5),
.sw6(sw6 | tsw6),
.sw7(sw7 | tsw7),
.sw8(sw8 | tsw8),
.sw9(sw9 | tsw9),
.swa(swa | tswa),
.swb(swb | tswb),
.swc(swc | tswc),
.swd(swd | tswd),
.swe(swe | tswe),
.swf(swf | tswf),
.swrst(swrst | tswrst),
.swm(swm | tswm),
.swl(swl | tswl),
.swg(swg | tswg),
.swr(swr | tswr),
.swp(swp | tswp),
.swU(swUP | tswUP),
.sws(sws | tsws),
.swD(swDW | tswDW),
.cas_in(1'b0),
.cas_out()
);
vga vga(
.clk(clk_sys),
.rst(reset),
.mbtnL(mouse_flags[0]),
.mbtnR(mouse_flags[1]),
.mbtnM(mouse_flags[2]),
.mx(mouse_x),//mx),
.my(mouse_y),//my),
.ch0(ch0),
.ch1(ch1),
.ch2(ch2),
.ch3(ch3),
.ch4(ch4),
.ch5(ch5),
.ch6(ch6),
.ch7(ch7),
.osw0(sw0),
.osw1(sw1),
.osw2(sw2),
.osw3(sw3),
.osw4(sw4),
.osw5(sw5),
.osw6(sw6),
.osw7(sw7),
.osw8(sw8),
.osw9(sw9),
.oswa(swa),
.oswb(swb),
.oswc(swc),
.oswd(swd),
.oswe(swe),
.oswf(swf),
.oswrst(swrst),
.oswm(swm),
.oswl(swl),
.oswg(swg),
.oswr(swr),
.oswp(swp),
.oswU(swUP),
.osws(sws),
.oswD(swDW),
.r(r),
.g(g),
.b(b),
.hs(hs),
.vs(vs),
.hblank(hb),
.vblank(vb)
);
/*
wire [10:0] mx,my;
wire x1,y1,mbtnL,mbtnR,mbtnM;
ps2_mouse mouse
(
.clk(clk_sys),
.ce(1'b1),
.reset(reset),
.ps2_mouse(ps2_mouse),
.mx(mx),
.my(my),
.mbtnL(mbtnL),
.mbtnR(mbtnR),
.mbtnM(mbtnM)
);*/
/*
ps2_mouse #(
.clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
.ps2_debounce_counter_size : INTEGER := 8); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
MOUSE(
.clk : IN STD_LOGIC; --system clock input
.reset_n : IN STD_LOGIC; --active low asynchronous reset
.ps2_clk : INOUT STD_LOGIC; --clock signal from PS2 mouse
.ps2_data : INOUT STD_LOGIC; --data signal from PS2 mouse
.mouse_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); --data received from mouse
.mouse_data_new : OUT STD_LOGIC
);
*/
reg tsw0 = 1'b0;
reg tsw1 = 1'b0;
reg tsw2 = 1'b0;
reg tsw3 = 1'b0;
reg tsw4 = 1'b0;
reg tsw5 = 1'b0;
reg tsw6 = 1'b0;
reg tsw7 = 1'b0;
reg tsw8 = 1'b0;
reg tsw9 = 1'b0;
reg tswa = 1'b0;
reg tswb = 1'b0;
reg tswc = 1'b0;
reg tswd = 1'b0;
reg tswe = 1'b0;
reg tswf = 1'b0;
reg tswm = 1'b0;
reg tswl = 1'b0;
reg tswg = 1'b0;
reg tswr = 1'b0;
reg tswp = 1'b0;
reg tswUP = 1'b0;
reg tsws = 1'b0;
reg tswDW = 1'b0;
reg tswrst = 1'b0;
always @(posedge clk_sys) begin
reg old_state;
old_state <= key_strobe;
if(old_state != key_strobe) begin
casex(key_code)
'h75: tswUP <= key_pressed; // up
'h72: tswDW <= key_pressed; // down
'h45: tsw0 <= key_pressed; // 0
// 'h70: tsw0 <= key_pressed; // 0
'h16: tsw1 <= key_pressed; // 1
// 'h69: tsw1 <= key_pressed; // 1
'h1E: tsw2 <= key_pressed; // 2
// 'h72: tsw2 <= key_pressed; // 2
'h26: tsw3 <= key_pressed; // 3
// 'h7A: tsw3 <= key_pressed; // 3
'h25: tsw4 <= key_pressed; // 4
// 'h6B: tsw4 <= key_pressed; // 4
'h2E: tsw5 <= key_pressed; // 5
// 'h73: tsw5 <= key_pressed; // 5
'h36: tsw6 <= key_pressed; // 6
// 'h74: tsw6 <= key_pressed; // 6
'h3D: tsw7 <= key_pressed; // 7
// 'h6C: tsw7 <= key_pressed; // 7
'h3E: tsw8 <= key_pressed; // 8
// 'h75: tsw8 <= key_pressed; // 8
'h46: tsw9 <= key_pressed; // 9
// 'h7D: tsw9 <= key_pressed; // 9
'h1C: tswa <= key_pressed; // a
'h32: tswb <= key_pressed; // b
'h21: tswc <= key_pressed; // c
'h23: tswd <= key_pressed; // d
'h24: tswe <= key_pressed; // e
'h2B: tswf <= key_pressed; // f
'h3A: tswm <= key_pressed; // m
'h34: tswg <= key_pressed; // g
'h4D: tswp <= key_pressed; // p
'h1B: tsws <= key_pressed; // s
'h4B: tswl <= key_pressed; // l
'h2D: tswr <= key_pressed; // r
// 'h05: tswrst <= key_pressed; // F1
endcase
end
end
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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Computer_MiST/Acorn - System1/rtl/debounce.vhd Normal file
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--------------------------------------------------------------------------------
--
-- FileName: debounce.vhd
-- Dependencies: none
-- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 3/26/2012 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY debounce IS
GENERIC(
counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END debounce;
ARCHITECTURE logic OF debounce IS
SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set : STD_LOGIC; --sync reset to zero
SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output
BEGIN
counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter
PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops(0) <= button;
flipflops(1) <= flipflops(0);
If(counter_set = '1') THEN --reset counter because input is changing
counter_out <= (OTHERS => '0');
ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met
counter_out <= counter_out + 1;
ELSE --stable input time is met
result <= flipflops(1);
END IF;
END IF;
END PROCESS;
END logic;

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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
qReg <= ram(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
<pin name="c1" direction="output" scope="external" source="clock" />
</global>
</pinplan>

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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1);
input inclk0;
output c0;
output c1;
wire [4:0] sub_wire0;
wire [0:0] sub_wire5 = 1'h0;
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.inclk (sub_wire4),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 255,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 236,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 54,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 25,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "255"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "54"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.988235"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "236"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "255"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "236"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

78
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`timescale 1ns / 100ps
// Dave Wood (oldgit) 2019 code taken from muliple sources
// thanks to the original designers. I just glue bits together.
/*
* PS2 mouse protocol
* Bit 7 6 5 4 3 2 1 0
* Byte 0: YOVR XOVR YSGN XSGN 1 MBUT RBUT LBUT
* Byte 1: XMOVE
* Byte 2: YMOVE
*/
/*
* simple PS2 Mouse interface module
* starts with mouse pos(0,0) and keeps mouse location and updates. output is mouse pos(0--636/0--476) ! pos less 4 pixels for size
* mouse buttons 0 by default and 1 when pressed
*/
module ps2_mouse
(
input clk,
input ce,
input reset,
input [24:0] ps2_mouse,
output reg [10:0] mx, my,
output reg mbtnL,
output reg mbtnR,
output reg mbtnM
);
wire strobe = (old_stb != ps2_mouse[24]);
reg old_stb = 0;
always @(posedge clk) old_stb <= ps2_mouse[24];
/* Capture buttons state */
always@(posedge clk or posedge reset) begin
if (reset) begin
mbtnL <= 1'b0;
mbtnR <= 1'b0;
mbtnM <= 1'b0;
end else if (strobe) begin
mbtnL <= ps2_mouse[0];
mbtnR <= ps2_mouse[1];
mbtnM <= ps2_mouse[2];
end
end
// module parameters
parameter MAX_X = 635;
parameter MAX_Y = 475;
// low level mouse driver
wire [8:0] dx, dy;
// Update "absolute" position of mouse
wire sx = ps2_mouse[4]; // signs
wire sy = ps2_mouse[5];
wire [8:0] ndx = sx ? {1'b0,~ps2_mouse[15:8]}+9'b000000001 : {1'b0,ps2_mouse[15:8]}; // magnitudes
wire [8:0] ndy = sy ? {1'b0,~ps2_mouse[23:16]}+9'b000000001 : {1'b0,ps2_mouse[23:16]};
always @(posedge clk) begin
mx <= reset ? 0 :
strobe ? (sx ? (mx>ndx ? mx - ndx : 0)
: (mx < MAX_X - ndx ? mx+ndx : MAX_X)) : mx;
// note Y is flipped for video cursor use of mouse
my <= reset ? 0 :
strobe ? (sy ? (my < MAX_Y - ndy ? my+ndy : MAX_Y)
: (my>ndy ? my - ndy : 0)) : my;
// strobe ? (sy ? (my>ndy ? my - ndy : 0)
// : (my < MAX_Y - ndy ? my+ndy : MAX_Y)) : my;
end
endmodule

173
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@@ -0,0 +1,173 @@
--------------------------------------------------------------------------------
--
-- FileName: ps2_mouse.vhd
-- Dependencies: ps2_transceiver.vhd, debounce.vhd
-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 2/16/2018 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_mouse IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
ps2_debounce_counter_size : INTEGER := 8); --set such that 2^size/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock input
reset_n : IN STD_LOGIC; --active low asynchronous reset
ps2_clk : INOUT STD_LOGIC; --clock signal from PS2 mouse
ps2_data : INOUT STD_LOGIC; --data signal from PS2 mouse
mouse_data : OUT STD_LOGIC_VECTOR(23 DOWNTO 0); --data received from mouse
mouse_data_new : OUT STD_LOGIC); --new data packet available flag
END ps2_mouse;
ARCHITECTURE logic OF ps2_mouse IS
TYPE machine IS(reset, rx_ack1, rx_bat, rx_id, ena_reporting, rx_ack2, stream); --needed states
SIGNAL state : machine := reset; --state machine
SIGNAL tx_ena : STD_LOGIC := '0'; --transmit enable for ps2_transceiver
SIGNAL tx_cmd : STD_LOGIC_VECTOR(8 DOWNTO 0); --command to transmit
SIGNAL tx_busy : STD_LOGIC; --ps2_transceiver busy signal
SIGNAL ps2_code : STD_LOGIC_VECTOR(7 DOWNTO 0); --PS/2 code received from ps2_transceiver
SIGNAL ps2_code_new : STD_LOGIC; --new PS/2 code available flag from ps2_transceiver
SIGNAL ps2_code_new_prev : STD_LOGIC; --previous value of ps2_code_new
SIGNAL packet_byte : INTEGER RANGE 0 TO 2 := 2; --counter to track which packet byte is being received
SIGNAL mouse_data_int : STD_LOGIC_VECTOR(23 DOWNTO 0); --internal mouse data register
--component to control PS/2 bus interface to the mouse
COMPONENT ps2_transceiver IS
GENERIC(
clk_freq : INTEGER; --system clock frequency in Hz
debounce_counter_size : INTEGER); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low asynchronous reset
tx_ena : IN STD_LOGIC; --enable transmit
tx_cmd : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --8-bit command to transmit, MSB is parity bit
tx_busy : OUT STD_LOGIC; --indicates transmit in progress
ack_error : OUT STD_LOGIC; --device acknowledge from transmit, '1' is error
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --code received from PS/2 bus
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
rx_error : OUT STD_LOGIC; --start, stop, or parity receive error detected, '1' is error
ps2_clk : INOUT STD_LOGIC; --PS/2 port clock signal
ps2_data : INOUT STD_LOGIC); --PS/2 port data signal
END COMPONENT;
BEGIN
--PS/2 transceiver to control transactions with mouse
ps2_transceiver_0: ps2_transceiver
GENERIC MAP(clk_freq => clk_freq, debounce_counter_size => ps2_debounce_counter_size)
PORT MAP(clk => clk, reset_n => reset_n, tx_ena => tx_ena, tx_cmd => tx_cmd, tx_busy => tx_busy, ack_error => OPEN,
ps2_code => ps2_code, ps2_code_new => ps2_code_new, rx_error => OPEN, ps2_clk => ps2_clk, ps2_data => ps2_data);
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
mouse_data_new <= '0'; --clear new mouse data available flag
mouse_data <= (OTHERS => '0'); --clear last mouse data packet received
state <= reset; --set state machine to reset the mouse
ELSIF(clk'EVENT AND clk = '1') THEN
ps2_code_new_prev <= ps2_code_new; --store previous value of the new PS/2 code flag
CASE state IS
WHEN reset =>
IF(tx_busy = '0') THEN --transmit to mouse not yet in process
tx_ena <= '1'; --enable transmit to PS/2 mouse
tx_cmd <= "111111111"; --send reset command (0xFF)
state <= reset; --remain in reset state
ELSIF(tx_busy = '1') THEN --transmit to mouse is in process
tx_ena <= '0'; --clear transmit enable
state <= rx_ack1; --wait to receive an acknowledge from mouse
END IF;
WHEN rx_ack1 =>
IF(ps2_code_new_prev = '0' AND ps2_code_new = '1') THEN --new PS/2 code received
IF(ps2_code = "11111010") THEN --new PS/2 code is acknowledge (0xFA)
state <= rx_bat; --wait to receive new BAT completion code
ELSE --new PS/2 code was not an acknowledge
state <= reset; --reset mouse again
END IF;
ELSE --new PS/2 code not yet received
state <= rx_ack1; --wait to receive a code from mouse
END IF;
WHEN rx_bat =>
IF(ps2_code_new_prev = '0' AND ps2_code_new = '1') THEN --new PS/2 code received
IF(ps2_code = "10101010") THEN --new PS/2 code is BAT completion (0xAA)
state <= rx_id; --wait to receive device ID code
ELSE --new PS/2 code was not BAT completion
state <= reset; --reset mouse again
END IF;
ELSE --new PS/2 code not yet received
state <= rx_bat; --wait to receive a code from mouse
END IF;
WHEN rx_id =>
IF(ps2_code_new_prev = '0' AND ps2_code_new = '1') THEN --new PS/2 code received
IF(ps2_code = "00000000") THEN --new PS/2 code is a mouse device ID (0x00)
state <= ena_reporting; --send command to enable data reporting
ELSE --new PS/2 code is not a mouse device ID
state <= reset; --reset mouse again
END IF;
ELSE --new PS/2 code not yet received
state <= rx_id; --wait to receive a code from mouse
END IF;
WHEN ena_reporting =>
IF(tx_busy = '0') THEN --transmit to mouse not yet in process
tx_ena <= '1'; --enable transmit to PS/2 mouse
tx_cmd <= "011110100"; --send enable reporting command (0xF4)
state <= ena_reporting; --remain in ena_reporting state
ELSIF(tx_busy = '1') THEN --transmit to mouse is in process
tx_ena <= '0'; --clear transmit enable
state <= rx_ack2; --wait to receive an acknowledge from mouse
END IF;
WHEN rx_ack2 =>
IF(ps2_code_new_prev = '0' AND ps2_code_new = '1') THEN --new PS/2 code received
IF(ps2_code = "11111010") THEN --new PS/2 code is acknowledge (0xFA)
state <= stream; --proceed to collect and output data from mouse
ELSE --new PS/2 code was not an acknowledge
state <= reset; --reset mouse again
END IF;
ELSE --new PS/2 code not yet received
state <= rx_ack2; --wait to receive a code from mouse
END IF;
WHEN stream =>
IF(ps2_code_new_prev = '0' AND ps2_code_new = '1') THEN --new PS/2 code received
mouse_data_new <= '0'; --clear new data packet available flag
mouse_data_int(7+packet_byte*8 DOWNTO packet_byte*8) <= ps2_code; --store new mouse data byte
IF(packet_byte = 0) THEN --all bytes in packet received and presented
packet_byte <= 2; --clear packet byte counter
ELSE --not all bytes in packet received yet
packet_byte <= packet_byte - 1; --increment packet byte counter
END IF;
END IF;
IF(ps2_code_new_prev = '1' AND ps2_code_new = '1' AND packet_byte = 2) THEN --mouse data receive is complete
mouse_data <= mouse_data_int; --present new mouse data at output
mouse_data_new <= '1'; --set new data packet available flag
END IF;
END CASE;
END IF;
END PROCESS;
END logic;

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--------------------------------------------------------------------------------
--
-- FileName: ps2_transceiver.vhd
-- Dependencies: debounce.vhd
-- Design Software: Quartus II 64-bit Version 13.1.0 Build 162 SJ Web Edition
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 1/19/2018 Scott Larson
-- Initial Public Release
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ps2_transceiver IS
GENERIC(
clk_freq : INTEGER := 50_000_000; --system clock frequency in Hz
debounce_counter_size : INTEGER := 8); --set such that (2^size)/clk_freq = 5us (size = 8 for 50MHz)
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low asynchronous reset
tx_ena : IN STD_LOGIC; --enable transmit
tx_cmd : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --8-bit command to transmit, MSB is parity bit
tx_busy : OUT STD_LOGIC; --indicates transmit in progress
ack_error : OUT STD_LOGIC; --device acknowledge from transmit, '1' is error
ps2_code : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --code received from PS/2
ps2_code_new : OUT STD_LOGIC; --flag that new PS/2 code is available on ps2_code bus
rx_error : OUT STD_LOGIC; --start, stop, or parity receive error detected, '1' is error
ps2_clk : INOUT STD_LOGIC; --PS/2 port clock signal
ps2_data : INOUT STD_LOGIC); --PS/2 port data signal
END ps2_transceiver;
ARCHITECTURE logic OF ps2_transceiver IS
TYPE machine IS(receive, inhibit, transact, tx_complete); --needed states
SIGNAL state : machine := receive; --state machine
SIGNAL sync_ffs : STD_LOGIC_VECTOR(1 DOWNTO 0); --synchronizer flip-flops for PS/2 signals
SIGNAL ps2_clk_int : STD_LOGIC; --debounced input clock signal from PS/2 port
SIGNAL ps2_clk_int_prev : STD_LOGIC; --previous state of the ps2_clk_int signal
SIGNAL ps2_data_int : STD_LOGIC; --debounced input data signal from PS/2 port
SIGNAL ps2_word : STD_LOGIC_VECTOR(10 DOWNTO 0); --stores the ps2 data word (both tx and rx)
SIGNAL error : STD_LOGIC; --validate parity, start, and stop bits for received data
SIGNAL timer : INTEGER RANGE 0 TO clk_freq/10_000 := 0; --counter to determine both inhibit period and when PS/2 is idle
SIGNAL bit_cnt : INTEGER RANGE 0 TO 11 := 0; --count the number of clock pulses during transmit
--declare debounce component for debouncing PS2 input signals
COMPONENT debounce IS
GENERIC(
counter_size : INTEGER); --debounce period (in seconds) = 2^counter_size/(clk freq in Hz)
PORT(
clk : IN STD_LOGIC; --input clock
button : IN STD_LOGIC; --input signal to be debounced
result : OUT STD_LOGIC); --debounced signal
END COMPONENT;
BEGIN
--synchronizer flip-flops
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
sync_ffs(0) <= ps2_clk; --synchronize PS/2 clock signal
sync_ffs(1) <= ps2_data; --synchronize PS/2 data signal
END IF;
END PROCESS;
--debounce PS2 input signals
debounce_ps2_clk: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(0), result => ps2_clk_int);
debounce_ps2_data: debounce
GENERIC MAP(counter_size => debounce_counter_size)
PORT MAP(clk => clk, button => sync_ffs(1), result => ps2_data_int);
--verify that parity, start, and stop bits are all correct for received data
error <= NOT (NOT ps2_word(0) AND ps2_word(10) AND (ps2_word(9) XOR ps2_word(8) XOR
ps2_word(7) XOR ps2_word(6) XOR ps2_word(5) XOR ps2_word(4) XOR ps2_word(3) XOR
ps2_word(2) XOR ps2_word(1)));
--state machine to control transmit and receive processes
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset PS/2 transceiver
ps2_clk <= '0'; --inhibit communication on PS/2 bus
ps2_data <= 'Z'; --release PS/2 data line
tx_busy <= '1'; --indicate that no transmit is in progress
ack_error <= '0'; --clear acknowledge error flag
ps2_code <= (OTHERS => '0'); --clear received PS/2 code
ps2_code_new <= '0'; --clear new received PS/2 code flag
rx_error <= '0'; --clear receive error flag
state <= receive; --set state machine to receive state
ELSIF(clk'EVENT AND clk = '1') THEN --rising edge of system clock
ps2_clk_int_prev <= ps2_clk_int; --store previous value of the PS/2 clock signal
CASE state IS --implement state machine
WHEN receive =>
IF(tx_ena = '1') THEN --transmit requested
tx_busy <= '1'; --indicate transmit in progress
timer <= 0; --reset timer for inhibit timing
ps2_word(9 DOWNTO 0) <= tx_cmd & '0'; --load parity, command, and start bit into PS/2 data buffer
bit_cnt <= 0; --clear bit counter
state <= inhibit; --inhibit communication to begin transaction
ELSE --transmit not requested
tx_busy <= '0'; --indicate no transmit in progress
ps2_clk <= 'Z'; --release PS/2 clock port
ps2_data <= 'Z'; --release PS/2 data port
--clock in receive data
IF(ps2_clk_int_prev = '1' AND ps2_clk_int = '0') THEN --falling edge of PS2 clock
ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift contents of PS/2 data buffer
END IF;
--determine if PS/2 port is idle
IF(ps2_clk_int = '0') THEN --low PS2 clock, PS/2 is active
timer <= 0; --reset idle counter
ELSIF(timer < clk_freq/18_000) THEN --PS2 clock has been high less than a half clock period (<55us)
timer <= timer + 1; --continue counting
END IF;
--output received data and port status
IF(timer = clk_freq/18_000) THEN --idle threshold reached
IF(error = '0') THEN --no error detected
ps2_code_new <= '1'; --set flag that new PS/2 code is available
ps2_code <= ps2_word(8 DOWNTO 1); --output new PS/2 code
ELSIF(error = '1') THEN --error detected
rx_error <= '1'; --set receive error flag
END IF;
ELSE --PS/2 port active
rx_error <= '0'; --clear receive error flag
ps2_code_new <= '0'; --set flag that PS/2 transaction is in progress
END IF;
state <= receive; --continue streaming receive transactions
END IF;
WHEN inhibit =>
IF(timer < clk_freq/10_000) THEN --first 100us not complete
timer <= timer + 1; --increment timer
ps2_data <= 'Z'; --release data port
ps2_clk <= '0'; --inhibit communication
state <= inhibit; --continue inhibit
ELSE --100us complete
ps2_data <= ps2_word(0); --output start bit to PS/2 data port
state <= transact; --proceed to send bits
END IF;
WHEN transact =>
ps2_clk <= 'Z'; --release clock port
IF(ps2_clk_int_prev = '1' AND ps2_clk_int = '0') THEN --falling edge of PS2 clock
ps2_word <= ps2_data_int & ps2_word(10 DOWNTO 1); --shift contents of PS/2 data buffer
bit_cnt <= bit_cnt + 1; --count clock falling edges
END IF;
IF(bit_cnt < 10) THEN --all bits not sent
ps2_data <= ps2_word(0); --connect serial output of PS/2 data buffer to data port
ELSE --all bits sent
ps2_data <= 'Z'; --release data port
END IF;
IF(bit_cnt = 11) THEN --acknowledge bit received
ack_error <= ps2_data_int; --set error flag if acknowledge is not '0'
state <= tx_complete; --proceed to wait until the slave releases the bus
ELSE --acknowledge bit not received
state <= transact; --continue transaction
END IF;
WHEN tx_complete =>
IF(ps2_clk_int = '1' AND ps2_data_int = '1') THEN --device has released the bus
state <= receive; --proceed to receive data state
ELSE --bus not released by device
state <= tx_complete; --wait for device to release bus
END IF;
END CASE;
END IF;
END PROCESS;
END logic;

53
Computer_MiST/Acorn - System1/rtl/roms/ONE.mif Normal file
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-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec -o --mif
--
DEPTH = 1024;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0018: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0048: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0078: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00A8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00D8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0108: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0138: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0168: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0180: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0198: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
01B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
01C8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
01E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
01F8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0210: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0228: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0258: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0270: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0288: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
02A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
02B8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
02D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
02E8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0300: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0318: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0330: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0348: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0378: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
0390: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
03A8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
03C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
03D8: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
03F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00;
END;

BIN
Computer_MiST/Acorn - System1/rtl/roms/acrnsys1.bin Normal file
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54
Computer_MiST/Acorn - System1/rtl/roms/acrnsys1.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity acrnsys1 is
port (
clk : in std_logic;
addr : in std_logic_vector(8 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of acrnsys1 is
type rom is array(0 to 511) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"A0",X"06",X"B5",X"00",X"20",X"6F",X"FE",X"CA",X"88",X"88",X"10",X"F6",X"86",X"1A",X"A2",X"07",
X"8E",X"22",X"0E",X"A0",X"00",X"B5",X"10",X"8D",X"21",X"0E",X"8E",X"20",X"0E",X"AD",X"20",X"0E",
X"29",X"3F",X"24",X"0F",X"10",X"18",X"C9",X"38",X"B0",X"06",X"86",X"19",X"A9",X"40",X"85",X"0F",
X"A1",X"00",X"88",X"D0",X"FB",X"CA",X"10",X"DB",X"A5",X"0E",X"30",X"D2",X"10",X"14",X"E4",X"19",
X"D0",X"EE",X"C9",X"38",X"90",X"04",X"A9",X"80",X"D0",X"E4",X"C5",X"0F",X"F0",X"E2",X"85",X"0F",
X"49",X"38",X"29",X"1F",X"C9",X"10",X"85",X"0D",X"A6",X"1A",X"8C",X"21",X"0E",X"60",X"A1",X"00",
X"A0",X"06",X"D0",X"0B",X"A0",X"03",X"B5",X"00",X"20",X"6F",X"FE",X"88",X"88",X"B5",X"01",X"C8",
X"48",X"20",X"7A",X"FE",X"88",X"68",X"4A",X"4A",X"4A",X"4A",X"84",X"1A",X"29",X"0F",X"A8",X"B9",
X"EA",X"FF",X"A4",X"1A",X"99",X"10",X"00",X"60",X"20",X"64",X"FE",X"20",X"0C",X"FE",X"B0",X"20",
X"A0",X"04",X"0A",X"0A",X"0A",X"0A",X"0A",X"36",X"00",X"36",X"01",X"88",X"D0",X"F8",X"F0",X"E8",
X"F6",X"06",X"D0",X"02",X"F6",X"07",X"B5",X"06",X"D5",X"08",X"D0",X"04",X"B5",X"07",X"D5",X"09",
X"60",X"A0",X"40",X"8C",X"22",X"0E",X"A0",X"07",X"8C",X"20",X"0E",X"6A",X"6A",X"20",X"CD",X"FE",
X"6A",X"8D",X"20",X"0E",X"88",X"10",X"F6",X"20",X"CD",X"FE",X"8C",X"20",X"0E",X"20",X"D0",X"FE",
X"84",X"1A",X"A0",X"48",X"88",X"D0",X"FD",X"88",X"D0",X"FD",X"A4",X"1A",X"60",X"A0",X"08",X"2C",
X"20",X"0E",X"30",X"FB",X"20",X"D0",X"FE",X"20",X"CD",X"FE",X"0E",X"20",X"0E",X"6A",X"88",X"D0",
X"F6",X"F0",X"DA",X"A2",X"FF",X"9A",X"8E",X"23",X"0E",X"86",X"0E",X"A0",X"80",X"A2",X"09",X"94",
X"0E",X"CA",X"D0",X"FB",X"20",X"0C",X"FE",X"90",X"F2",X"29",X"07",X"C9",X"04",X"90",X"25",X"F0",
X"6F",X"C9",X"06",X"F0",X"09",X"B0",X"0F",X"A5",X"0A",X"A6",X"0B",X"A4",X"0C",X"40",X"F6",X"00",
X"D0",X"0C",X"F6",X"01",X"B0",X"08",X"B5",X"00",X"D0",X"02",X"D6",X"01",X"D6",X"00",X"20",X"64",
X"FE",X"4C",X"45",X"FF",X"84",X"16",X"84",X"17",X"0A",X"AA",X"49",X"F7",X"85",X"10",X"20",X"88",
X"FE",X"E0",X"02",X"B0",X"15",X"20",X"5E",X"FE",X"20",X"0C",X"FE",X"B0",X"BC",X"A1",X"00",X"0A",
X"0A",X"0A",X"0A",X"05",X"0D",X"81",X"00",X"4C",X"45",X"FF",X"D0",X"03",X"6C",X"02",X"00",X"E0",
X"04",X"F0",X"36",X"A2",X"08",X"86",X"10",X"20",X"88",X"FE",X"A2",X"04",X"B5",X"05",X"20",X"B1",
X"FE",X"CA",X"D0",X"F8",X"A1",X"06",X"20",X"B1",X"FE",X"20",X"A0",X"FE",X"D0",X"F6",X"F0",X"2A",
X"A2",X"04",X"20",X"DD",X"FE",X"95",X"05",X"CA",X"D0",X"F8",X"20",X"DD",X"FE",X"81",X"06",X"8D",
X"21",X"0E",X"20",X"A0",X"FE",X"D0",X"F3",X"F0",X"11",X"A1",X"00",X"F0",X"06",X"85",X"18",X"A9",
X"00",X"F0",X"02",X"A5",X"18",X"81",X"00",X"20",X"5E",X"FE",X"4C",X"04",X"FF",X"6C",X"1C",X"00",
X"6C",X"1E",X"00",X"85",X"0A",X"86",X"0B",X"84",X"0C",X"68",X"48",X"85",X"0D",X"A2",X"0D",X"A9",
X"FF",X"85",X"0E",X"20",X"00",X"FE",X"BA",X"86",X"13",X"C8",X"84",X"12",X"D8",X"BD",X"02",X"01",
X"38",X"E5",X"1B",X"9D",X"02",X"01",X"85",X"11",X"BD",X"03",X"01",X"E9",X"00",X"9D",X"03",X"01",
X"85",X"10",X"A2",X"13",X"20",X"00",X"FE",X"4C",X"07",X"FF",X"3F",X"06",X"5B",X"4F",X"66",X"6D",
X"7D",X"07",X"7F",X"6F",X"77",X"7C",X"58",X"5E",X"79",X"71",X"AD",X"FF",X"F3",X"FE",X"B0",X"FF");
begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

32
Computer_MiST/Acorn - System1/rtl/roms/monitor.mif Normal file
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-- http://srecord.sourceforge.net/
--
-- Generated automatically by srec -o --mif
--
DEPTH = 512;
WIDTH = 8;
ADDRESS_RADIX = HEX;
DATA_RADIX = HEX;
CONTENT BEGIN
0000: A0 06 B5 00 20 6F FE CA 88 88 10 F6 86 1A A2 07 8E 22 0E A0 00 B5 10 8D;
0018: 21 0E 8E 20 0E AD 20 0E 29 3F 24 0F 10 18 C9 38 B0 06 86 19 A9 40 85 0F;
0030: A1 00 88 D0 FB CA 10 DB A5 0E 30 D2 10 14 E4 19 D0 EE C9 38 90 04 A9 80;
0048: D0 E4 C5 0F F0 E2 85 0F 49 38 29 1F C9 10 85 0D A6 1A 8C 21 0E 60 A1 00;
0060: A0 06 D0 0B A0 03 B5 00 20 6F FE 88 88 B5 01 C8 48 20 7A FE 88 68 4A 4A;
0078: 4A 4A 84 1A 29 0F A8 B9 EA FF A4 1A 99 10 00 60 20 64 FE 20 0C FE B0 20;
0090: A0 04 0A 0A 0A 0A 0A 36 00 36 01 88 D0 F8 F0 E8 F6 06 D0 02 F6 07 B5 06;
00A8: D5 08 D0 04 B5 07 D5 09 60 A0 40 8C 22 0E A0 07 8C 20 0E 6A 6A 20 CD FE;
00C0: 6A 8D 20 0E 88 10 F6 20 CD FE 8C 20 0E 20 D0 FE 84 1A A0 48 88 D0 FD 88;
00D8: D0 FD A4 1A 60 A0 08 2C 20 0E 30 FB 20 D0 FE 20 CD FE 0E 20 0E 6A 88 D0;
00F0: F6 F0 DA A2 FF 9A 8E 23 0E 86 0E A0 80 A2 09 94 0E CA D0 FB 20 0C FE 90;
0108: F2 29 07 C9 04 90 25 F0 6F C9 06 F0 09 B0 0F A5 0A A6 0B A4 0C 40 F6 00;
0120: D0 0C F6 01 B0 08 B5 00 D0 02 D6 01 D6 00 20 64 FE 4C 45 FF 84 16 84 17;
0138: 0A AA 49 F7 85 10 20 88 FE E0 02 B0 15 20 5E FE 20 0C FE B0 BC A1 00 0A;
0150: 0A 0A 0A 05 0D 81 00 4C 45 FF D0 03 6C 02 00 E0 04 F0 36 A2 08 86 10 20;
0168: 88 FE A2 04 B5 05 20 B1 FE CA D0 F8 A1 06 20 B1 FE 20 A0 FE D0 F6 F0 2A;
0180: A2 04 20 DD FE 95 05 CA D0 F8 20 DD FE 81 06 8D 21 0E 20 A0 FE D0 F3 F0;
0198: 11 A1 00 F0 06 85 18 A9 00 F0 02 A5 18 81 00 20 5E FE 4C 04 FF 6C 1C 00;
01B0: 6C 1E 00 85 0A 86 0B 84 0C 68 48 85 0D A2 0D A9 FF 85 0E 20 00 FE BA 86;
01C8: 13 C8 84 12 D8 BD 02 01 38 E5 1B 9D 02 01 85 11 BD 03 01 E9 00 9D 03 01;
01E0: 85 10 A2 13 20 00 FE 4C 07 FF 3F 06 5B 4F 66 6D 7D 07 7F 6F 77 7C 58 5E;
01F8: 79 71 AD FF F3 FE B0 FF;
END;

1638
Computer_MiST/Acorn - System1/rtl/vga.v Normal file
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