github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-29 13:01:00 +00:00
Code Issues Releases Wiki Activity

add Irem M58 Project Files

Browse Source
This commit is contained in:
Gehstock
2020-04-09 22:56:40 +02:00
parent e757094287
commit ca65d33352
15 changed files with 3511 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/TenYardFight_MiST.qpf Normal file
View File

@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 18:28:29 January 01, 2020
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "18:28:29 January 01, 2020"
# Revisions
PROJECT_REVISION = "TenYardFight_MiST"

241
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/TenYardFight_MiST.qsf Normal file
View File

@@ -0,0 +1,241 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 22:53:52 April 09, 2020
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TenYardFight_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:22:13 JUNE 04, 2019"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TenYardFight_MiST.sv
set_global_assignment -name VHDL_FILE rtl/TenYardFight.vhd
set_global_assignment -name VHDL_FILE rtl/Sound_Board.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VHDL_FILE rtl/pll_mist.vhd
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
set_global_assignment -name QIP_FILE ../../../common/CPU/T80/T80.qip
set_global_assignment -name VHDL_FILE ../../../common/CPU/6800/cpu68.vhd
set_global_assignment -name QIP_FILE ../../../common/Sound/jt5205/jt5205.qip
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY TenYardFight_MiST
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/trop.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -------------------------------
# start ENTITY(TenYardFight_MiST)
# Pin & Location Assignments
# ==========================
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
# Fitter Assignments
# ==================
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TenYardFight_MiST)
# -----------------------------

135
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/TenYardFight_MiST.sdc Normal file
View File

@@ -0,0 +1,135 @@
## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
set_false_path -to [get_ports {SDRAM_CLK}]
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -setup 2
set_multicycle_path -from [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {pll|altpll_component|auto_generated|pll1|clk[2]}] -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

15
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/clean.bat Normal file
View File

@@ -0,0 +1,15 @@
@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

392
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/Sound_Board.vhd Normal file
View File

@@ -0,0 +1,392 @@
---------------------------------------------------------------------------------
-- Irem M62 sound board, based on
-- Moon patrol sound board by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- cpu68 - Version 9th Jan 2004 0.8
-- 6800/01 compatible CPU core
-- GNU public license - December 2002 : John E. Kent
---------------------------------------------------------------------------------
-- jt5205 hardware by Jose Tejada (@topapate)
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Version 0.0 -- 24/11/2017 --
-- initial version
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity Sound_Board is
port(
clock_E : in std_logic; -- 3.58 Mhz/4
areset : in std_logic;
select_sound : in std_logic_vector(7 downto 0);
audio_out : out std_logic_vector(11 downto 0);
snd_rom_addr : out std_logic_vector(14 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
snd_vma : out std_logic;
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end Sound_Board;
architecture struct of Sound_Board is
component YM2149
port (
CLK : in std_logic;
CE : in std_logic;
RESET : in std_logic;
A8 : in std_logic := '1';
A9_L : in std_logic := '0';
BDIR : in std_logic; -- Bus Direction (0 - read , 1 - write)
BC : in std_logic; -- Bus control
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
CHANNEL_A : out std_logic_vector(7 downto 0);
CHANNEL_B : out std_logic_vector(7 downto 0);
CHANNEL_C : out std_logic_vector(7 downto 0);
SEL : in std_logic;
MODE : in std_logic;
ACTIVE : out std_logic_vector(5 downto 0);
IOA_in : in std_logic_vector(7 downto 0);
IOA_out : out std_logic_vector(7 downto 0);
IOB_in : in std_logic_vector(7 downto 0);
IOB_out : out std_logic_vector(7 downto 0)
);
end component;
component jt5205
port (
rst : in std_logic;
clk : in std_logic;
cen : in std_logic;
sel : in std_logic_vector(1 downto 0); -- s pin
din : in std_logic_vector(3 downto 0);
sound : out signed(11 downto 0);
irq : out std_logic;
vclk_o : out std_logic
);
end component;
signal reset : std_logic := '1';
signal reset_cnt : integer range 0 to 1000000 := 1000000;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_rw : std_logic;
signal cpu_irq : std_logic;
signal cpu_nmi : std_logic;
signal cpu_vma : std_logic;
signal irqraz_cs : std_logic;
signal irqraz_we : std_logic;
signal wram_cs : std_logic;
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal rom_cs : std_logic;
signal rom_do : std_logic_vector( 7 downto 0);
signal rom_addr : std_logic_vector(15 downto 0);
signal ay1_chan_a : std_logic_vector(7 downto 0);
signal ay1_chan_b : std_logic_vector(7 downto 0);
signal ay1_chan_c : std_logic_vector(7 downto 0);
signal ay1_do : std_logic_vector(7 downto 0);
signal ay1_audio : std_logic_vector(9 downto 0);
signal ay1_port_b_do : std_logic_vector(7 downto 0);
signal ay2_chan_a : std_logic_vector(7 downto 0);
signal ay2_chan_b : std_logic_vector(7 downto 0);
signal ay2_chan_c : std_logic_vector(7 downto 0);
signal ay2_do : std_logic_vector(7 downto 0);
signal ay2_audio : std_logic_vector(9 downto 0);
signal ports_cs : std_logic;
signal ports_we : std_logic;
signal port1_bus : std_logic_vector(7 downto 0);
signal port1_data : std_logic_vector(7 downto 0);
signal port1_ddr : std_logic_vector(7 downto 0);
signal port1_in : std_logic_vector(7 downto 0);
signal port2_bus : std_logic_vector(7 downto 0);
signal port2_data : std_logic_vector(7 downto 0);
signal port2_ddr : std_logic_vector(7 downto 0);
signal port2_in : std_logic_vector(7 downto 0);
signal adpcm_ce : std_logic;
signal adpcm_cs : std_logic;
signal adpcm_0_we : std_logic;
signal adpcm_1_we : std_logic;
signal adpcm_0_di : std_logic_vector(3 downto 0);
signal adpcm_1_di : std_logic_vector(3 downto 0);
signal select_sound_r : std_logic_vector(7 downto 0);
signal adpcm_0_out : signed(11 downto 0);
signal adpcm_1_out : signed(11 downto 0);
signal adpcm_vclk : std_logic;
signal audio : std_logic_vector(12 downto 0);
begin
dbg_cpu_addr <= cpu_addr;
-- cs
wram_cs <= '1' when cpu_addr(15 downto 7) = X"00"&'1' else '0'; -- 0080-00FF
ports_cs <= '1' when cpu_addr(15 downto 4) = X"000" else '0'; -- 0000-000F
adpcm_cs <= '1' when cpu_addr(15 downto 14) = "00" and cpu_addr(11) = '1' and cpu_addr(1 downto 0) /= "00" else '0'; -- 0801-0802
irqraz_cs <= '1' when cpu_addr(15 downto 14) = "00" and cpu_addr(11) = '1' and cpu_addr(1 downto 0) = "00" else '0'; -- 0800
rom_cs <= '1' when cpu_addr(15 downto 14) >= "01" else '0'; -- 8000-FFFF
-- write enables
wram_we <= '1' when cpu_rw = '0' and wram_cs = '1' else '0';
ports_we <= '1' when cpu_rw = '0' and ports_cs = '1' else '0';
adpcm_0_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' and cpu_addr(0) = '1' else '0';
adpcm_1_we <= '1' when cpu_rw = '0' and adpcm_cs = '1' and cpu_addr(1) = '1' else '0';
irqraz_we <= '1' when cpu_rw = '0' and irqraz_cs = '1' else '0';
-- mux cpu in data between roms/io/wram
cpu_di <=
wram_do when wram_cs = '1' else
port1_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"0" else
port2_ddr when ports_cs = '1' and cpu_addr(3 downto 0) = X"1" else
port1_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"2" else
port2_in when ports_cs = '1' and cpu_addr(3 downto 0) = X"3" else
snd_rom_do when rom_cs = '1' else X"55";
process (clock_E)
begin
if rising_edge(clock_E) then
reset <= '0';
if reset_cnt /= 0 then
reset_cnt <= reset_cnt - 1;
reset <= '1';
end if;
if areset = '1' then
reset_cnt <= 1000000;
end if;
end if;
end process;
-- irq to cpu
process (reset, clock_E)
begin
if reset='1' then
cpu_irq <= '0';
select_sound_r(7) <= '0';
elsif rising_edge(clock_E) then
select_sound_r <= select_sound;
if select_sound_r(7) = '0' then
cpu_irq <= '1';
end if;
if irqraz_we = '1' then
cpu_irq <= '0';
end if;
end if;
end process;
-- cpu nmi
cpu_nmi <= adpcm_vclk;
-- 6803 ports 1 and 2 (only)
process (reset, clock_E)
begin
if reset='1' then
port1_ddr <= (others=>'0'); -- port1 set as input
port1_data <= (others=>'0'); -- port1 data set to 0
port2_ddr <= ("11100000"); -- port2 bit 7 to 5 should always remain output to simulate mode data
port2_data <= ("01000000"); -- port2 data bit 7 to 5 set to 2 (for mode 2 at start up)
elsif rising_edge(clock_E) then
if ports_cs = '1' and ports_we = '1' then
if cpu_addr(3 downto 0) = X"0" then port1_ddr <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"1" then port2_ddr <= cpu_do and "11100000"; end if;
if cpu_addr(3 downto 0) = X"2" then port1_data <= cpu_do; end if;
if cpu_addr(3 downto 0) = X"3" then port2_data <= cpu_do; end if;
end if;
end if;
end process;
port1_in <= (port1_bus and not(port1_ddr)) or (port1_data and port1_ddr);
port2_in <= (port2_bus and not(port2_ddr)) or (port2_data and port2_ddr);
-- port1 bus mux
port1_bus <= ay1_do when port2_data(4) = '0' else
ay2_do when port2_data(3) = '0' else X"FF";
-- port2 bus
port2_bus <= X"FF";
-- latch adpcm (msm5205) data in
process (reset, clock_E)
begin
if reset='1' then
adpcm_0_di <= (others=>'0');
elsif rising_edge(clock_E) then
if adpcm_cs = '1' and adpcm_0_we = '1' then
adpcm_0_di <= cpu_do(3 downto 0);
end if;
if adpcm_cs = '1' and adpcm_1_we = '1' then
adpcm_1_di <= cpu_do(3 downto 0);
end if;
end if;
end process;
-- 384 kHz clock enable
process( reset, clock_E )
variable CLK_SUM : integer;
begin
if reset = '1' then
CLK_SUM := 0;
adpcm_ce <= '0';
elsif rising_edge(clock_E) then
adpcm_ce <= '0';
CLK_SUM := CLK_SUM + 384;
if CLK_SUM >= 895 then
CLK_SUM := CLK_SUM - 895;
adpcm_ce <= '1';
end if;
end if;
end process;
-- MSM5205 ADPCM decoder chips
adpcm_0 : jt5205
port map (
rst => ay1_port_b_do(0),
clk => clock_E,
cen => adpcm_ce,
sel => ay1_port_b_do(3 downto 2),
din => adpcm_0_di,
sound => adpcm_0_out,
irq => open,
vclk_o=> adpcm_vclk
);
adpcm_1 : jt5205
port map (
rst => ay1_port_b_do(1),
clk => clock_E,
cen => adpcm_ce,
sel => ay1_port_b_do(3 downto 2),
din => adpcm_1_di,
sound => adpcm_1_out,
irq => open,
vclk_o=> open
);
-- audio mux
audio <= ("00"&ay1_audio&'0') + ("00"&ay2_audio&'0') + std_logic_vector(not adpcm_0_out(11)&adpcm_0_out(10 downto 0)) + std_logic_vector(not adpcm_1_out(11)&adpcm_1_out(10 downto 0));
audio_out <= audio(12 downto 1);
-- microprocessor 6800/01/03
main_cpu : entity work.cpu68
port map(
clk => clock_E, -- E clock input (falling edge)
rst => reset, -- reset input (active high)
rw => cpu_rw, -- read not write output
vma => cpu_vma, -- valid memory address (active high)
address => cpu_addr, -- address bus output
data_in => cpu_di, -- data bus input
data_out => cpu_do, -- data bus output
hold => '0', -- hold input (active high) extend bus cycle
halt => '0', -- halt input (active high) grants DMA
irq => cpu_irq, -- interrupt request input (active high)
nmi => cpu_nmi, -- non maskable interrupt request input (active high)
test_alu => open,
test_cc => open
);
rom_addr <= cpu_addr(15 downto 0) - x"8000";
snd_vma <= rom_cs and cpu_vma;
snd_rom_addr <= rom_addr(14 downto 0);
-- cpu wram
cpu_ram : entity work.spram
generic map( widthad_a => 7)
port map(
clock => clock_E,
wren => wram_we,
address => cpu_addr(6 downto 0),
data => cpu_do,
q => wram_do
);
ay83910_inst1: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(4),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay1_do,
CHANNEL_A => ay1_chan_a,
CHANNEL_B => ay1_chan_b,
CHANNEL_C => ay1_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => select_sound_r,
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => ay1_port_b_do
);
ay1_audio <= "0000000000" + ay1_chan_a + ay1_chan_b + ay1_chan_c;
ay83910_inst2: YM2149
port map (
CLK => clock_E,
CE => '1',
RESET => reset,
A8 => '1',
A9_L => port2_data(3),
BDIR => port2_data(0),
BC => port2_data(2),
DI => port1_data,
DO => ay2_do,
CHANNEL_A => ay2_chan_a,
CHANNEL_B => ay2_chan_b,
CHANNEL_C => ay2_chan_c,
SEL => '0',
MODE => '1',
ACTIVE => open,
IOA_in => (others => '0'),
IOA_out => open,
IOB_in => (others => '0'),
IOB_out => open
);
ay2_audio <= "0000000000" + ay2_chan_a + ay2_chan_b + ay2_chan_c;
end struct;

974
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/TenYardFight.vhd Normal file
View File

@@ -0,0 +1,974 @@
---------------------------------------------------------------------------------
-- TenYardFight, by Slingshot
-- based on Traverse USA by Dar (darfpga@aol.fr) (16/03/2019)
-- http://darfpga.blogspot.fr
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
--------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
-- T80/T80se - Version : 0247
-----------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
---------------------------------------------------------------------------------
-- cpu68 - Version 9th Jan 2004 0.8
-- 6800/01 compatible CPU core
-- GNU public license - December 2002 : John E. Kent
---------------------------------------------------------------------------------
-- YM2149 (AY-3-8910)
-- Copyright (c) MikeJ - Jan 2005
---------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- Features :
-- Video : TV 15KHz mode only (atm)
-- Coctail mode : OK
-- Sound : OK
-- Use with MAME roms from troangel.zip
--
-- Tropical Angel (Irem M57) Hardware caracteristics :
-- (No schematics available, video gen info is from MAME sources)
--
-- VIDEO : 1xZ80@3MHz CPU accessing its program rom, working ram,
-- sprite data ram, I/O, sound board register and trigger.
-- 32Kx8bits program rom
--
-- One char tile map 32x32 with H scrolling (32x32 visible)
-- 8Kx24bits graphics rom 3bits/pixel
-- 8colors per tile / 16 color sets
-- rbg palette 128 colors 8bits : 2red 3green 3blue
--
-- 256x16bits fine scroll RAM
-- Single RAM position 0x40 is used to scroll lines 64-127 (with wrapping)
-- Only 128-255 are used for fine scroll the bottom half (by signed 16 bit value), without wrapping around
--
-- 72 sprites / line, 16x32 with flip H/V
--
-- 16Kx24bits graphics rom 3bits/pixel
-- 8colors per sprite / 32 color sets among 16 colors;
-- rbg palette 16 colors 8bits : 2red 3green 3blue
--
-- Working ram : 2Kx8bits
-- Sprites data ram : 256x8bits
-- Sprites line buffer rams : 1 scan line delay flip/flop 2x256x4bits
--
-- SOUND : 1x6803@3.58MHz CPU accessing its program rom, working ram, 2x-AY3-8910, 1xMSM5205
-- 4Kx8bits program rom
-- 128x8bits working ram
--
-- 1xAY-3-8910
-- I/O to MSM5205 and command/trigger from video board.
-- 3 sound channels
--
-- 1xAY-3-8910
-- 3 sound channels
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity TenYardFight is
port(
clock_36 : in std_logic;
clock_0p895 : in std_logic;
reset : in std_logic;
palmode : in std_logic;
-- tv15Khz_mode : in std_logic;
video_r : out std_logic_vector(1 downto 0);
video_g : out std_logic_vector(2 downto 0);
video_b : out std_logic_vector(2 downto 0);
video_clk : out std_logic;
video_csync : out std_logic;
video_blankn : out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
audio_out : out std_logic_vector(10 downto 0);
cpu_rom_addr : out std_logic_vector(14 downto 0);
cpu_rom_do : in std_logic_vector( 7 downto 0);
snd_rom_addr: out std_logic_vector(14 downto 0);
snd_rom_do : in std_logic_vector(7 downto 0);
snd_vma : out std_logic;
sp_addr : out std_logic_vector(14 downto 0);
sp_graphx32_do : in std_logic_vector(31 downto 0);
dip_switch_1 : in std_logic_vector(7 downto 0);
dip_switch_2 : in std_logic_vector(7 downto 0);
input_0 : in std_logic_vector(7 downto 0);
input_1 : in std_logic_vector(7 downto 0);
input_2 : in std_logic_vector(7 downto 0);
dl_clk : in std_logic;
dl_addr : in std_logic_vector(17 downto 0);
dl_data : in std_logic_vector( 7 downto 0);
dl_wr : in std_logic;
dbg_cpu_addr : out std_logic_vector(15 downto 0)
);
end TenYardFight;
architecture struct of TenYardFight is
signal reset_n: std_logic;
signal clock_36n : std_logic;
signal clock_cnt : std_logic_vector(3 downto 0) := "0000";
signal hcnt : std_logic_vector(8 downto 0) := '0'&x"00"; -- horizontal counter
signal vcnt : std_logic_vector(8 downto 0) := '0'&x"00"; -- vertical counter
signal hcnt_flip : std_logic_vector(7 downto 0);
signal vcnt_flip : std_logic_vector(8 downto 0);
signal hcnt_scrolled : std_logic_vector(7 downto 0);
signal hcnt_scrolled_val : std_logic_vector(15 downto 0);
signal hcnt_scrolled_flip : std_logic_vector(2 downto 0);
signal pix_ena : std_logic;
signal csync : std_logic;
signal hsync0 : std_logic;
signal hsync1 : std_logic;
signal hsync2 : std_logic;
signal hblank : std_logic;
signal vblank : std_logic;
signal cpu_ena : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_di : std_logic_vector( 7 downto 0);
signal cpu_do : std_logic_vector( 7 downto 0);
signal cpu_wr_n : std_logic;
signal cpu_mreq_n : std_logic;
signal cpu_ioreq_n : std_logic;
signal cpu_irq_n : std_logic;
signal cpu_m1_n : std_logic;
-- signal cpu_rom_do : std_logic_vector( 7 downto 0);
signal wram_we : std_logic;
signal wram_do : std_logic_vector( 7 downto 0);
signal flip : std_logic;
signal flip_int : std_logic;
signal chrram_addr: std_logic_vector(11 downto 0);
signal chrram_we : std_logic;
signal chrram_do : std_logic_vector(7 downto 0);
signal chrram_do_to_cpu : std_logic_vector( 7 downto 0);
signal scroll_x : std_logic_vector(7 downto 0) := (others=>'0');
signal apply_xscroll : std_logic;
signal scrollram_addr : std_logic_vector( 7 downto 0);
signal scrollram_l_sel : std_logic;
signal scrollram_l_we : std_logic;
signal scrollram_l_cpu_do : std_logic_vector( 7 downto 0);
signal scrollram_l_do : std_logic_vector( 7 downto 0);
signal scrollram_h_sel : std_logic;
signal scrollram_h_we : std_logic;
signal scrollram_h_cpu_do : std_logic_vector( 7 downto 0);
signal scrollram_h_do : std_logic_vector( 7 downto 0);
signal scroll_val : std_logic_vector(15 downto 0);
signal chr_code: std_logic_vector( 9 downto 0);
signal chr_attr: std_logic_vector( 7 downto 0);
signal chr_code_line : std_logic_vector(12 downto 0);
signal chr_flip_h : std_logic;
signal chr_graphx1_do : std_logic_vector(7 downto 0);
signal chr_graphx2_do : std_logic_vector(7 downto 0);
signal chr_graphx3_do : std_logic_vector(7 downto 0);
signal chr_color : std_logic_vector(3 downto 0);
signal chr_palette_addr : std_logic_vector(7 downto 0);
signal chr_palette_do : std_logic_vector(7 downto 0);
signal chr_palettel_do : std_logic_vector(7 downto 0);
signal chr_paletteh_do : std_logic_vector(7 downto 0);
signal sprram_addr : std_logic_vector(6 downto 0);
signal sprram_we : std_logic;
signal sprram_do : std_logic_vector(7 downto 0);
signal spr_en : std_logic;
signal spr_pix_ena : std_logic;
signal spr_hcnt : std_logic_vector( 9 downto 0);
signal spr_posv, spr_posv_r : std_logic_vector( 7 downto 0);
signal spr_attr, spr_attr_r : std_logic_vector( 7 downto 0);
signal spr_code, spr_code_r : std_logic_vector( 7 downto 0);
signal spr_posh, spr_posh_r : std_logic_vector( 7 downto 0);
signal rad_palette_addr : std_logic_vector( 7 downto 0);
signal rad_palettel_do : std_logic_vector( 7 downto 0);
signal rad_paletteh_do : std_logic_vector( 7 downto 0);
signal rad_palette_do : std_logic_vector( 7 downto 0);
signal spr_vcnt : std_logic_vector( 7 downto 0);
signal spr_on_line : std_logic;
signal spr_on_line_r : std_logic;
signal spr_code_line : std_logic_vector(13 downto 0);
signal spr_line_cnt : std_logic_vector( 4 downto 0);
signal spr_graphx1_do : std_logic_vector( 7 downto 0);
signal spr_graphx2_do : std_logic_vector( 7 downto 0);
signal spr_graphx3_do : std_logic_vector( 7 downto 0);
signal spr_palette_addr : std_logic_vector( 7 downto 0);
signal spr_palette_do : std_logic_vector( 7 downto 0);
signal spr_pixels : std_logic_vector( 4 downto 0);
signal spr_rgb_lut_addr : std_logic_vector( 4 downto 0);
signal spr_rgb_lut_do : std_logic_vector( 7 downto 0);
signal spr_input_line_addr : std_logic_vector(7 downto 0);
signal spr_input_line_di : std_logic_vector(3 downto 0);
signal spr_input_line_do : std_logic_vector(3 downto 0);
signal spr_input_line_we : std_logic;
signal spr_output_line_addr : std_logic_vector(7 downto 0);
signal spr_output_line_di : std_logic_vector(3 downto 0);
signal spr_output_line_do : std_logic_vector(3 downto 0);
signal spr_output_line_we : std_logic;
signal spr_buffer_ram1_addr : std_logic_vector(7 downto 0);
signal spr_buffer_ram1_we : std_logic;
signal spr_buffer_ram1_di : std_logic_vector(3 downto 0);
signal spr_buffer_ram1_do : std_logic_vector(3 downto 0);
signal spr_buffer_ram2_addr : std_logic_vector(7 downto 0);
signal spr_buffer_ram2_we : std_logic;
signal spr_buffer_ram2_di : std_logic_vector(3 downto 0);
signal spr_buffer_ram2_do : std_logic_vector(3 downto 0);
signal sound_cmd : std_logic_vector( 7 downto 0);
signal audio : std_logic_vector(11 downto 0);
signal char_graphics1_we : std_logic;
signal char_graphics2_we : std_logic;
signal char_graphics3_we : std_logic;
signal char_palette_l_we : std_logic;
signal char_palette_h_we : std_logic;
signal rad_palette_l_we : std_logic;
signal rad_palette_h_we : std_logic;
signal spr_palette_we : std_logic;
signal spr_rgb_lut_we : std_logic;
begin
clock_36n <= not clock_36;
reset_n <= not reset;
sp_addr <= '0'& spr_code_line;
-- debug
process (reset, clock_36)
begin
if rising_edge(clock_36) and cpu_ena ='1' and cpu_mreq_n ='0' then
dbg_cpu_addr <= cpu_addr;
end if;
end process;
-- make enables clock from 36MHz
process (clock_36, reset)
begin
if reset='1' then
clock_cnt <= "0000";
else
if rising_edge(clock_36) then
if clock_cnt = "1011" then
clock_cnt <= "0000";
else
clock_cnt <= clock_cnt + 1;
end if;
end if;
end if;
end process;
pix_ena <= '1' when clock_cnt = "0101" or clock_cnt = "1011" else '0'; -- (6MHz)
cpu_ena <= '1' when clock_cnt = "1011" else '0'; -- (3MHz)
-------------------
-- Video scanner --
-------------------
-- hcnt [x080..x0FF-x100..x1FF] => 128+256 = 384 pixels, 384/6.144Mhz => 1 line is 62.5us (16.000KHz)
-- vcnt [x0E6..x0FF-x100..x1FF] => 26+256 = 282 lines, 1 frame is 260 x 62.5us = 17.625ms (56.74Hz)
process (reset, clock_36, pix_ena)
begin
if reset='1' then
hcnt <= (others=>'0');
vcnt <= '0'&X"FC";
else
if rising_edge(clock_36) and pix_ena = '1'then
hcnt <= hcnt + 1;
if hcnt = '1'&x"FF" then
hcnt <= '0'&x"80";
vcnt <= vcnt + 1;
if vcnt = '1'&x"FF" then
if palmode = '0' then
vcnt <= '0'&x"E6"; -- from M52 schematics
else
vcnt <= '0'&x"C8";
end if;
end if;
end if;
end if;
end if;
end process;
flip <= flip_int xor dip_switch_2(0);
hcnt_flip <= hcnt(7 downto 0) when flip ='1' else not hcnt(7 downto 0);
vcnt_flip <= vcnt when flip ='1' else not vcnt;
------------------------------------------
-- cpu data input with address decoding --
------------------------------------------
cpu_di <= cpu_rom_do when cpu_addr(15 downto 12) < X"6" else -- 0000-7FFF
scrollram_l_cpu_do when scrollram_l_sel = '1' else
scrollram_h_cpu_do when scrollram_h_sel = '1' else
chrram_do_to_cpu when cpu_addr(15 downto 12) = X"8" else -- 8000-8FFF
wram_do when cpu_addr(15 downto 12) = X"E" else -- E000-EFFF
input_0 when cpu_addr(15 downto 0) = X"D000" else -- D000
input_1 when cpu_addr(15 downto 0) = X"D001" else -- D001
input_2 when cpu_addr(15 downto 0) = X"D002" else -- D002
dip_switch_1 when cpu_addr(15 downto 0) = X"D003" else -- D003
dip_switch_2 when cpu_addr(15 downto 0) = X"D004" else -- D004
X"FF";
------------------------------------------------------------------------
-- Misc registers : interrupt, scroll, cocktail flip, sound trigger
------------------------------------------------------------------------
scrollram_l_sel <= '1' when cpu_addr(15 downto 8) = X"90" else '0';
scrollram_l_we <= scrollram_l_sel and not cpu_wr_n;
scrollram_h_sel <= '1' when cpu_addr(15 downto 8) = X"91" else '0';
scrollram_h_we <= scrollram_h_sel and not cpu_wr_n;
process (clock_36, reset)
begin
if reset = '1' then
sound_cmd <= x"00";
elsif rising_edge(clock_36) then
if cpu_m1_n = '0' and cpu_ioreq_n = '0' then
cpu_irq_n <= '1';
else -- lauch irq and end of frame
if ((vcnt = 230 and flip = '0') or (vcnt = 448 and flip = '1')) and (hcnt = '0'&X"80") then
cpu_irq_n <= '0';
end if;
end if;
if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"9040" then scroll_x <= cpu_do; end if;--scrollram[0x40]
if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D000" then sound_cmd <= cpu_do; end if;
if cpu_wr_n = '0' and cpu_addr(15 downto 0) = X"D001" then flip_int <= cpu_do(0); end if;
end if;
end process;
------------------------------------------
-- write enable to working ram from CPU --
------------------------------------------
wram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"E" else '0';
----------------------
--- sprite machine ---
----------------------
-- sprite data scanner
-- 080-3FF => C820-C8FF
process (clock_36)
begin
if rising_edge(clock_36) then
spr_pix_ena <= not spr_pix_ena; -- (18MHz)
if hcnt = '1'&x"FF" and pix_ena = '1' then -- synched with hcnt
spr_hcnt <= "00"&x"80";
spr_pix_ena <= '0';
else
if spr_pix_ena = '1' then
spr_hcnt <= spr_hcnt + '1';
if spr_hcnt( 9 downto 0) = "11"&x"FF" then
spr_hcnt <= "00"&x"80";
end if;
end if;
end if;
end if;
end process;
sprram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 8) = X"C8" else '0';
sprram_addr <= spr_hcnt(8 downto 4) & spr_hcnt(1 downto 0);
-- Enable sprites in lines 64-240
spr_en <= '1' when ( vcnt > '1'&x"40" and vcnt < '1'&x"EF" and flip = '1') or ((vcnt > '1'&x"10" or vcnt < '1'&x"C0") and flip = '0') else '0';
-- latch current sprite data with respect to pixel and hcnt in relation with sprite data ram addressing
process (clock_36)
variable code:std_logic_vector(7 downto 0);
begin
if rising_edge(clock_36) then
if spr_pix_ena = '1' then
if spr_hcnt(2 downto 0) = "000" then spr_posv <= sprram_do; end if;
if spr_hcnt(2 downto 0) = "001" then spr_attr <= sprram_do; end if;
if spr_hcnt(2 downto 0) = "010" then
code := spr_attr(5) & sprram_do(7) & sprram_do(5 downto 0);
spr_code_line <= code(7 downto 6) & (spr_vcnt(4) xor spr_attr(7)) & code(5 downto 0) & (spr_attr(6) xor spr_hcnt(3)) & (spr_vcnt(3 downto 0) xor (spr_attr(7) & spr_attr(7) & spr_attr(7) & spr_attr(7)));
end if;
if spr_hcnt(2 downto 0) = "011" then spr_posh <= sprram_do; end if;
if spr_hcnt(2 downto 0) = "111" then
spr_posh_r <= spr_posh;
spr_posv_r <= spr_posv;
spr_attr_r <= spr_attr;
spr_graphx1_do <= sp_graphx32_do(23 downto 16);
spr_graphx2_do <= sp_graphx32_do(15 downto 8);
spr_graphx3_do <= sp_graphx32_do( 7 downto 0);
if spr_vcnt(7 downto 5) = "111" and spr_en = '1' then
spr_on_line <= '1';
else
spr_on_line <= '0';
end if;
end if;
end if;
end if;
end process;
-- compute sprite presence and graphics rom address w.r.t vertical position and v_flip (attr(7))
-- sprite is also inhibited when outside scrolling zone (cpu_has_spr_ram)
spr_vcnt <= vcnt_flip(7 downto 0) + spr_posv - 1;
-- get and serialise sprite graphics data and h_flip (attr(6))
-- and compute palette address from graphics bits and color set#
spr_palette_addr(0) <= spr_graphx1_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when spr_attr_r(6) = '0' else
spr_graphx1_do(to_integer(unsigned( (spr_hcnt(2 downto 0)))));
spr_palette_addr(1) <= spr_graphx2_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when spr_attr_r(6) = '0' else
spr_graphx2_do(to_integer(unsigned( (spr_hcnt(2 downto 0)))));
spr_palette_addr(2) <= spr_graphx3_do(to_integer(unsigned(not(spr_hcnt(2 downto 0))))) when spr_attr_r(6) = '0' else
spr_graphx3_do(to_integer(unsigned( (spr_hcnt(2 downto 0)))));
spr_palette_addr(7 downto 3) <= spr_attr_r(4 downto 0); -- color set#
----------------------------------------------------
-- manage read/write flip-flop sprite line buffer --
----------------------------------------------------
-- input buffer work at 36Mhz (read previous data before write)
-- sprite data is written to input buffer when not already written (previous data differ from 0000)
-- buffer data is written back to 0000 (cleared) after read from output buffer
-- output buffer work at normal pixel speed (12Mhz since read previous data before clear)
-- input/output buffers are swapped (fkip-flop) each other line
process (clock_36)
begin
if rising_edge(clock_36) then
if spr_pix_ena = '1' then
spr_on_line_r <= spr_on_line;
spr_pixels(3 downto 0) <= spr_palette_do(3 downto 0);
spr_pixels(4) <= spr_attr_r(4); -- not used !
-- write input buffer at the right place
if spr_hcnt(3 downto 0) = "1000" then
spr_input_line_addr <= spr_posh_r;
else
spr_input_line_addr <= spr_input_line_addr+1;
end if;
end if;
-- read output buffer w.r.t. flip screen (normal/reverse)
if pix_ena = '1' then
if hcnt < '1'&x"09" then
spr_output_line_addr <= X"00";
else
if flip = '0' then
spr_output_line_addr <= spr_output_line_addr+1;
else
spr_output_line_addr <= spr_output_line_addr-1;
end if;
end if;
end if;
-- demux output buffer (flip-flop)
if pix_ena = '0' then
if vcnt(0) = '1'then
spr_output_line_do <= spr_buffer_ram1_do;
else
spr_output_line_do <= spr_buffer_ram2_do;
end if;
end if;
end if;
end process;
-- read previous data from input buffer w.r.t. flip-flop
spr_input_line_do <= spr_buffer_ram1_do when vcnt(0) = '0' else spr_buffer_ram2_do;
-- feed input buffer
spr_input_line_di <= spr_pixels(3 downto 0);
-- keep write data if input buffer is clear
spr_input_line_we <= '1' when spr_on_line_r = '1' and spr_pix_ena = '1' and spr_input_line_do = "0000" else '0';
-- feed output buufer (clear)
spr_output_line_di <= "0000";
-- always clear just after read
spr_output_line_we <= pix_ena;
-- flip-flop input/output buffers
spr_buffer_ram1_addr <= not(spr_input_line_addr) when vcnt(0) = '0' else spr_output_line_addr;
spr_buffer_ram1_di <= spr_input_line_di when vcnt(0) = '0' else spr_output_line_di;
spr_buffer_ram1_we <= spr_input_line_we when vcnt(0) = '0' else spr_output_line_we;
spr_buffer_ram2_addr <= not(spr_input_line_addr) when vcnt(0) = '1' else spr_output_line_addr;
spr_buffer_ram2_di <= spr_input_line_di when vcnt(0) = '1' else spr_output_line_di;
spr_buffer_ram2_we <= spr_input_line_we when vcnt(0) = '1' else spr_output_line_we;
-- feed sprite color lut with sprite output buffer
spr_rgb_lut_addr <= '0' & not spr_output_line_do;
--------------------
--- char machine ---
--------------------
-- compute scrolling zone and apply to horizontal scanner
scrollram_addr <= vcnt_flip(7 downto 0);
apply_xscroll <= '1' when vcnt_flip(7 downto 6) = "01" else '0'; -- apply common scroll_x (scroll mem[0x40]) to lines 64-127
hcnt_scrolled_val <= x"00" & hcnt_flip + scroll_x when apply_xscroll = '1' else
hcnt_flip(7 downto 0) + scroll_val when scroll_val(15) = '0' else
hcnt_flip(7 downto 0) - not scroll_val - 1;
hcnt_scrolled <= hcnt_scrolled_val(7 downto 0) when apply_xscroll = '1' or hcnt_scrolled_val(15 downto 8) = x"00" else
x"F"&'1'&hcnt_scrolled_val(2 downto 0) when hcnt_scrolled_val(15) = '0' else -- positive overflow
x"0"&'0'&hcnt_scrolled_val(2 downto 0); -- negative overflow
hcnt_scrolled_flip <= hcnt_scrolled(2 downto 0) when flip = '1' else not (hcnt_scrolled(2 downto 0));
-- compute ram tile address w.r.t horizontal scanner
-- address char attr at pixel # 0
-- address char code at pixel # 4
-- give access to CPU for all other pixels
-- todo not sure about this Gehstock
with hcnt_scrolled_flip(2 downto 0) select chrram_addr <=
vcnt_flip(7 downto 2) & hcnt_scrolled(7 downto 3) & '1' when "000",
vcnt_flip(7 downto 2) & hcnt_scrolled(7 downto 3) & '0' when "100",
cpu_addr(11 downto 0) when others;
-- write enable to char tile ram from CPU
chrram_we <= '1' when cpu_wr_n = '0' and cpu_addr(15 downto 12) = X"8" and hcnt_scrolled_flip(1 downto 0) /= "00" else '0';
-- read char tile ram and manage char graphics
process (clock_36)
begin
if rising_edge(clock_36) then
-- latch fine scroll value at the beginning of the line
if hcnt = '0'&x"80" then
scroll_val <= scrollram_h_do & scrollram_l_do;
end if;
-- latch ram tile output w.r.t to addressing scheme (attr/code/CPU)
if hcnt_scrolled_flip(2 downto 0) = "000" then
chr_code(7 downto 0) <= chrram_do;
end if;
if hcnt_scrolled_flip(1 downto 0) /= "00" then
chrram_do_to_cpu <= chrram_do;
end if;
if hcnt_scrolled_flip(2 downto 0) = "100" then
chr_attr <= chrram_do;
chr_code(9 downto 8) <= chrram_do(7 downto 6);
end if;
-- compute graphics rom address and delay char flip and color
if hcnt_scrolled_flip(2 downto 0) = "111" and pix_ena = '1' then
chr_code_line( 2 downto 0) <= vcnt_flip(2 downto 0) xor (chr_attr(4) & chr_attr(4) & chr_attr(4));
chr_code_line(12 downto 3) <= chr_code;
chr_flip_h <= chr_attr(5);
chr_color <= chr_attr(3 downto 0);
end if;
-- get and serialise char graphics data and w.r.t char flip
-- and compute palette address from graphics bits and color set#
if pix_ena = '1' then
chr_palette_addr(7) <= '0';
chr_palette_addr(6 downto 3) <= chr_color;
if chr_flip_h = '0' then
chr_palette_addr(0) <= chr_graphx1_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0)))));
chr_palette_addr(1) <= chr_graphx2_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0)))));
chr_palette_addr(2) <= chr_graphx3_do(to_integer(unsigned(not(hcnt_scrolled(2 downto 0)))));
else
chr_palette_addr(0) <= chr_graphx1_do(to_integer(unsigned(hcnt_scrolled(2 downto 0))));
chr_palette_addr(1) <= chr_graphx2_do(to_integer(unsigned(hcnt_scrolled(2 downto 0))));
chr_palette_addr(2) <= chr_graphx3_do(to_integer(unsigned(hcnt_scrolled(2 downto 0))));
end if;
end if;
end if;
end process;
---------------------------
-- mux char/sprite video --
---------------------------
process (clock_36)
begin
if rising_edge(clock_36) then
if pix_ena = '1' then
-- always give priority to sprite when not 0000
if spr_output_line_do /= "0000" then
video_r <= spr_rgb_lut_do(7 downto 6);
video_g <= spr_rgb_lut_do(5 downto 3);
video_b <= spr_rgb_lut_do(2 downto 0);
else
video_r <= chr_palette_do(7 downto 6);
video_g <= chr_palette_do(5 downto 3);
video_b <= chr_palette_do(2 downto 0);
end if;
end if;
end if;
end process;
---------------------------------------------------------
-- Sound board is same as Moon patrol (except CPU rom) --
---------------------------------------------------------
Sound_Board : entity work.Sound_Board
port map(
clock_E => clock_0p895,
areset => reset,
select_sound => sound_cmd,
snd_rom_addr => snd_rom_addr,
snd_rom_do => snd_rom_do,
snd_vma => snd_vma,
audio_out => audio
);
audio_out <= audio(11 downto 1);
----------------------------
-- video syncs and blanks --
----------------------------
video_csync <= csync;
process(clock_36, pix_ena)
constant hcnt_base : integer := 180;
variable hsync_cnt : std_logic_vector(8 downto 0);
variable vsync_cnt : std_logic_vector(3 downto 0);
begin
if rising_edge(clock_36) and pix_ena = '1' then
if hcnt = hcnt_base then
hsync_cnt := (others=>'0');
else
hsync_cnt := hsync_cnt + 1;
end if;
if hsync_cnt = 0 then hsync0 <= '0';
elsif hsync_cnt = 24 then hsync0 <= '1';
end if;
if hsync_cnt = 0 then hsync1 <= '0';
elsif hsync_cnt = 0+8 then hsync1 <= '1';
elsif hsync_cnt = 192 then hsync1 <= '0';
elsif hsync_cnt = 192+8 then hsync1 <= '1';
end if;
if hsync_cnt = 0 then hsync2 <= '0';
elsif hsync_cnt = 192-8 then hsync2 <= '1';
elsif hsync_cnt = 192 then hsync2 <= '0';
elsif hsync_cnt = 384-8 then hsync2 <= '1';
end if;
if hcnt = hcnt_base then
if vcnt = 238 then
vsync_cnt := X"0";
else
if vsync_cnt < X"F" then vsync_cnt := vsync_cnt + 1; end if;
end if;
end if;
if vsync_cnt = 0 then csync <= hsync1;
elsif vsync_cnt = 1 then csync <= hsync1;
elsif vsync_cnt = 2 then csync <= hsync1;
elsif vsync_cnt = 3 then csync <= hsync2;
elsif vsync_cnt = 4 then csync <= hsync2;
elsif vsync_cnt = 5 then csync <= hsync2;
elsif vsync_cnt = 6 then csync <= hsync1;
elsif vsync_cnt = 7 then csync <= hsync1;
elsif vsync_cnt = 8 then csync <= hsync1;
else csync <= hsync0;
end if;
-- hcnt : [128-511] 384 pixels
if hcnt = 128 then hblank <= '1';
elsif hcnt = 272 then hblank <= '0';
end if;
-- vcnt : [230-511] 282 lines
if vcnt = 495 then vblank <= '1';
elsif vcnt = 256 then vblank <= '0';
end if;
-- external sync and blank outputs
video_blankn <= not (hblank or vblank);
--
video_hs <= hsync0;
--
if vsync_cnt = 0 then video_vs <= '0';
elsif vsync_cnt = 2 then video_vs <= '1';
end if;
--
end if;
end process;
------------------------------
-- components & sound board --
------------------------------
-- microprocessor Z80
cpu : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
port map(
RESET_n => reset_n,
CLK_n => clock_36,
CLKEN => cpu_ena,
WAIT_n => '1',
INT_n => cpu_irq_n,
NMI_n => '1', --cpu_nmi_n,
BUSRQ_n => '1',
M1_n => cpu_m1_n,
MREQ_n => cpu_mreq_n,
IORQ_n => cpu_ioreq_n,
RD_n => open,
WR_n => cpu_wr_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_di,
DO => cpu_do
);
cpu_rom_addr <= cpu_addr(14 downto 0);
-- working RAM 0xE000-0xEFFF
wram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 12)
port map(
clk => clock_36n,
we => wram_we,
addr => cpu_addr(11 downto 0),
d => cpu_do,
q => wram_do
);
-- scroll RAM lo 0x9000-0x90FF
scrollram_l : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
we_a => scrollram_l_we,
addr_a => cpu_addr(7 downto 0),
d_a => cpu_do,
q_a => scrollram_l_cpu_do,
clk_b => clock_36n,
addr_b => scrollram_addr,
q_b => scrollram_l_do
);
-- scroll RAM hi 0x9100-0x91FF
scrollram_h : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
we_a => scrollram_h_we,
addr_a => cpu_addr(7 downto 0),
d_a => cpu_do,
q_a => scrollram_h_cpu_do,
clk_b => clock_36n,
addr_b => scrollram_addr,
q_b => scrollram_h_do
);
-- char RAM 0x8000-0x8FFF
chrram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 12)
port map(
clk => clock_36n,
we => chrram_we,
addr => chrram_addr,
d => cpu_do,
q => chrram_do
);
-- sprite RAM 0xC820-0xC87F
sprite_ram : entity work.dpram
--generic map( dWidth => 8, aWidth => 8)
generic map( dWidth => 8, aWidth => 7)
port map(
clk_a => clock_36n,
we_a => sprram_we,
-- addr_a => cpu_addr(7 downto 0),
addr_a => cpu_addr(6 downto 0),
d_a => cpu_do,
clk_b => clock_36n,
addr_b => sprram_addr,
q_b => sprram_do
);
-- sprite line buffer 1
sprlinebuf1 : entity work.gen_ram
generic map( dWidth => 4, aWidth => 8)
port map(
clk => clock_36n,
we => spr_buffer_ram1_we,
addr => spr_buffer_ram1_addr,
d => spr_buffer_ram1_di,
q => spr_buffer_ram1_do
);
-- sprite line buffer 2
sprlinebuf2 : entity work.gen_ram
generic map( dWidth => 4, aWidth => 8)
port map(
clk => clock_36n,
we => spr_buffer_ram2_we,
addr => spr_buffer_ram2_addr,
d => spr_buffer_ram2_di,
q => spr_buffer_ram2_do
);
-- char graphics ROM 3E
char_graphics_1 : entity work.dpram
generic map( dWidth => 8, aWidth => 13)
port map(
clk_a => clock_36n,
addr_a => chr_code_line,
q_a => chr_graphx1_do,
clk_b => dl_clk,
addr_b => dl_addr(12 downto 0),
we_b => char_graphics1_we,
d_b => dl_data
);
char_graphics1_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "01000" else '0'; -- 10000 - 11FFF
-- char graphics ROM 3D
char_graphics_2 : entity work.dpram
generic map( dWidth => 8, aWidth => 13)
port map(
clk_a => clock_36n,
addr_a => chr_code_line,
q_a => chr_graphx2_do,
clk_b => dl_clk,
addr_b => dl_addr(12 downto 0),
we_b => char_graphics2_we,
d_b => dl_data
);
char_graphics2_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "01001" else '0'; -- 12000 - 13FFF
-- char graphics ROM 3C
char_graphics_3 : entity work.dpram
generic map( dWidth => 8, aWidth => 13)
port map(
clk_a => clock_36n,
addr_a => chr_code_line,
q_a => chr_graphx3_do,
clk_b => dl_clk,
addr_b => dl_addr(12 downto 0),
we_b => char_graphics3_we,
d_b => dl_data
);
char_graphics3_we <= '1' when dl_wr = '1' and dl_addr(17 downto 13) = "01010" else '0'; -- 14000 - 15FFF
radar_palette_l : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
addr_a => rad_palette_addr,
q_a => rad_palettel_do,
clk_b => dl_clk,
addr_b => dl_addr(7 downto 0),
we_b => rad_palette_l_we,
d_b => dl_data
);
radar_palette_h : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
addr_a => rad_palette_addr,
q_a => rad_paletteh_do,
clk_b => dl_clk,
addr_b => dl_addr(7 downto 0),
we_b => rad_palette_h_we,
d_b => dl_data
);
rad_palette_l_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100000" else '0'; --22000 - 220FF radar pal 256b yard.2n
rad_palette_h_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100001" else '0'; --22100 - 221FF radar pal 256b yard.2m
rad_palette_do <= rad_paletteh_do(3 downto 0) & rad_palettel_do(3 downto 0);
char_palette_l : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
addr_a => chr_palette_addr,
q_a => chr_palettel_do,
clk_b => dl_clk,
addr_b => dl_addr(7 downto 0),
we_b => char_palette_l_we,
d_b => dl_data
);
char_palette_h : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
addr_a => chr_palette_addr,
q_a => chr_paletteh_do,
clk_b => dl_clk,
addr_b => dl_addr(7 downto 0),
we_b => char_palette_h_we,
d_b => dl_data
);
char_palette_l_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100010" else '0'; --22200 - 222FF chr pal lo 256b yard.1c
char_palette_h_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100011" else '0'; --22300 - 223FF chr pal hi 256b yard.1d
chr_palette_do <= chr_paletteh_do(3 downto 0) & chr_palettel_do(3 downto 0);
-- sprite palette ROM 3D
spr_palette : entity work.dpram
generic map( dWidth => 8, aWidth => 8)
port map(
clk_a => clock_36n,
addr_a => spr_palette_addr,
q_a => spr_palette_do,
clk_b => dl_clk,
addr_b => dl_addr(7 downto 0),
we_b => spr_palette_we,
d_b => dl_data
);
spr_palette_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100100" else '0'; --22400 - 224FF spr lut 256b yard.2h
-- sprite rgb lut ROM 1B
spr_rgb_lut : entity work.dpram
generic map( dWidth => 8, aWidth => 5)
port map(
clk_a => clock_36n,
addr_a => spr_rgb_lut_addr,
q_a => spr_rgb_lut_do,
clk_b => dl_clk,
addr_b => dl_addr(4 downto 0),
we_b => spr_rgb_lut_we,
d_b => dl_data
);
spr_rgb_lut_we <= '1' when dl_wr = '1' and dl_addr(17 downto 8) = "1000100101" else '0'; --22500 - 2251F spr pal 32b yard.1f
end struct;

321
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/TenYardFight_MiST.sv Normal file
View File

@@ -0,0 +1,321 @@
//============================================================================
// Arcade: TenYardFight top-level for MiST
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module TenYardFight_MiST(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
`include "rtl/build_id.v"
localparam CONF_STR = {
"TENYARD;ROM;",
"O2,Rotate Controls,Off,On;",
"O1,Video Timing,Original,Pal 50Hz;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blending,Off,On;",
"O6,Service,Off,On;",
"O7,Flip,Off,On;",
"O8,Invulnerability,Off,On;",
"T0,Reset;",
"V,v1.0.",`BUILD_DATE
};
wire palmode = status[1];
wire rotate = status[2];
wire [1:0] scanlines = status[4:3];
wire blend = status[5];
wire service = status[6];
wire flip = status[7];
wire invuln = status[8];
assign LED = ~ioctl_downl;
assign SDRAM_CLK = clk_sd;
assign SDRAM_CKE = 1;
wire clk_sys, clk_aud, clk_sd;
wire pll_locked;
pll_mist pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys),
.c1(clk_aud),
.c2(clk_sd),
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] audio;
wire hs, vs;
wire blankn;
wire [2:0] g,b;
wire [1:0] r;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [14:0] snd_addr;
wire [15:0] snd_do;
wire snd_vma;
wire [14:0] sp_addr;
wire [31:0] sp_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
/* ROM structure
00000 - 07FFF main CPU 32k yf-a-3p-b + yf-a-3n-b + yf-a-3m-b + yf-a-3m-b
08000 - 0FFFF snd CPU 32k yf-s.3b + yf-s.1b + yf-s.3a + yf-s.1a
10000 - 15FFF gfx1 24k yf-a.3e + yf-a.3d + yf-a.3c
16000 - 21FFF gfx2 48k yf-b.5b + yf-b.5c + yf-b.5f + yf-b.5e + yf-b.5j + yf-b.5k
22000 - 220FF radar pal lo 256b yard.2n
22100 - 221FF radar pal hi 256b yard.2m
22200 - 222FF chr pal lo 256b yard.1c
22300 - 223FF chr pal hi 256b yard.1d
22400 - 224FF spr lut 256b yard.2h
22500 - 2251F spr pal 32b yard.1f
*/
data_io data_io(
.clk_sys ( clk_sd ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
wire [24:0] sp_ioctl_addr = ioctl_addr - 17'h16000;
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clk_sd ),
// port1 used for main + sound CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 16'hffff : {2'b00, rom_addr[14:1]} ),
.cpu1_q ( rom_do ),
.cpu2_addr ( ioctl_downl ? 16'hffff : (16'h8000 + snd_addr[14:1]) ),
.cpu2_q ( snd_do ),
// port2 for sprite graphics
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( {sp_ioctl_addr[23:16], sp_ioctl_addr[13:0], sp_ioctl_addr[15]} ), // merge sprite roms to 32-bit wide words
.port2_ds ( {sp_ioctl_addr[14], ~sp_ioctl_addr[14]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.sp_addr ( ioctl_downl ? 15'h7fff : sp_addr ),
.sp_q ( sp_do )
);
// ROM download controller
always @(posedge clk_sd) begin
reg ioctl_wr_last = 0;
reg snd_vma_r, snd_vma_r2;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
// reset signal generation
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clk_sys) begin
reg ioctl_downlD;
reg [15:0] reset_count;
ioctl_downlD <= ioctl_downl;
if (status[0] | buttons[1] | ~rom_loaded) reset_count <= 16'hffff;
else if (reset_count != 0) reset_count <= reset_count - 1'd1;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= reset_count != 16'h0000;
end
wire [7:0] dip1 = ~8'b00000010;
wire [7:0] dip2 = ~{ 1'b0, invuln, 1'b0, 1'b0/*stop*/, 3'b010, flip };
TenYardFight TenYardFight(
.clock_36 ( clk_sys ),
.clock_0p895 ( clk_aud ),
.reset ( reset ),
.palmode ( palmode ),
.video_r ( r ),
.video_g ( g ),
.video_b ( b ),
.video_hs ( hs ),
.video_vs ( vs ),
.video_blankn ( blankn ),
.audio_out ( audio ),
.cpu_rom_addr ( rom_addr ),
.cpu_rom_do ( rom_addr[0] ? rom_do[15:8] : rom_do[7:0] ),
.snd_rom_addr ( snd_addr ),
.snd_rom_do ( snd_addr[0] ? snd_do[15:8] : snd_do[7:0] ),
.snd_vma(snd_vma),
.sp_addr ( sp_addr ),
.sp_graphx32_do( sp_do ),
.dip_switch_1 ( dip1 ),
.dip_switch_2 ( dip2 ),
.input_0 ( ~{4'd0, m_coin1, service, m_two_players, m_one_player} ),
.input_1 ( ~{m_fireA, 1'b0, m_fireB, 1'b0, m_up, m_down, m_left, m_right} ),
.input_2 ( ~{m_fire2A, 1'b0, m_fire2B, m_coin2, m_up2, m_down2, m_left2, m_right2} ),
.dl_clk ( clk_sd ),
.dl_addr ( ioctl_addr[17:0]),
.dl_data ( ioctl_dout ),
.dl_wr ( ioctl_wr )
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clk_sys ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? {r, r[1] } : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? b : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( { 1'b1, rotate } ),
.scandoubler_disable( scandoublerD ),
.scanlines ( scanlines ),
.blend ( blend ),
.ypbpr ( ypbpr )
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
wire dac_o;
assign AUDIO_L = dac_o;
assign AUDIO_R = dac_o;
dac #(
.C_bits(11))
dac(
.clk_i(clk_aud),
.res_n_i(1),
.dac_i(audio),
.dac_o(dac_o)
);
wire m_up, m_down, m_left, m_right, m_fireA, m_fireB, m_fireC, m_fireD, m_fireE, m_fireF;
wire m_up2, m_down2, m_left2, m_right2, m_fire2A, m_fire2B, m_fire2C, m_fire2D, m_fire2E, m_fire2F;
wire m_tilt, m_coin1, m_coin2, m_coin3, m_coin4, m_one_player, m_two_players, m_three_players, m_four_players;
arcade_inputs inputs (
.clk ( clk_sys ),
.key_strobe ( key_strobe ),
.key_pressed ( key_pressed ),
.key_code ( key_code ),
.joystick_0 ( joystick_0 ),
.joystick_1 ( joystick_1 ),
.rotate ( rotate ),
.orientation ( 2'b10 ),
.joyswap ( 1'b0 ),
.oneplayer ( 1'b1 ),
.controls ( {m_tilt, m_coin4, m_coin3, m_coin2, m_coin1, m_four_players, m_three_players, m_two_players, m_one_player} ),
.player1 ( {m_fireF, m_fireE, m_fireD, m_fireC, m_fireB, m_fireA, m_up, m_down, m_left, m_right} ),
.player2 ( {m_fire2F, m_fire2E, m_fire2D, m_fire2C, m_fire2B, m_fire2A, m_up2, m_down2, m_left2, m_right2} )
);
endmodule

329
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/YM2149.sv Normal file
View File

@@ -0,0 +1,329 @@
//
// Copyright (c) MikeJ - Jan 2005
// Copyright (c) 2016-2018 Sorgelig
//
// All rights reserved
//
// Redistribution and use in source and synthezised forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in synthesized form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// Neither the name of the author nor the names of other contributors may
// be used to endorse or promote products derived from this software without
// specific prior written permission.
//
// THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// BDIR BC MODE
// 0 0 inactive
// 0 1 read value
// 1 0 write value
// 1 1 set address
//
module YM2149
(
input CLK, // Global clock
input CE, // PSG Clock enable
input RESET, // Chip RESET (set all Registers to '0', active hi)
input BDIR, // Bus Direction (0 - read , 1 - write)
input BC, // Bus control
input A8,
input A9_L,
input [7:0] DI, // Data In
output [7:0] DO, // Data Out
output [7:0] CHANNEL_A, // PSG Output channel A
output [7:0] CHANNEL_B, // PSG Output channel B
output [7:0] CHANNEL_C, // PSG Output channel C
input SEL,
input MODE,
output [5:0] ACTIVE,
input [7:0] IOA_in,
output [7:0] IOA_out,
input [7:0] IOB_in,
output [7:0] IOB_out
);
assign ACTIVE = ~ymreg[7][5:0];
assign IOA_out = ymreg[7][6] ? ymreg[14] : 8'hff;
assign IOB_out = ymreg[7][7] ? ymreg[15] : 8'hff;
reg [7:0] addr;
reg [7:0] ymreg[16];
wire cs = !A9_L & A8;
// Write to PSG
reg env_reset;
always @(posedge CLK) begin
if(RESET) begin
ymreg <= '{default:0};
ymreg[7] <= '1;
addr <= '0;
env_reset <= 0;
end else begin
env_reset <= 0;
if(cs & BDIR) begin
if(BC) addr <= DI;
else if(!addr[7:4]) begin
ymreg[addr[3:0]] <= DI;
env_reset <= (addr == 13);
end
end
end
end
// Read from PSG
assign DO = dout;
reg [7:0] dout;
always_comb begin
dout = 8'hFF;
if(cs & ~BDIR & BC & !addr[7:4]) begin
case(addr[3:0])
0: dout = ymreg[0];
1: dout = ymreg[1][3:0];
2: dout = ymreg[2];
3: dout = ymreg[3][3:0];
4: dout = ymreg[4];
5: dout = ymreg[5][3:0];
6: dout = ymreg[6][4:0];
7: dout = ymreg[7];
8: dout = ymreg[8][4:0];
9: dout = ymreg[9][4:0];
10: dout = ymreg[10][4:0];
11: dout = ymreg[11];
12: dout = ymreg[12];
13: dout = ymreg[13][3:0];
14: dout = ymreg[7][6] ? ymreg[14] : IOA_in;
15: dout = ymreg[7][7] ? ymreg[15] : IOB_in;
endcase
end
end
reg ena_div;
reg ena_div_noise;
// p_divider
always @(posedge CLK) begin
reg [3:0] cnt_div;
reg noise_div;
if(CE) begin
ena_div <= 0;
ena_div_noise <= 0;
if(!cnt_div) begin
cnt_div <= {SEL, 3'b111};
ena_div <= 1;
noise_div <= (~noise_div);
if (noise_div) ena_div_noise <= 1;
end else begin
cnt_div <= cnt_div - 1'b1;
end
end
end
reg [2:0] noise_gen_op;
// p_noise_gen
always @(posedge CLK) begin
reg [16:0] poly17;
reg [4:0] noise_gen_cnt;
if(CE) begin
if (ena_div_noise) begin
if (!ymreg[6][4:0] || noise_gen_cnt >= ymreg[6][4:0] - 1'd1) begin
noise_gen_cnt <= 0;
poly17 <= {(poly17[0] ^ poly17[2] ^ !poly17), poly17[16:1]};
end else begin
noise_gen_cnt <= noise_gen_cnt + 1'd1;
end
noise_gen_op <= {3{poly17[0]}};
end
end
end
wire [11:0] tone_gen_freq[1:3];
assign tone_gen_freq[1] = {ymreg[1][3:0], ymreg[0]};
assign tone_gen_freq[2] = {ymreg[3][3:0], ymreg[2]};
assign tone_gen_freq[3] = {ymreg[5][3:0], ymreg[4]};
reg [3:1] tone_gen_op;
//p_tone_gens
always @(posedge CLK) begin
integer i;
reg [11:0] tone_gen_cnt[1:3];
if(CE) begin
// looks like real chips count up - we need to get the Exact behaviour ..
for (i = 1; i <= 3; i = i + 1) begin
if(ena_div) begin
if (tone_gen_freq[i]) begin
if (tone_gen_cnt[i] >= (tone_gen_freq[i] - 1'd1)) begin
tone_gen_cnt[i] <= 0;
tone_gen_op[i] <= ~tone_gen_op[i];
end else begin
tone_gen_cnt[i] <= tone_gen_cnt[i] + 1'd1;
end
end else begin
tone_gen_op[i] <= ymreg[7][i];
tone_gen_cnt[i] <= 0;
end
end
end
end
end
reg env_ena;
wire [15:0] env_gen_comp = {ymreg[12], ymreg[11]} ? {ymreg[12], ymreg[11]} - 1'd1 : 16'd0;
//p_envelope_freq
always @(posedge CLK) begin
reg [15:0] env_gen_cnt;
if(CE) begin
env_ena <= 0;
if(ena_div) begin
if (env_gen_cnt >= env_gen_comp) begin
env_gen_cnt <= 0;
env_ena <= 1;
end else begin
env_gen_cnt <= (env_gen_cnt + 1'd1);
end
end
end
end
reg [4:0] env_vol;
wire is_bot = (env_vol == 5'b00000);
wire is_bot_p1 = (env_vol == 5'b00001);
wire is_top_m1 = (env_vol == 5'b11110);
wire is_top = (env_vol == 5'b11111);
always @(posedge CLK) begin
reg env_hold;
reg env_inc;
// envelope shapes
// C AtAlH
// 0 0 x x \___
//
// 0 1 x x /___
//
// 1 0 0 0 \\\\
//
// 1 0 0 1 \___
//
// 1 0 1 0 \/\/
// ___
// 1 0 1 1 \
//
// 1 1 0 0 ////
// ___
// 1 1 0 1 /
//
// 1 1 1 0 /\/\
//
// 1 1 1 1 /___
if(env_reset | RESET) begin
// load initial state
if(!ymreg[13][2]) begin // attack
env_vol <= 5'b11111;
env_inc <= 0; // -1
end else begin
env_vol <= 5'b00000;
env_inc <= 1; // +1
end
env_hold <= 0;
end
else if(CE) begin
if (env_ena) begin
if (!env_hold) begin
if (env_inc) env_vol <= (env_vol + 5'b00001);
else env_vol <= (env_vol + 5'b11111);
end
// envelope shape control.
if(!ymreg[13][3]) begin
if(!env_inc) begin // down
if(is_bot_p1) env_hold <= 1;
end else if (is_top) env_hold <= 1;
end else if(ymreg[13][0]) begin // hold = 1
if(!env_inc) begin // down
if(ymreg[13][1]) begin // alt
if(is_bot) env_hold <= 1;
end else if(is_bot_p1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alt
if(is_top) env_hold <= 1;
end else if(is_top_m1) env_hold <= 1;
end else if(ymreg[13][1]) begin // alternate
if(env_inc == 1'b0) begin // down
if(is_bot_p1) env_hold <= 1;
if(is_bot) begin
env_hold <= 0;
env_inc <= 1;
end
end else begin
if(is_top_m1) env_hold <= 1;
if(is_top) begin
env_hold <= 0;
env_inc <= 0;
end
end
end
end
end
end
reg [5:0] A,B,C;
always @(posedge CLK) begin
A <= {MODE, ~((ymreg[7][0] | tone_gen_op[1]) & (ymreg[7][3] | noise_gen_op[0])) ? 5'd0 : ymreg[8][4] ? env_vol[4:0] : { ymreg[8][3:0], ymreg[8][3]}};
B <= {MODE, ~((ymreg[7][1] | tone_gen_op[2]) & (ymreg[7][4] | noise_gen_op[1])) ? 5'd0 : ymreg[9][4] ? env_vol[4:0] : { ymreg[9][3:0], ymreg[9][3]}};
C <= {MODE, ~((ymreg[7][2] | tone_gen_op[3]) & (ymreg[7][5] | noise_gen_op[2])) ? 5'd0 : ymreg[10][4] ? env_vol[4:0] : {ymreg[10][3:0], ymreg[10][3]}};
end
wire [7:0] volTable[64] = '{
//YM2149
8'h00, 8'h01, 8'h01, 8'h02, 8'h02, 8'h03, 8'h03, 8'h04,
8'h06, 8'h07, 8'h09, 8'h0a, 8'h0c, 8'h0e, 8'h11, 8'h13,
8'h17, 8'h1b, 8'h20, 8'h25, 8'h2c, 8'h35, 8'h3e, 8'h47,
8'h54, 8'h66, 8'h77, 8'h88, 8'ha1, 8'hc0, 8'he0, 8'hff,
//AY8910
8'h00, 8'h00, 8'h03, 8'h03, 8'h04, 8'h04, 8'h06, 8'h06,
8'h0a, 8'h0a, 8'h0f, 8'h0f, 8'h15, 8'h15, 8'h22, 8'h22,
8'h28, 8'h28, 8'h41, 8'h41, 8'h5b, 8'h5b, 8'h72, 8'h72,
8'h90, 8'h90, 8'hb5, 8'hb5, 8'hd7, 8'hd7, 8'hff, 8'hff
};
assign CHANNEL_A = volTable[A];
assign CHANNEL_B = volTable[B];
assign CHANNEL_C = volTable[C];
endmodule

35
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/build_id.tcl Normal file
View File

@@ -0,0 +1,35 @@
# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

81
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/dpram.vhd Normal file
View File

@@ -0,0 +1,81 @@
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

84
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/gen_ram.vhd Normal file
View File

@@ -0,0 +1,84 @@
-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
-- q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
---- qReg <= ram(to_integer(unsigned(addr)));
q <= ram(to_integer(unsigned(addr)));
end if;
end process;
--q <= ram(to_integer(unsigned(addr)));
end architecture;

429
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/pll_mist.vhd Normal file
View File

@@ -0,0 +1,429 @@
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll_mist.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll_mist IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll_mist;
ARCHITECTURE SYN OF pll_mist IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire7_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
locked <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 3,
clk0_duty_cycle => 50,
clk0_multiply_by => 4,
clk0_phase_shift => "0",
clk1_divide_by => 30,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
clk2_divide_by => 3,
clk2_duty_cycle => 50,
clk2_multiply_by => 8,
clk2_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll_mist",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "OFF",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire6,
clk => sub_wire0,
locked => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "30"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1200"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "15"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "36.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "0.900000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "72.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "41"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "41"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "36.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "0.90000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "72.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_mist.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "30"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_mist_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

6
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/rom/make.bat Normal file
View File

@@ -0,0 +1,6 @@
copy /b yf-a-3p-b + yf-a-3n-b + yf-a-3m-b + yf-a-3m-b cpu.rom
copy /b yf-s.3b + yf-s.1b + yf-s.3a + yf-s.1a snd.rom
copy /b yf-a.3e + yf-a.3d + yf-a.3c gfx1.rom
copy /b yf-b.5b + yf-b.5c + yf-b.5f + yf-b.5e + yf-b.5j + yf-b.5k gfx2.rom
copy /b cpu.rom + snd.rom + gfx1.rom + gfx2.rom + yard.2n + yard.2m + yard.1c + yard.1d + yard.2h + yard.1f TENYARD.ROM

348
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/sdram.sv Normal file
View File

@@ -0,0 +1,348 @@
//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output reg [15:0] port1_q,
input [16:1] cpu1_addr,
output reg [15:0] cpu1_q,
input [16:1] cpu2_addr,
output reg [15:0] cpu2_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output reg [31:0] port2_q,
input [16:2] sp_addr,
output reg [31:0] sp_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b001; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1 - data0 read burst terminated
1 ras0
2 data1 returned
3 CAS0 data1 returned
4 RAS1 cas0
5 ras1
6 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd4; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY + 1'd1; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 6
localparam STATE_READ0 = 3'd0;// STATE_CAS0 + CAS_LATENCY + 2'd2; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_DS1b = 3'd0;
localparam STATE_READ1b = 3'd4;
localparam STATE_LAST = 3'd6;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [16:1] addr_last[2];
reg [16:2] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
reg port1_state;
reg port2_state;
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_CPU2 = 2'd2;
localparam PORT_SP = 2'd1;
localparam PORT_REQ = 2'd3;
reg [1:0] next_port[2];
reg [1:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_state) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 8'd0, cpu1_addr };
end else if (cpu2_addr != addr_last[PORT_CPU2]) begin
next_port[0] = PORT_CPU2;
addr_latch_next[0] = { 8'd0, cpu2_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT1: bank 2,3
always @(*) begin
if (port2_req ^ port2_state) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (sp_addr != addr_last2[PORT_SP]) begin
next_port[1] = PORT_SP;
addr_latch_next[1] = { 1'b1, 7'd0, sp_addr, 1'b0 };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][16:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
port1_state <= port1_req;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][16:2];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port1_we, port1_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
port2_state <= port2_req;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
PORT_CPU2: begin cpu2_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: port2_q[15:0] <= sd_din;
PORT_SP : sp_q[15:0] <= sd_din;
default: ;
endcase;
end
if(t == STATE_DS1b && oe_latch[1]) { SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if(t == STATE_READ1b && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q[31:16] <= sd_din; port2_ack <= port2_req; end
PORT_SP : begin sp_q[31:16] <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

91
Arcade_MiST/IremM58 Hardware/10-Yard Fight_MiST/rtl/spram.vhd Normal file
View File

@@ -0,0 +1,91 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
--numwords_a : natural;
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;