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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-20 09:44:38 +00:00
This commit is contained in:
Gehstock 2019-12-27 00:44:04 +01:00
parent c6d769f64a
commit cc776e79e6
6 changed files with 85 additions and 113 deletions

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@ -190,8 +190,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/LunarLander_MiST.sv
set_global_assignment -name VHDL_FILE rtl/llander_top.vhd
set_global_assignment -name VHDL_FILE rtl/llander.vhd
set_global_assignment -name VHDL_FILE rtl/llander_vg.vhd
set_global_assignment -name VHDL_FILE rtl/llander_ram.vhd
set_global_assignment -name VHDL_FILE rtl/llander_dw.vhd
set_global_assignment -name VHDL_FILE rtl/llander_ram.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/ovo.vhd

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@ -72,9 +72,9 @@ wire [7:0] audio;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
wire [12:0] cpu_rom_address;
wire [12:0] cpu_rom_addr;
wire [15:0] cpu_rom_data;
wire [12:0] vector_rom_address;
wire [12:0] vector_rom_addr;
wire [15:0] vector_rom_data;
wire ioctl_downl;
wire [7:0] ioctl_index;
@ -92,7 +92,7 @@ data_io data_io(
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
);
reg port1_req, port2_req;
sdram sdram(
@ -109,7 +109,7 @@ sdram sdram(
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 15'h7fff : {3'b000, cpu_rom_address[12:1]} ),
.cpu1_addr ( ioctl_downl ? 15'h7fff : {3'b000, cpu_rom_addr[12:1]} ),
.cpu1_q ( cpu_rom_data ),
// port2 for sound board
@ -121,9 +121,9 @@ sdram sdram(
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, vector_rom_address[12:1]} ),
.snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, vector_rom_addr[12:1]} ),
.snd_q ( vector_rom_data )
);
);
always @(posedge clk_25) begin
reg ioctl_wr_last = 0;
@ -178,11 +178,11 @@ LLANDER_TOP LLANDER_TOP (
.RESET_L(~(reset)),
.clk_6(clk_6),
.clk_25(clk_25),
.cpu_rom_address(cpu_rom_address),
.cpu_rom_data (cpu_rom_address[0] ? cpu_rom_data[15:8] : cpu_rom_data[7:0] ),
.vector_rom_address(vector_rom_address),
.vector_rom_data (vector_rom_address[0] ? vector_rom_data[15:8] : vector_rom_data[7:0] )
);
.cpu_rom_addr(cpu_rom_addr),
.cpu_rom_data (cpu_rom_addr[0] ? cpu_rom_data[15:8] : cpu_rom_data[7:0] ),
.vector_rom_addr(vector_rom_addr),
.vector_rom_data (vector_rom_addr[0] ? vector_rom_data[15:8] : vector_rom_data[7:0])
);
ovo #(
.COLS(1),
@ -207,7 +207,7 @@ diff (
.ena(diff_count > 0),
.in0(difficulty),
.in1()
);
);
reg [7:0] thrust = 0;

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@ -85,10 +85,10 @@ entity LLander is
Z_VECTOR : out std_logic_vector(3 downto 0);
BEAM_ON : out std_logic;
BEAM_ENA : out std_logic;
cpu_rom_address : out std_logic_vector(12 downto 0);
cpu_rom_data : in std_logic_vector( 7 downto 0);
vector_rom_address : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector( 7 downto 0)
cpu_rom_addr : out std_logic_vector(12 downto 0);
cpu_rom_data : in std_logic_vector( 7 downto 0);
vector_rom_addr : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector( 7 downto 0)
);
end;
@ -141,10 +141,6 @@ architecture RTL of LLander is
signal halt : std_logic;
-- memory
signal rom0_dout : std_logic_vector(7 downto 0);
signal rom1_dout : std_logic_vector(7 downto 0);
signal rom2_dout : std_logic_vector(7 downto 0);
signal rom3_dout : std_logic_vector(7 downto 0);
signal rom_dout : std_logic_vector(7 downto 0);
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_dout : std_logic_vector(7 downto 0);
@ -441,7 +437,7 @@ begin
-- data => rom_dout
--);
cpu_rom_address <= c_addr(12 downto 0);
cpu_rom_addr <= c_addr(12 downto 0);
rom_dout <= cpu_rom_data;
RAM: Entity work.gen_ram
@ -603,7 +599,7 @@ end process;
RESET_L => reset_l,
CLK_6 => CLK_6,
CLK_25 => CLK_25,
vector_rom_address => vector_rom_address,
vector_rom_addr => vector_rom_addr,
vector_rom_data => vector_rom_data
);

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@ -64,7 +64,6 @@ library ieee;
entity LLANDER_TOP is
port (
ROT_LEFT_L : in std_logic;
ROT_RIGHT_L : in std_logic;
ABORT_L : in std_logic;
@ -86,67 +85,44 @@ entity LLANDER_TOP is
LAMP5 : out std_logic;
AUDIO_OUT : out std_logic_vector(7 downto 0);
VIDEO_R_OUT : out std_logic_vector(3 downto 0);
VIDEO_G_OUT : out std_logic_vector(3 downto 0);
VIDEO_B_OUT : out std_logic_vector(3 downto 0);
AUDIO_OUT : out std_logic_vector(7 downto 0);
VIDEO_R_OUT : out std_logic_vector(3 downto 0);
VIDEO_G_OUT : out std_logic_vector(3 downto 0);
VIDEO_B_OUT : out std_logic_vector(3 downto 0);
HSYNC_OUT : out std_logic;
VSYNC_OUT : out std_logic;
VGA_DE : out std_logic;
VID_HBLANK : out std_logic;
VID_VBLANK : out std_logic;
HSYNC_OUT : out std_logic;
VSYNC_OUT : out std_logic;
VGA_DE : out std_logic;
VID_HBLANK : out std_logic;
VID_VBLANK : out std_logic;
DIP : in std_logic_vector(7 downto 0);
DIP : in std_logic_vector(7 downto 0);
RESET_L : in std_logic;
RESET_L : in std_logic;
-- ref clock in
clk_6 : in std_logic;
clk_25 : in std_logic;
cpu_rom_address : out std_logic_vector(12 downto 0);
cpu_rom_data : in std_logic_vector(7 downto 0);
vector_rom_address : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector(7 downto 0)
);
-- ref clock in
clk_6 : in std_logic;
clk_25 : in std_logic;
cpu_rom_addr : out std_logic_vector(12 downto 0);
cpu_rom_data : in std_logic_vector(7 downto 0);
vector_rom_addr : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector(7 downto 0)
);
end;
architecture RTL of LLANDER_TOP is
signal RAM_ADDR_A : std_logic_vector(18 downto 0);
signal RAM_ADDR_B : std_logic_vector(15 downto 0); -- same as above
signal RAM_WE_L : std_logic;
signal RAM_ADV_L : std_logic;
signal RAM_OE_L : std_logic;
signal RAM_DO : std_logic_vector(31 downto 0);
signal RAM_DI : std_logic_vector(31 downto 0);
signal ram_we : std_logic;
signal reset_dll_h : std_logic;
signal delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal reset_6_l : std_logic;
signal reset_6 : std_logic;
signal clk_cnt : std_logic_vector(2 downto 0) := "000";
signal x_vector : std_logic_vector(9 downto 0);
signal y_vector : std_logic_vector(9 downto 0);
signal y_vector_w_offset : std_logic_vector(9 downto 0);
signal y_vector_w_offset : std_logic_vector(9 downto 0);
signal z_vector : std_logic_vector(3 downto 0);
signal beam_on : std_logic;
signal beam_ena : std_logic;
signal ram_addr_int : std_logic_vector(18 downto 0);
signal ram_we_l_int : std_logic;
signal ram_adv_l_int : std_logic;
signal ram_oe_l_int : std_logic;
signal ram_dout_oe_l : std_logic;
signal ram_dout_oe_l_reg : std_logic;
signal ram_dout : std_logic_vector(31 downto 0);
signal ram_dout_reg : std_logic_vector(31 downto 0);
signal ram_din : std_logic_vector(31 downto 0);
begin
--
@ -176,62 +152,62 @@ begin
LLander: entity work.llander
port map(
clk_6 => clk_6,
clk_25 => clk_25,
reset_6_l => reset_6_l,
clk_6 => clk_6,
clk_25 => clk_25,
reset_6_l => reset_6_l,
dip => DIP,
rot_left_l => rot_left_l,
rot_right_l => rot_right_l,
abort_l => abort_l,
game_sel_l => game_sel_l,
start_l => start_l,
coin1_l => coin1_l,
coin2_l => coin2_l,
thrust => thrust,
diag_step_l => diag_step_l,
slam_l => '1', --switches(15),
self_test_l =>self_test_l,
start_sel_l => start_sel_l,
lamp2 => lamp2,
lamp3 => lamp3,
lamp4 => lamp4,
lamp5 => lamp5,
coin_ctr => open,
audio_out => AUDIO_OUT,
x_vector => x_vector,
y_vector => y_vector,
z_vector => z_vector,
beam_on => beam_on,
BEAM_ENA => beam_ena,
cpu_rom_address => cpu_rom_address,
cpu_rom_data => cpu_rom_data,
vector_rom_address => vector_rom_address,
vector_rom_data => vector_rom_data
rot_left_l => rot_left_l,
rot_right_l => rot_right_l,
abort_l => abort_l,
game_sel_l => game_sel_l,
start_l => start_l,
coin1_l => coin1_l,
coin2_l => coin2_l,
thrust => thrust,
diag_step_l => diag_step_l,
slam_l => '1', --switches(15),
self_test_l => self_test_l,
start_sel_l => start_sel_l,
lamp2 => lamp2,
lamp3 => lamp3,
lamp4 => lamp4,
lamp5 => lamp5,
coin_ctr => open,
audio_out => AUDIO_OUT,
x_vector => x_vector,
y_vector => y_vector,
z_vector => z_vector,
beam_on => beam_on,
BEAM_ENA => beam_ena,
cpu_rom_addr => cpu_rom_addr,
cpu_rom_data => cpu_rom_data,
vector_rom_addr => vector_rom_addr,
vector_rom_data => vector_rom_data
);
y_vector_w_offset<= y_vector+100;
u_DW : entity work.LLANDER_DW
port map (
RESET => reset_6,
RESET => reset_6,
clk_25 => clk_25,
clk_6 => clk_6,
X_VECTOR => x_vector,
Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector,
Z_VECTOR => z_vector,
X_VECTOR => x_vector,
Y_VECTOR => y_vector_w_offset,-- AJS move up y_vector,
Z_VECTOR => z_vector,
BEAM_ON => beam_on,
BEAM_ENA => beam_ena,
BEAM_ON => beam_on,
BEAM_ENA => beam_ena,
VIDEO_R_OUT => VIDEO_R_OUT,
VIDEO_G_OUT => VIDEO_G_OUT,
VIDEO_B_OUT => VIDEO_B_OUT,
HSYNC_OUT => HSYNC_OUT,
VSYNC_OUT => VSYNC_OUT,
VIDEO_R_OUT => VIDEO_R_OUT,
VIDEO_G_OUT => VIDEO_G_OUT,
VIDEO_B_OUT => VIDEO_B_OUT,
HSYNC_OUT => HSYNC_OUT,
VSYNC_OUT => VSYNC_OUT,
VID_DE => VGA_DE,
VID_HBLANK => VID_HBLANK,
VID_VBLANK => VID_VBLANK
VID_HBLANK => VID_HBLANK,
VID_VBLANK => VID_VBLANK
);

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@ -72,8 +72,8 @@ entity LLANDER_VG is
RESET_L : in std_logic;
CLK_6 : in std_logic;
Clk_25 : in std_logic;
vector_rom_address : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector( 7 downto 0)
vector_rom_addr : out std_logic_vector(12 downto 0);
vector_rom_data : in std_logic_vector( 7 downto 0)
);
end;
@ -456,7 +456,7 @@ begin
-- data => rom_dout
--);
vector_rom_address <= am_bus(12 downto 0);
vector_rom_addr <= am_bus(12 downto 0);
rom_dout <= vector_rom_data;
p_memory_data_mux : process(vram1_t1_l, vram2_t1_l, vrom_t1_l, ram_dout_1, ram_dout_2, rom_dout)