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MiST: replace rgb2ypbpr
This commit is contained in:
Gyorgy Szombathelyi
@@ -5,6 +5,6 @@ set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) mist_vi
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) scandoubler.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) osd.v]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) arcade_inputs.v]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.sv]
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set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) rgb2ypbpr.v]
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set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) cofi.sv]
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set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) dac.vhd]
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@@ -166,25 +166,26 @@ cofi cofi (
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.blue_out( cofi_b )
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);
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wire [5:0] y, pb, pr;
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wire hs, vs;
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rgb2ypbpr rgb2ypbpr
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RGBtoYPbPr #(6) rgb2ypbpr
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(
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.red ( cofi_r ),
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.green ( cofi_g ),
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.blue ( cofi_b ),
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.y ( y ),
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.pb ( pb ),
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.pr ( pr )
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.clk ( clk_sys ),
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.ena ( ypbpr ),
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.red_in ( cofi_r ),
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.green_in ( cofi_g ),
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.blue_in ( cofi_b ),
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.hs_in ( cofi_hs ),
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.vs_in ( cofi_vs ),
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.red_out ( VGA_R ),
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.green_out ( VGA_G ),
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.blue_out ( VGA_B ),
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.hs_out ( hs ),
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.vs_out ( vs )
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);
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assign VGA_R = ypbpr?pr:cofi_r;
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assign VGA_G = ypbpr? y:cofi_g;
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assign VGA_B = ypbpr?pb:cofi_b;
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wire cs = SYNC_AND ? (cofi_hs & cofi_vs) : ~(cofi_hs ^ cofi_vs);
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wire hs = cofi_hs;
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wire vs = cofi_vs;
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wire cs = SYNC_AND ? (hs & vs) : ~(hs ^ vs);
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// a minimig vga->scart cable expects a composite sync signal on the VGA_HS output.
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// and VCC on VGA_VS (to switch into rgb mode)
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@@ -1,55 +0,0 @@
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module rgb2ypbpr (
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input [5:0] red,
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input [5:0] green,
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input [5:0] blue,
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output [5:0] y,
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output [5:0] pb,
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output [5:0] pr
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);
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wire [5:0] yuv_full[225] = '{
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6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1,
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6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4,
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6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6,
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6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8,
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6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
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6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
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6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
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6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
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6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
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6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
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6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
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6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
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6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
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6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
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6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
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6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
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6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
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6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
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6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
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6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
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6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
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6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
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6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
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6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
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6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
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6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
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6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
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6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
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6'd63
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};
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wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
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wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
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wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
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wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8];
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wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
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wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
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assign pr = yuv_full[pr_i - 8'd16];
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assign y = yuv_full[y_i - 8'd16];
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assign pb = yuv_full[pb_i - 8'd16];
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endmodule
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103
common/mist/rgb2ypbpr.v
Normal file
103
common/mist/rgb2ypbpr.v
Normal file
@@ -0,0 +1,103 @@
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// Multiplier-based RGB -> YPbPr conversion
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// Copyright 2020/2021 by Alastair M. Robinson
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module RGBtoYPbPr
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(
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input clk,
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input ena,
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input [WIDTH-1:0] red_in,
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input [WIDTH-1:0] green_in,
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input [WIDTH-1:0] blue_in,
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input hs_in,
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input vs_in,
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input cs_in,
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input pixel_in,
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output [WIDTH-1:0] red_out,
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output [WIDTH-1:0] green_out,
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output [WIDTH-1:0] blue_out,
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output reg hs_out,
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output reg vs_out,
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output reg cs_out,
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output reg pixel_out
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);
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parameter WIDTH = 8;
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reg [8+WIDTH-1:0] r_y;
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reg [8+WIDTH-1:0] g_y;
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reg [8+WIDTH-1:0] b_y;
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reg [8+WIDTH-1:0] r_b;
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reg [8+WIDTH-1:0] g_b;
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reg [8+WIDTH-1:0] b_b;
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reg [8+WIDTH-1:0] r_r;
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reg [8+WIDTH-1:0] g_r;
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reg [8+WIDTH-1:0] b_r;
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reg [8+WIDTH-1:0] y;
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reg [8+WIDTH-1:0] b;
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reg [8+WIDTH-1:0] r;
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reg hs_d;
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reg vs_d;
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reg cs_d;
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reg pixel_d;
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assign red_out = r[8+WIDTH-1:8];
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assign green_out = y[8+WIDTH-1:8];
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assign blue_out = b[8+WIDTH-1:8];
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// Multiply in the first stage...
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always @(posedge clk) begin
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hs_d <= hs_in; // Register sync, pixel clock, etc
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vs_d <= vs_in; // so they're delayed the same amount as the incoming video
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cs_d <= cs_in;
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pixel_d <= pixel_in;
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if(ena) begin
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// (Y = 0.299*R + 0.587*G + 0.114*B)
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r_y <= red_in * 8'd76;
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g_y <= green_in * 8'd150;
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b_y <= blue_in * 8'd29;
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// (Pb = -0.169*R - 0.331*G + 0.500*B)
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r_b <= red_in * 8'd43;
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g_b <= green_in * 8'd84;
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b_b <= blue_in * 8'd128;
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// (Pr = 0.500*R - 0.419*G - 0.081*B)
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r_r <= red_in * 8'd128;
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g_r <= green_in * 8'd107;
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b_r <= blue_in * 8'd20;
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end else begin
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r_r[8+WIDTH-1:8] <= red_in; // Passthrough
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g_y[8+WIDTH-1:8] <= green_in;
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b_b[8+WIDTH-1:8] <= blue_in;
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end
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end
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// Second stage - adding
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always @(posedge clk) begin
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hs_out <= hs_d;
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vs_out <= vs_d;
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cs_out <= cs_d;
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pixel_out <= pixel_d;
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if(ena) begin
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y <= r_y + g_y + b_y;
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b <= 2'd2**(8+WIDTH-1) + b_b - r_b - g_b;
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r <= 2'd2**(8+WIDTH-1) + r_r - g_r - b_r;
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end else begin
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y <= g_y; // Passthrough
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b <= b_b;
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r <= r_r;
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end
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end
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endmodule
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