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Add SG1000(Not Working)

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Gehstock 2018-09-21 22:22:18 +02:00
parent 52e852733c
commit d39aad126e
31 changed files with 5887 additions and 0 deletions
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BIN
Sega - SG1000/Snapshot/sg1000_mist.rbf Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del *.cdf
del *.rpt
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY dpram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED";
outdata_reg_b : string := "UNREGISTERED"
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock_a : IN STD_LOGIC ;
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren_a : IN STD_LOGIC := '1';
wren_b : IN STD_LOGIC := '1';
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END dpram;
ARCHITECTURE SYN OF dpram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(width_a-1 DOWNTO 0);
q_b <= sub_wire1(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
numwords_b => 2**widthad_a,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => outdata_reg_a,
outdata_reg_b => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
widthad_b => widthad_a,
width_a => width_a,
width_b => width_a,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg is
port (clk : in STD_LOGIC;
WR_n : in STD_LOGIC;
D_in : in STD_LOGIC_VECTOR (7 downto 0);
outputs: out STD_LOGIC_VECTOR (5 downto 0)
);
end psg;
architecture rtl of psg is
signal clk_divide : unsigned(5 downto 0) := "000000";
signal clk32 : std_logic;
signal regn : std_logic_vector(2 downto 0);
signal tone0 : std_logic_vector(9 downto 0):="0000100000";
signal tone1 : std_logic_vector(9 downto 0):="0000100000";
signal tone2 : std_logic_vector(9 downto 0):="0000100000";
signal ctrl3 : std_logic_vector(2 downto 0):="100";
signal volume0 : std_logic_vector(3 downto 0):="1111";
signal volume1 : std_logic_vector(3 downto 0):="1111";
signal volume2 : std_logic_vector(3 downto 0):="1111";
signal volume3 : std_logic_vector(3 downto 0):="1111";
signal output0 : std_logic_vector(3 downto 0);
signal output1 : std_logic_vector(3 downto 0);
signal output2 : std_logic_vector(3 downto 0);
signal output3 : std_logic_vector(3 downto 0);
-- signal outputs : std_logic_vector(5 downto 0);
component psg_tone is
port (clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component psg_noise is
port (clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component dac is
port (clk : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (5 downto 0);
output: out STD_LOGIC);
end component;
begin
t0: psg_tone
port map (
clk => clk32,
tone => tone0,
volume => volume0,
output => output0);
t1: psg_tone
port map (
clk => clk32,
tone => tone1,
volume => volume1,
output => output1);
t2: psg_tone
port map (
clk => clk32,
tone => tone2,
volume => volume2,
output => output2);
t3: psg_noise
port map(
clk => clk32,
style => ctrl3,
tone => tone2,
volume => volume3,
output => output3);
process (clk)
begin
if rising_edge(clk) then
clk_divide <= clk_divide+1;
end if;
end process;
clk32 <= std_logic(clk_divide(5));
process (clk, WR_n)
begin
if rising_edge(clk) and WR_n='0' then
if D_in(7)='1' then
case D_in(6 downto 4) is
when "000" => tone0(3 downto 0) <= D_in(3 downto 0);
when "010" => tone1(3 downto 0) <= D_in(3 downto 0);
when "100" => tone2(3 downto 0) <= D_in(3 downto 0);
when "110" => ctrl3 <= D_in(2 downto 0);
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
regn <= D_in(6 downto 4);
else
case regn is
when "000" => tone0(9 downto 4) <= D_in(5 downto 0);
when "010" => tone1(9 downto 4) <= D_in(5 downto 0);
when "100" => tone2(9 downto 4) <= D_in(5 downto 0);
when "110" =>
when "001" => volume0 <= D_in(3 downto 0);
when "011" => volume1 <= D_in(3 downto 0);
when "101" => volume2 <= D_in(3 downto 0);
when "111" => volume3 <= D_in(3 downto 0);
when others =>
end case;
end if;
end if;
end process;
outputs <= std_logic_vector(
unsigned("00"&output0)
+ unsigned("00"&output1)
+ unsigned("00"&output2)
+ unsigned("00"&output3)
);
end rtl;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_noise is
port (
clk : in STD_LOGIC;
style : in STD_LOGIC_VECTOR (2 downto 0);
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume : in STD_LOGIC_VECTOR (3 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end psg_noise;
architecture rtl of psg_noise is
signal counter : unsigned(9 downto 0);
signal v : std_logic;
signal shift : std_logic_vector(15 downto 0) := "1000000000000000";
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000001" then
v <= not v;
case style(1 downto 0) is
when "00" => counter <= "0000010000";
when "01" => counter <= "0000100000";
when "10" => counter <= "0001000000";
when "11" => counter <= unsigned(tone);
when others =>
end case;
else
counter <= counter-1;
end if;
end if;
end process;
process (v)
variable feedback: std_logic;
begin
if rising_edge(v) then
if (style(2)='1') then
feedback := shift(0) xor shift(3);
else
feedback := shift(0);
end if;
shift <= feedback & shift(15 downto 1);
end if;
end process;
output <= (shift(0)&shift(0)&shift(0)&shift(0)) or volume;
end rtl;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity psg_tone is
Port (
clk : in STD_LOGIC;
tone : in STD_LOGIC_VECTOR (9 downto 0);
volume: in STD_LOGIC_VECTOR (3 downto 0);
output: out STD_LOGIC_VECTOR (3 downto 0));
end psg_tone;
architecture rtl of psg_tone is
signal counter : unsigned(9 downto 0) := (0=>'1', others=>'0');
signal v : std_logic := '0';
begin
process (clk, tone)
begin
if rising_edge(clk) then
if counter="000000000" then
v <= not v;
counter <= unsigned(tone);
else
counter <= counter-1;
end if;
end if;
end process;
output <= (v&v&v&v) or volume;
end rtl;

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module sg1000_top(
input RESET_n,
input sys_clk,
input clk_vdp,
input pause,
input [7:0] Cart_In,
output [7:0] Cart_Out,
output [14:0] Cart_Addr,
output x,
output y,
output vblank,
output hblank,
output [7:0] color,
input [7:0] Joy_A,
input [7:0] Joy_B
);
wire WAIT_n, MREQ_n, M1_n, IORQ_n, RFSH_n, INT_n;
wire NMI_n = pause;//go to M1_n and generate CS_PSG_n
wire RD_n, WR_n;
wire [7:0]D_in, D_out, RAM_D_out;
wire [15:0]Addr;
T80se #(
.Mode(0),
.T2Write(0),
.IOWait(1))
CPU (
.RESET_n(RESET_n),
.CLK_n(sys_clk),
.CLKEN(1'b1),
.WAIT_n(1'b1),
.INT_n(INT_n),
.NMI_n(NMI_n),
.BUSRQ_n(),//?
.M1_n(M1_n),
.MREQ_n(MREQ_n),
.IORQ_n(IORQ_n),
.RD_n(RD_n),
.WR_n(WR_n),
.RFSH_n(RFSH_n),
.HALT_n(WAIT_n),
.BUSAK_n(),
.A(Addr),
.DI(D_in),
.DO(D_out)
);
spram #(
.widthad_a(10),
.width_a(8))
MRAM (
.address(Addr[9:0]),
.clock(sys_clk),
.data(D_out),
.wren(WR_n),
.q(RAM_D_out)
);
assign Cart_Addr = Addr[14:0];
spram #(
.widthad_a(15),
.width_a(8))
CART (
.address(Cart_Addr),
.clock(sys_clk),
.data(Cart_In),
.wren(WR_n),
.q(Cart_Out)
);
wire [5:0]audio;
psg PSG (
.clk(sys_clk),
.WR_n(WR_n),
.D_in(D_out),
.outputs(audio)
);
wire [7:0]vdp_D_out;
vdp vdp (
.cpu_clk(sys_clk),
.vdp_clk(clk_vdp),
.RD_n(VDP_RD_n),
.WR_n(VDP_WR_n),
.IRQ_n(IORQ_n),
.A(Addr[7:0]),
.D_in(D_out),
.D_out(vdp_D_out),
.x(x),
.y(y),
.vblank(vblank),
.hblank(hblank),
.color(color)
);
wire CS_WRAM_n = (~MREQ_n & Addr[15:14] == "11") ? 1'b0 : 1'b1;
wire EXM1_n = (~MREQ_n & Addr[15:14] == "10") ? 1'b0 : 1'b1;
wire EXM2_n = (~MREQ_n | Addr[15]) ? 1'b0 : 1'b1;
wire CS_PSG_n = (~IORQ_n & Addr[7:6] == "01") ? 1'b0 : 1'b1;
wire VDP_RD_n = (~IORQ_n & Addr[7:6] == "10") | RD_n ? 1'b0 : 1'b1;
wire VDP_WR_n = (~IORQ_n & Addr[7:6] == "10") | WR_n ? 1'b0 : 1'b1;
wire JOY_SEL_n = (~IORQ_n & Addr[7:6] == "11") | RD_n ? 1'b0 : 1'b1;
wire KB_SEL_n = (~IORQ_n & Addr[7:6] == "11") ? 1'b0 : 1'b1;
assign D_in = ~CS_WRAM_n ? RAM_D_out :
~VDP_RD_n ? vdp_D_out :
"00000000";
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY spram IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

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--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp is
port (
cpu_clk: in STD_LOGIC;
vdp_clk: in STD_LOGIC;
RD_n: in STD_LOGIC;
WR_n: in STD_LOGIC;
IRQ_n: out STD_LOGIC;
A: in STD_LOGIC_VECTOR (7 downto 0);
D_in: in STD_LOGIC_VECTOR (7 downto 0);
D_out: out STD_LOGIC_VECTOR (7 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
vblank: std_logic;
hblank: std_logic;
color: out std_logic_vector (5 downto 0));
end vdp;
architecture Behavioral of vdp is
component vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end component;
component vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in std_logic;
cpu_A: in std_logic_vector(4 downto 0);
cpu_D: in std_logic_vector(5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in std_logic_vector(4 downto 0);
vdp_D: out std_logic_vector(5 downto 0));
end component;
-- helper bits
signal data_write: std_logic;
signal address_ff: std_logic := '0';
signal to_cram: boolean := false;
-- vram and cram lines for the cpu interface
signal xram_cpu_A: std_logic_vector(13 downto 0);
signal vram_cpu_WE: std_logic;
signal cram_cpu_WE: std_logic;
signal vram_cpu_D_out: std_logic_vector(7 downto 0);
signal xram_cpu_A_incr: std_logic := '0';
-- vram and cram lines for the video interface
signal vram_vdp_A: std_logic_vector(13 downto 0);
signal vram_vdp_D: std_logic_vector(7 downto 0);
signal cram_vdp_A: std_logic_vector(4 downto 0);
signal cram_vdp_D: std_logic_vector(5 downto 0);
-- control bits
signal display_on: std_logic := '1';
signal disable_hscroll: std_logic := '0';
signal mask_column0: std_logic := '0';
signal overscan: std_logic_vector (3 downto 0) := "0000";
signal irq_frame_en: std_logic := '0';
signal irq_line_en: std_logic := '0';
signal irq_line_count: unsigned(7 downto 0) := (others=>'1');
signal bg_address: std_logic_vector (2 downto 0) := (others=>'0');
signal bg_scroll_x: unsigned(7 downto 0) := (others=>'0');
signal bg_scroll_y: unsigned(7 downto 0) := (others=>'0');
signal spr_address: std_logic_vector (5 downto 0) := (others=>'0');
signal spr_shift: std_logic := '0';
signal spr_tall: std_logic := '0';
signal spr_high_bit: std_logic := '0';
-- various counters
signal last_y0: std_logic := '0';
signal virq_flag: std_logic := '0';
signal reset_virq_flag: boolean := false;
signal irq_counter: unsigned(4 downto 0) := (others=>'0');
signal hbl_counter: unsigned(7 downto 0) := (others=>'0');
signal vbl_irq: std_logic;
signal hbl_irq: std_logic;
begin
vdp_main_inst: vdp_main
port map(
clk => vdp_clk,
vram_A => vram_vdp_A,
vram_D => vram_vdp_D,
cram_A => cram_vdp_A,
cram_D => cram_vdp_D,
x => x,
y => y,
color => color,
display_on => display_on,
mask_column0 => mask_column0,
overscan => overscan,
bg_address => bg_address,
bg_scroll_x => bg_scroll_x,
bg_scroll_y => bg_scroll_y,
disable_hscroll=>disable_hscroll,
spr_address => spr_address,
spr_high_bit => spr_high_bit,
spr_shift => spr_shift,
spr_tall => spr_tall);
vdp_vram_inst : entity work.dpram
generic map
(
init_file => "vram.hex",
widthad_a => 14
)
port map
(
clock_a => cpu_clk,
address_a => xram_cpu_A(13 downto 0),
wren_a => vram_cpu_WE,
data_a => D_in,
q_a => vram_cpu_D_out,
clock_b => not vdp_clk,
address_b => vram_vdp_A,
wren_b => '0',
data_b => (others => '0'),
q_b => vram_vdp_D
);
vdp_cram_inst: vdp_cram
port map (
cpu_clk => cpu_clk,
cpu_WE => cram_cpu_WE,
cpu_A => xram_cpu_A(4 downto 0),
cpu_D => D_in(5 downto 0),
vdp_clk => vdp_clk,
vdp_A => cram_vdp_A,
vdp_D => cram_vdp_D);
data_write <= not WR_n and not A(0);
cram_cpu_WE <= data_write when to_cram else '0';
vram_cpu_WE <= data_write when not to_cram else '0';
process (cpu_clk)
begin
if rising_edge(cpu_clk) then
if WR_n='0' then
if A(0)='0' then
xram_cpu_A_incr <= '1';
else
if address_ff='0' then
xram_cpu_A(7 downto 0) <= D_in;
else
xram_cpu_A(13 downto 8) <= D_in(5 downto 0);
to_cram <= D_in(7 downto 6)="11";
case D_in is
when "10000000" =>
disable_hscroll<= xram_cpu_A(6);
mask_column0 <= xram_cpu_A(5);
irq_line_en <= xram_cpu_A(4);
spr_shift <= xram_cpu_A(3);
when "10000001" =>
display_on <= xram_cpu_A(6);
irq_frame_en <= xram_cpu_A(5);
spr_tall <= xram_cpu_A(1);
when "10000010" =>
bg_address <= xram_cpu_A(3 downto 1);
when "10000101" =>
spr_address <= xram_cpu_A(6 downto 1);
when "10000110" =>
spr_high_bit <= xram_cpu_A(2);
when "10000111" =>
overscan <= xram_cpu_A(3 downto 0);
when "10001000" =>
bg_scroll_x <= unsigned(xram_cpu_A(7 downto 0));
when "10001001" =>
bg_scroll_y <= unsigned(xram_cpu_A(7 downto 0));
when "10001010" =>
irq_line_count <= unsigned(xram_cpu_A(7 downto 0));
when others =>
end case;
end if;
address_ff <= not address_ff;
end if;
elsif RD_n='0' then
case A(7 downto 6)&A(0) is
when "010" =>
D_out <= std_logic_vector(y);
when "011" =>
D_out <= std_logic_vector(x(7 downto 0));
when "100" =>
D_out <= vram_cpu_D_out;
xram_cpu_A_incr <= '1';
when "101" =>
D_out(7) <= virq_flag;
D_out(6 downto 0) <= (others=>'0');
reset_virq_flag <= true;
when others =>
end case;
elsif xram_cpu_A_incr='1' then
xram_cpu_A <= std_logic_vector(unsigned(xram_cpu_A) + 1);
xram_cpu_A_incr <= '0';
else
reset_virq_flag <= false;
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vblank='1' then
vbl_irq <= irq_frame_en;
else
vbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if x=256 and not (last_y0=std_logic(y(0))) then
last_y0 <= std_logic(y(0));
if y<192 then
if hbl_counter=0 then
hbl_irq <= irq_line_en;
hbl_counter <= irq_line_count;
else
hbl_counter <= hbl_counter-1;
end if;
else
hbl_counter <= irq_line_count;
end if;
else
hbl_irq <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' then
virq_flag <= '1';
elsif reset_virq_flag then
virq_flag <= '0';
end if;
end if;
end process;
process (vdp_clk)
begin
if rising_edge(vdp_clk) then
if vbl_irq='1' or hbl_irq='1' then
irq_counter <= (others=>'1');
elsif irq_counter>0 then
irq_counter <= irq_counter-1;
end if;
end if;
end process;
IRQ_n <= '0' when irq_counter>0 else '1';
end Behavioral;

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library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.ALL;
entity vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic
);
end entity;
architecture rtl of vdp_background is
signal tile_index : std_logic_vector (8 downto 0);
signal x : unsigned (7 downto 0);
signal tile_y : std_logic_vector (2 downto 0);
signal palette : std_logic;
signal priority_latch: std_logic;
signal flip_x : std_logic;
signal data0 : std_logic_vector(7 downto 0);
signal data1 : std_logic_vector(7 downto 0);
signal data2 : std_logic_vector(7 downto 0);
signal data3 : std_logic_vector(7 downto 0);
signal shift0 : std_logic_vector(7 downto 0);
signal shift1 : std_logic_vector(7 downto 0);
signal shift2 : std_logic_vector(7 downto 0);
signal shift3 : std_logic_vector(7 downto 0);
begin
process (clk) begin
if (rising_edge(clk)) then
if (reset='1') then
if disable_hscroll='0' or y>=16 then
x <= 240-scroll_x;
else
x <= "11110000"; -- 240
end if;
else
x <= x + 1;
end if;
end if;
end process;
process (clk)
variable char_address : std_logic_vector(12 downto 0);
variable data_address : std_logic_vector(11 downto 0);
begin
if (rising_edge(clk)) then
char_address(12 downto 10) := table_address;
char_address(9 downto 5) := std_logic_vector(y(7 downto 3));
char_address(4 downto 0) := std_logic_vector(x(7 downto 3) + 1);
data_address := tile_index & tile_y;
case x(2 downto 0) is
when "000" => vram_A <= char_address & "0";
when "001" => vram_A <= char_address & "1";
when "011" => vram_A <= data_address & "00";
when "100" => vram_A <= data_address & "01";
when "101" => vram_A <= data_address & "10";
when "110" => vram_A <= data_address & "11";
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "001" =>
tile_index(7 downto 0) <= vram_D;
when "010" =>
tile_index(8) <= vram_D(0);
flip_x <= vram_D(1);
tile_y(0) <= y(0) xor vram_D(2);
tile_y(1) <= y(1) xor vram_D(2);
tile_y(2) <= y(2) xor vram_D(2);
palette <= vram_D(3);
priority_latch <= vram_D(4);
when "100" =>
data0 <= vram_D;
when "101" =>
data1 <= vram_D;
when "110" =>
data2 <= vram_D;
-- when "111" =>
-- data3 <= vram_D;
when others =>
end case;
end if;
end process;
process (clk) begin
if (rising_edge(clk)) then
case x(2 downto 0) is
when "111" =>
if flip_x='0' then
shift0 <= data0;
shift1 <= data1;
shift2 <= data2;
shift3 <= vram_D;
else
shift0 <= data0(0)&data0(1)&data0(2)&data0(3)&data0(4)&data0(5)&data0(6)&data0(7);
shift1 <= data1(0)&data1(1)&data1(2)&data1(3)&data1(4)&data1(5)&data1(6)&data1(7);
shift2 <= data2(0)&data2(1)&data2(2)&data2(3)&data2(4)&data2(5)&data2(6)&data2(7);
shift3 <= vram_D(0)&vram_D(1)&vram_D(2)&vram_D(3)&vram_D(4)&vram_D(5)&vram_D(6)&vram_D(7);
end if;
color(4) <= palette;
priority <= priority_latch;
when others =>
shift0(7 downto 1) <= shift0(6 downto 0);
shift1(7 downto 1) <= shift1(6 downto 0);
shift2(7 downto 1) <= shift2(6 downto 0);
shift3(7 downto 1) <= shift3(6 downto 0);
end case;
end if;
end process;
color(0) <= shift0(7);
color(1) <= shift1(7);
color(2) <= shift2(7);
color(3) <= shift3(7);
end architecture;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_cram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in STD_LOGIC;
cpu_A: in STD_LOGIC_VECTOR (4 downto 0);
cpu_D: in STD_LOGIC_VECTOR (5 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (4 downto 0);
vdp_D: out STD_LOGIC_VECTOR (5 downto 0));
end vdp_cram;
architecture Behavioral of vdp_cram is
type t_ram is array (0 to 31) of std_logic_vector(5 downto 0);
signal ram : t_ram := (others => "111111");
begin
process (cpu_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(cpu_clk) then
if cpu_WE='1'then
i := to_integer(unsigned(cpu_A));
ram(i) <= cpu_D;
end if;
end if;
end process;
process (vdp_clk)
variable i : integer range 0 to 31;
begin
if rising_edge(vdp_clk) then
i := to_integer(unsigned(vdp_A));
vdp_D <= ram(i);
end if;
end process;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_main is
port (
clk: in std_logic;
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
cram_A: out std_logic_vector(4 downto 0);
cram_D: in std_logic_vector(5 downto 0);
x: unsigned(8 downto 0);
y: unsigned(7 downto 0);
color: out std_logic_vector (5 downto 0);
display_on: in std_logic;
mask_column0: in std_logic;
overscan: in std_logic_vector (3 downto 0);
bg_address: in std_logic_vector (2 downto 0);
bg_scroll_x: in unsigned(7 downto 0);
bg_scroll_y: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
spr_address: in std_logic_vector (5 downto 0);
spr_high_bit: in std_logic;
spr_shift: in std_logic;
spr_tall: in std_logic);
end vdp_main;
architecture Behavioral of vdp_main is
component vdp_background is
port (
clk: in std_logic;
reset: in std_logic;
table_address: in std_logic_vector(13 downto 11);
scroll_x: in unsigned(7 downto 0);
disable_hscroll: in std_logic;
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(4 downto 0);
priority: out std_logic);
end component;
component vdp_sprites is
port (
clk: in std_logic;
table_address: in std_logic_vector(13 downto 8);
char_high_bit: in std_logic;
tall: in std_logic;
x: in unsigned(8 downto 0);
y: in unsigned(7 downto 0);
vram_A: out std_logic_vector(13 downto 0);
vram_D: in std_logic_vector(7 downto 0);
color: out std_logic_vector(3 downto 0));
end component;
signal bg_y: unsigned(7 downto 0);
signal bg_vram_A: std_logic_vector(13 downto 0);
signal bg_color: std_logic_vector(4 downto 0);
signal bg_priority: std_logic;
signal spr_vram_A: std_logic_vector(13 downto 0);
signal spr_color: std_logic_vector(3 downto 0);
signal line_reset: std_logic;
begin
process (y,bg_scroll_y)
variable sum: unsigned(8 downto 0);
begin
sum := ('0'&y)+('0'&bg_scroll_y);
if (sum>=224) then
sum := sum-224;
end if;
bg_y <= sum(7 downto 0);
end process;
line_reset <= '1' when x=512-16 else '0';
vdp_bg_inst: vdp_background
port map (
clk => clk,
table_address => bg_address,
reset => line_reset,
disable_hscroll=> disable_hscroll,
scroll_x => bg_scroll_x,
y => bg_y,
vram_A => bg_vram_A,
vram_D => vram_D,
color => bg_color,
priority => bg_priority);
vdp_spr_inst: vdp_sprites
port map (
clk => clk,
table_address => spr_address,
char_high_bit => spr_high_bit,
tall => spr_tall,
x => x,
y => y,
vram_A => spr_vram_A,
vram_D => vram_D,
color => spr_color);
process (x, y, bg_priority, spr_color, bg_color, overscan)
variable spr_active : boolean;
variable bg_active : boolean;
begin
if x<256 and y<192 and (mask_column0='0' or x>=8) then
spr_active := not (spr_color="0000");
bg_active := not (bg_color(3 downto 0)="0000");
if (bg_priority='0' and spr_active) or (bg_priority='1' and not bg_active) then
cram_A <= "1"&spr_color;
else
cram_A <= bg_color;
end if;
else
cram_A <= "1"&overscan;
end if;
end process;
vram_A <= spr_vram_A when x>=256 and x<384 else bg_vram_A;
color <= cram_D;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vpd_sprite_shifter is
Port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end vpd_sprite_shifter;
architecture Behavioral of vpd_sprite_shifter is
signal count : integer range 0 to 8;
signal shift0 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift1 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift2 : std_logic_vector (7 downto 0) := (others=>'0');
signal shift3 : std_logic_vector (7 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if spr_x=x then
shift0 <= spr_d0;
shift1 <= spr_d1;
shift2 <= spr_d2;
shift3 <= spr_d3;
else
shift0 <= shift0(6 downto 0)&"0";
shift1 <= shift1(6 downto 0)&"0";
shift2 <= shift2(6 downto 0)&"0";
shift3 <= shift3(6 downto 0)&"0";
end if;
end if;
end process;
color <= shift3(7)&shift2(7)&shift1(7)&shift0(7);
active <= shift3(7) or shift2(7) or shift1(7) or shift0(7);
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vdp_sprites is
port (clk : in std_logic;
table_address : in STD_LOGIC_VECTOR (13 downto 8);
char_high_bit : in std_logic;
tall : in std_logic;
vram_A : out STD_LOGIC_VECTOR (13 downto 0);
vram_D : in STD_LOGIC_VECTOR (7 downto 0);
x : in unsigned (8 downto 0);
y : in unsigned (7 downto 0);
color : out STD_LOGIC_VECTOR (3 downto 0));
end vdp_sprites;
architecture Behavioral of vdp_sprites is
component vpd_sprite_shifter is
port( clk : in std_logic;
x : in unsigned (7 downto 0);
spr_x : in unsigned (7 downto 0);
spr_d0: in std_logic_vector (7 downto 0);
spr_d1: in std_logic_vector (7 downto 0);
spr_d2: in std_logic_vector (7 downto 0);
spr_d3: in std_logic_vector (7 downto 0);
color : out std_logic_vector (3 downto 0);
active: out std_logic);
end component;
constant WAITING: integer := 0;
constant COMPARE: integer := 1;
constant LOAD_N: integer := 2;
constant LOAD_X: integer := 3;
constant LOAD_0: integer := 4;
constant LOAD_1: integer := 5;
constant LOAD_2: integer := 6;
constant LOAD_3: integer := 7;
signal state: integer := WAITING;
signal count: integer range 0 to 7;
signal index: unsigned(5 downto 0);
signal data_address: std_logic_vector(13 downto 2);
type tenable is array (0 to 7) of boolean;
type tx is array (0 to 7) of unsigned(7 downto 0);
type tdata is array (0 to 7) of std_logic_vector(7 downto 0);
signal enable: tenable;
signal spr_x: tx;
signal spr_d0: tdata;
signal spr_d1: tdata;
signal spr_d2: tdata;
signal spr_d3: tdata;
type tcolor is array (0 to 7) of std_logic_vector(3 downto 0);
signal spr_color: tcolor;
signal active: std_logic_vector(7 downto 0);
begin
shifters:
for i in 0 to 7 generate
begin
shifter: vpd_sprite_shifter
port map(clk => clk,
x => x(7 downto 0),
spr_x => spr_x(i),
spr_d0=> spr_d0(i),
spr_d1=> spr_d1(i),
spr_d2=> spr_d2(i),
spr_d3=> spr_d3(i),
color => spr_color(i),
active=> active(i));
end generate;
with state select
vram_a <= table_address&"00"&std_logic_vector(index) when COMPARE,
table_address&"1"&std_logic_vector(index)&"1" when LOAD_N,
table_address&"1"&std_logic_vector(index)&"0" when LOAD_X,
data_address&"00" when LOAD_0,
data_address&"01" when LOAD_1,
data_address&"10" when LOAD_2,
data_address&"11" when LOAD_3,
(others=>'0') when others;
process (clk)
variable y9 : unsigned(8 downto 0);
variable d9 : unsigned(8 downto 0);
variable delta : unsigned(8 downto 0);
begin
if rising_edge(clk) then
if x=255 then
count <= 0;
enable <= (others=>false);
state <= COMPARE;
index <= (others=>'0');
else
y9 := "0"&y;
d9 := "0"&unsigned(vram_D);
if d9>=240 then
d9 := d9-256;
end if;
delta := y9-d9;
case state is
when COMPARE =>
if d9=208 then
state <= WAITING; -- stop
elsif 0<=delta and ((delta<8 and tall='0') or (delta<16 and tall='1')) then
enable(count) <= true;
data_address(5 downto 2) <= std_logic_vector(delta(3 downto 0));
state <= LOAD_N;
else
if index<63 then
index <= index+1;
else
state <= WAITING;
end if;
end if;
when LOAD_N =>
data_address(13) <= char_high_bit;
data_address(12 downto 6) <= vram_d(7 downto 1);
if tall='0' then
data_address(5) <= vram_d(0);
end if;
state <= LOAD_X;
when LOAD_X =>
spr_x(count) <= unsigned(vram_d);
state <= LOAD_0;
when LOAD_0 =>
spr_d0(count) <= vram_d;
state <= LOAD_1;
when LOAD_1 =>
spr_d1(count) <= vram_d;
state <= LOAD_2;
when LOAD_2 =>
spr_d2(count) <= vram_d;
state <= LOAD_3;
when LOAD_3 =>
spr_d3(count) <= vram_d;
if (count<7) then
state <= COMPARE;
index <= index+1;
count <= count+1;
else
state <= WAITING;
end if;
when others =>
end case;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if enable(0) and active(0)='1' then
color <= spr_color(0);
elsif enable(1) and active(1)='1' then
color <= spr_color(1);
elsif enable(2) and active(2)='1' then
color <= spr_color(2);
elsif enable(3) and active(3)='1' then
color <= spr_color(3);
elsif enable(4) and active(4)='1' then
color <= spr_color(4);
elsif enable(5) and active(5)='1' then
color <= spr_color(5);
elsif enable(6) and active(6)='1' then
color <= spr_color(6);
elsif enable(7) and active(7)='1' then
color <= spr_color(7);
else
color <= (others=>'0');
end if;
end if;
end process;
end Behavioral;

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
entity vdp_vram is
port (
cpu_clk: in STD_LOGIC;
cpu_WE: in STD_LOGIC;
cpu_A: in STD_LOGIC_VECTOR (13 downto 0);
cpu_D_in: in STD_LOGIC_VECTOR (7 downto 0);
cpu_D_out: out STD_LOGIC_VECTOR (7 downto 0);
vdp_clk: in STD_LOGIC;
vdp_A: in STD_LOGIC_VECTOR (13 downto 0);
vdp_D_out: out STD_LOGIC_VECTOR (7 downto 0));
end vdp_vram;
architecture Behavioral of vdp_vram is
begin
ram_blocks:
for b in 0 to 7 generate
begin
inst: RAMB16_S1_S1
port map (
CLKA => cpu_clk,
ADDRA => cpu_A,
DIA => cpu_D_in(b downto b),
DOA => cpu_D_out(b downto b),
ENA => '1',
SSRA => '0',
WEA => cpu_WE,
CLKB => not vdp_clk,
ADDRB => vdp_A,
DIB => "0",
DOB => vdp_D_out(b downto b),
ENB => '1',
SSRB => '0',
WEB => '0'
);
end generate;
end Behavioral;

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 20:36:09 September 21, 2018
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "20:36:09 September 21, 2018"
# Revisions
PROJECT_REVISION = "sg1000"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 20:36:09 September 21, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# sg1000_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name TOP_LEVEL_ENTITY sg1000_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:36:09 SEPTEMBER 21, 2018"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprites.vhd
set_global_assignment -name VHDL_FILE rtl/vdp/vdp_sprite_shifter.vhd
set_global_assignment -name VHDL_FILE rtl/vdp/vdp_main.vhd
set_global_assignment -name VHDL_FILE rtl/vdp/vdp_cram.vhd
set_global_assignment -name VHDL_FILE rtl/vdp/vdp_background.vhd
set_global_assignment -name VHDL_FILE rtl/vdp/vdp.vhd
set_global_assignment -name VHDL_FILE rtl/psg/psg_tone.vhd
set_global_assignment -name VHDL_FILE rtl/psg/psg_noise.vhd
set_global_assignment -name VHDL_FILE rtl/psg/psg.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80se.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/t80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sg1000_top.sv
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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