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Galaksija_MiST/Galaksija_Mist.qpf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 14:32:28  October 06, 2018
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.0"
+DATE = "14:32:28  October 06, 2018"
+
+# Revisions
+
+PROJECT_REVISION = "Galaksija_Mist"
+PROJECT_REVISION = "AtomElectron_Mist"

Galaksija_MiST/Galaksija_Mist.qsf

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+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2013 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
+# Date created = 23:16:13  October 05, 2018
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		AtomElectron_Mist_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "07:11:53  MARCH 09, 2017"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PIN_31 -to UART_RXD
+set_location_assignment PIN_46 -to UART_TXD
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY Galaksija_MiST
+set_global_assignment -name SEARCH_PATH roms/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/MC6522/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/RAM/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/T6502/ -tag from_archive
+set_global_assignment -name SEARCH_PATH src/ps2kybrd/ -tag from_archive
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name GENERATE_RBF_FILE ON
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+	# EDA Netlist Writer Assignments
+	# ==============================
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# -------------------------------
+# start ENTITY(AtomElectron_Mist)
+
+	# start DESIGN_PARTITION(Top)
+	# ---------------------------
+
+		# Incremental Compilation Assignments
+		# ===================================
+
+	# end DESIGN_PARTITION(Top)
+	# -------------------------
+
+# end ENTITY(AtomElectron_Mist)
+# -----------------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/Galaksija_MiST.sv
+set_global_assignment -name VERILOG_FILE rtl/galaksija_top.v
+set_global_assignment -name VHDL_FILE rtl/spram.vhd
+set_global_assignment -name VHDL_FILE rtl/sprom.vhd
+set_global_assignment -name VHDL_FILE rtl/dpram.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
+set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
+set_global_assignment -name VERILOG_FILE rtl/osd.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
+set_global_assignment -name VERILOG_FILE rtl/mist_io.v
+set_global_assignment -name VERILOG_FILE rtl/pll.v
+set_global_assignment -name VERILOG_FILE rtl/video.v
+set_global_assignment -name VERILOG_FILE rtl/TV80/tv80n.v
+set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_reg.v
+set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_mcode.v
+set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_core.v
+set_global_assignment -name VERILOG_FILE rtl/TV80/tv80_alu.v
+set_global_assignment -name VHDL_FILE rtl/galaksija_keyboard_v2.vhd
+set_global_assignment -name VHDL_FILE rtl/keyboard.vhd
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/ay8910.sv
+set_global_assignment -name VHDL_FILE rtl/dac.vhd
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

Galaksija_MiST/galaxy.cpp

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+// license:BSD-3-Clause
+// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic
+/***************************************************************************
+Galaksija driver by Krzysztof Strzecha and Miodrag Milanovic
+
+22/05/2008 Tape support added (Miodrag Milanovic)
+21/05/2008 Galaksija plus initial support (Miodrag Milanovic)
+20/05/2008 Added real video implementation (Miodrag Milanovic)
+18/04/2005 Possibilty to disable ROM 2. 2k, 22k, 38k and 54k memory
+       configurations added.
+13/03/2005 Memory mapping improved. Palette corrected. Supprort for newer
+           version of snapshots added. Lot of cleanups. Keyboard mapping
+           corrected.
+19/09/2002 malloc() replaced by image_malloc().
+15/09/2002 Snapshot loading fixed. Code cleanup.
+31/01/2001 Snapshot loading corrected.
+09/01/2001 Fast mode implemented (many thanks to Kevin Thacker).
+07/01/2001 Keyboard corrected (still some keys unknown).
+           Horizontal screen positioning in video subsystem added.
+05/01/2001 Keyboard implemented (some keys unknown).
+03/01/2001 Snapshot loading added.
+01/01/2001 Preliminary driver.
+
+***************************************************************************/
+
+#include "emu.h"
+#include "includes/galaxy.h"
+
+#include "cpu/z80/z80.h"
+#include "formats/gtp_cas.h"
+#include "imagedev/cassette.h"
+#include "imagedev/snapquik.h"
+#include "machine/ram.h"
+#include "sound/ay8910.h"
+#include "sound/wave.h"
+#include "emupal.h"
+#include "screen.h"
+#include "softlist.h"
+#include "speaker.h"
+
+
+void galaxy_state::galaxyp_io(address_map &map)
+{
+	map.global_mask(0x01);
+	map.unmap_value_high();
+	map(0x00, 0x00).w("ay8910", FUNC(ay8910_device::address_w));
+	map(0x01, 0x01).w("ay8910", FUNC(ay8910_device::data_w));
+}
+
+
+void galaxy_state::galaxy_mem(address_map &map)
+{
+	map(0x0000, 0x0fff).rom();
+	map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r));
+	map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w));
+}
+
+void galaxy_state::galaxyp_mem(address_map &map)
+{
+	map(0x0000, 0x0fff).rom(); // ROM A
+	map(0x1000, 0x1fff).rom(); // ROM B
+	map(0x2000, 0x2037).mirror(0x07c0).r(FUNC(galaxy_state::galaxy_keyboard_r));
+	map(0x2038, 0x203f).mirror(0x07c0).w(FUNC(galaxy_state::galaxy_latch_w));
+	map(0xe000, 0xefff).rom(); // ROM C
+	map(0xf000, 0xffff).rom(); // ROM D
+}
+
+/* 2008-05 FP:
+Small note about natural keyboard support. Currently:
+- "List" is mapped to 'ESC'
+- "Break" is mapped to 'F1'
+- "Repeat" is mapped to 'F2'                           */
+
+static INPUT_PORTS_START (galaxy_common)
+	PORT_START("LINE0")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_A)       PORT_CHAR('A')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_B)       PORT_CHAR('B')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_C)       PORT_CHAR('C')
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_D)       PORT_CHAR('D')
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_E)       PORT_CHAR('E')
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_F)       PORT_CHAR('F')
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_G)       PORT_CHAR('G')
+
+	PORT_START("LINE1")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_H)       PORT_CHAR('H')
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_I)       PORT_CHAR('I')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_J)       PORT_CHAR('J')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_K)       PORT_CHAR('K')
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_L)       PORT_CHAR('L')
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_M)       PORT_CHAR('M')
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_N)       PORT_CHAR('N')
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_O)       PORT_CHAR('O')
+
+	PORT_START("LINE2")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_P)       PORT_CHAR('P')
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Q)       PORT_CHAR('Q')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_R)       PORT_CHAR('R')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_S)       PORT_CHAR('S')
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_T)       PORT_CHAR('T')
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_U)       PORT_CHAR('U')
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_V)       PORT_CHAR('V')
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_W)       PORT_CHAR('W')
+
+	PORT_START("LINE3")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_X)       PORT_CHAR('X')
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Y)       PORT_CHAR('Y')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_Z)       PORT_CHAR('Z')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_UP)      PORT_CHAR(UCHAR_MAMEKEY(UP))
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_DOWN)    PORT_CHAR(UCHAR_MAMEKEY(DOWN))
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LEFT)    PORT_CHAR(UCHAR_MAMEKEY(LEFT))
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_RIGHT)   PORT_CHAR(UCHAR_MAMEKEY(RIGHT))
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SPACE)   PORT_CHAR(' ')
+
+	PORT_START("LINE4")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_0)       PORT_CHAR('0') PORT_CHAR('_')
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_1)       PORT_CHAR('1') PORT_CHAR('!')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_2)       PORT_CHAR('2') PORT_CHAR('"')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_3)       PORT_CHAR('3') PORT_CHAR('#')
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_4)       PORT_CHAR('4') PORT_CHAR('$')
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_5)       PORT_CHAR('5') PORT_CHAR('%')
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_6)       PORT_CHAR('6') PORT_CHAR('&')
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_7)       PORT_CHAR('7') PORT_CHAR('\'')
+
+	PORT_START("LINE5")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_8)       PORT_CHAR('8') PORT_CHAR('(')
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_9)       PORT_CHAR('9') PORT_CHAR(')')
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COLON)   PORT_CHAR(';') PORT_CHAR('+')
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_QUOTE)   PORT_CHAR(':') PORT_CHAR('*')
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_COMMA)   PORT_CHAR(',') PORT_CHAR('<')
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_EQUALS)  PORT_CHAR('=') PORT_CHAR('-')
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_STOP)    PORT_CHAR('.') PORT_CHAR('>')
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_SLASH)   PORT_CHAR('/') PORT_CHAR('?')
+
+	PORT_START("LINE6")
+		PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_ENTER)   PORT_CHAR(13)
+		PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Break") PORT_CODE(KEYCODE_PAUSE) PORT_CHAR(UCHAR_MAMEKEY(F1))
+		PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Repeat") PORT_CODE(KEYCODE_LALT) PORT_CHAR(UCHAR_MAMEKEY(F2))
+		PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("Delete") PORT_CODE(KEYCODE_BACKSPACE) PORT_CHAR(8)
+		PORT_BIT(0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_NAME("List") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
+		PORT_BIT(0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD) PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
+		PORT_BIT(0x40, IP_ACTIVE_HIGH, IPT_UNUSED)
+		PORT_BIT(0x80, IP_ACTIVE_HIGH, IPT_UNUSED)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( galaxy )
+	PORT_INCLUDE( galaxy_common )
+	PORT_START("ROM2")
+		PORT_CONFNAME(0x01, 0x01, "ROM 2")
+			PORT_CONFSETTING(0x01, "Installed")
+			PORT_CONFSETTING(0x00, "Not installed")
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( galaxyp )
+	PORT_INCLUDE( galaxy_common )
+INPUT_PORTS_END
+
+#define XTAL 6144000
+
+/* F4 Character Displayer */
+static const gfx_layout galaxy_charlayout =
+{
+	8, 16,                  /* 8 x 16 characters */
+	128,                    /* 128 characters */
+	1,                  /* 1 bits per pixel */
+	{ 0 },                  /* no bitplanes */
+	/* x offsets */
+	{ 7, 6, 5, 4, 3, 2, 1, 0 },
+	/* y offsets */
+	{ 0, 1*128*8, 2*128*8, 3*128*8, 4*128*8, 5*128*8, 6*128*8, 7*128*8, 8*128*8, 9*128*8, 10*128*8, 11*128*8, 12*128*8, 13*128*8, 14*128*8, 15*128*8 },
+	8                   /* every char takes 1 x 16 bytes */
+};
+
+static GFXDECODE_START( gfx_galaxy )
+	GFXDECODE_ENTRY( "gfx1", 0x0000, galaxy_charlayout, 0, 1 )
+GFXDECODE_END
+
+
+MACHINE_CONFIG_START(galaxy_state::galaxy)
+	/* basic machine hardware */
+	MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2)
+	MCFG_DEVICE_PROGRAM_MAP(galaxy_mem)
+	MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state,  galaxy_interrupt)
+	MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback)
+
+	MCFG_SCREEN_ADD("screen", RASTER)
+	MCFG_SCREEN_REFRESH_RATE(50)
+	MCFG_SCREEN_PALETTE("palette")
+
+	MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxy )
+
+	/* video hardware */
+	MCFG_SCREEN_SIZE(384, 212)
+	MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1)
+	MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy)
+
+	MCFG_DEVICE_ADD("gfxdecode", GFXDECODE, "palette", gfx_galaxy)
+	MCFG_PALETTE_ADD_MONOCHROME("palette")
+
+
+	/* snapshot */
+	MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0)
+
+	SPEAKER(config, "mono").front_center();
+	WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25);
+
+	MCFG_CASSETTE_ADD( "cassette" )
+	MCFG_CASSETTE_FORMATS(gtp_cassette_formats)
+	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED)
+	MCFG_CASSETTE_INTERFACE("galaxy_cass")
+
+	MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy")
+
+	/* internal ram */
+	RAM(config, RAM_TAG).set_default_size("6K").set_extra_options("2K,22K,38K,54K");
+MACHINE_CONFIG_END
+
+MACHINE_CONFIG_START(galaxy_state::galaxyp)
+	/* basic machine hardware */
+	MCFG_DEVICE_ADD("maincpu", Z80, XTAL / 2)
+	MCFG_DEVICE_PROGRAM_MAP(galaxyp_mem)
+	MCFG_DEVICE_IO_MAP(galaxyp_io)
+	MCFG_DEVICE_VBLANK_INT_DRIVER("screen", galaxy_state,  galaxy_interrupt)
+	MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(galaxy_state,galaxy_irq_callback)
+
+	MCFG_SCREEN_ADD("screen", RASTER)
+	MCFG_SCREEN_REFRESH_RATE(50)
+	MCFG_SCREEN_PALETTE("palette")
+
+	MCFG_MACHINE_RESET_OVERRIDE(galaxy_state, galaxyp )
+
+	/* video hardware */
+	MCFG_SCREEN_SIZE(384, 208)
+	MCFG_SCREEN_VISIBLE_AREA(0, 384-1, 0, 208-1)
+	MCFG_SCREEN_UPDATE_DRIVER(galaxy_state, screen_update_galaxy)
+
+	MCFG_PALETTE_ADD_MONOCHROME("palette")
+
+
+	/* snapshot */
+	MCFG_SNAPSHOT_ADD("snapshot", galaxy_state, galaxy, "gal", 0)
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+	MCFG_DEVICE_ADD("ay8910", AY8910, XTAL/4) // FIXME: really no output routes for this AY?
+	WAVE(config, "wave", "cassette").add_route(ALL_OUTPUTS, "mono", 0.25);
+
+	MCFG_CASSETTE_ADD( "cassette" )
+	MCFG_CASSETTE_FORMATS(gtp_cassette_formats)
+	MCFG_CASSETTE_DEFAULT_STATE(CASSETTE_STOPPED | CASSETTE_SPEAKER_ENABLED | CASSETTE_MOTOR_ENABLED)
+	MCFG_CASSETTE_INTERFACE("galaxy_cass")
+
+	MCFG_SOFTWARE_LIST_ADD("cass_list","galaxy")
+
+	/* internal ram */
+	RAM(config, RAM_TAG).set_default_size("38K");
+MACHINE_CONFIG_END
+
+ROM_START (galaxy)
+	ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF)
+	ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739))
+	ROM_LOAD_OPTIONAL ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1))
+	ROM_REGION(0x0800, "gfx1",0)
+	ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88))
+ROM_END
+
+ROM_START (galaxyp)
+	ROM_REGION (0x10000, "maincpu", ROMREGION_ERASEFF)
+	ROM_LOAD ("galrom1.bin", 0x0000, 0x1000, CRC(dc970a32) SHA1(dfc92163654a756b70f5a446daf49d7534f4c739))
+	ROM_LOAD ("galrom2.bin", 0x1000, 0x1000, CRC(5dc5a100) SHA1(5d5ab4313a2d0effe7572bb129193b64cab002c1))
+	ROM_LOAD ("galplus.bin", 0xe000, 0x1000, CRC(d4cfab14) SHA1(b507b9026844eeb757547679907394aa42055eee))
+	ROM_REGION(0x0800, "gfx1",0)
+	ROM_LOAD ("galchr.bin", 0x0000, 0x0800, CRC(5c3b5bb5) SHA1(19429a61dc5e55ddec3242a8f695e06dd7961f88))
+ROM_END
+
+/*    YEAR  NAME     PARENT  COMPAT  MACHINE  INPUT    CLASS         INIT          COMPANY                                   FULLNAME */
+COMP( 1983, galaxy,  0,      0,      galaxy,  galaxy,  galaxy_state, init_galaxy,  "Voja Antonic / Elektronika inzenjering", "Galaksija",      0)
+COMP( 1985, galaxyp, galaxy, 0,      galaxyp, galaxyp, galaxy_state, init_galaxyp, "Nenad Dunjic",                           "Galaksija plus", 0)

Galaksija_MiST/galaxy.h

@@ -0,0 +1,69 @@
+// license:BSD-3-Clause
+// copyright-holders:Krzysztof Strzecha, Miodrag Milanovic
+/*****************************************************************************
+ *
+ * includes/galaxy.h
+ *
+ ****************************************************************************/
+
+#ifndef MAME_INCLUDES_GALAXY_H
+#define MAME_INCLUDES_GALAXY_H
+
+#include "imagedev/snapquik.h"
+#include "imagedev/cassette.h"
+#include "machine/ram.h"
+#include "screen.h"
+
+class galaxy_state : public driver_device
+{
+public:
+	galaxy_state(const machine_config &mconfig, device_type type, const char *tag)
+		: driver_device(mconfig, type, tag)
+		, m_maincpu(*this, "maincpu")
+		, m_screen(*this, "screen")
+		, m_cassette(*this, "cassette")
+		, m_ram(*this, RAM_TAG)
+		, m_region_gfx1(*this, "gfx1") {}
+
+	void galaxy(machine_config &config);
+	void galaxyp(machine_config &config);
+
+	void init_galaxy();
+	void init_galaxyp();
+
+private:
+	DECLARE_READ8_MEMBER(galaxy_keyboard_r);
+	DECLARE_WRITE8_MEMBER(galaxy_latch_w);
+	virtual void video_start() override;
+	DECLARE_MACHINE_RESET(galaxy);
+	DECLARE_MACHINE_RESET(galaxyp);
+	uint32_t screen_update_galaxy(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+	INTERRUPT_GEN_MEMBER(galaxy_interrupt);
+	TIMER_CALLBACK_MEMBER(gal_video);
+	IRQ_CALLBACK_MEMBER(galaxy_irq_callback);
+	void galaxy_set_timer();
+	void galaxy_setup_snapshot (const uint8_t * data, uint32_t size);
+	DECLARE_SNAPSHOT_LOAD_MEMBER( galaxy );
+	void galaxy_mem(address_map &map);
+	void galaxyp_io(address_map &map);
+	void galaxyp_mem(address_map &map);
+
+	required_device<cpu_device> m_maincpu;
+	required_device<screen_device> m_screen;
+	required_device<cassette_image_device> m_cassette;
+	required_device<ram_device> m_ram;
+	required_memory_region m_region_gfx1;
+	ioport_port *m_io_ports[8];
+
+	int m_interrupts_enabled;
+	uint8_t m_latch_value;
+	uint32_t m_gal_cnt;
+	uint8_t m_code;
+	uint8_t m_first;
+	uint32_t m_start_addr;
+	emu_timer *m_gal_video_timer;
+	bitmap_ind16 m_bitmap;
+};
+
+
+#endif // MAME_INCLUDES_GALAXY_H

Galaksija_MiST/rtl/Galaksija_MiST.sv

@@ -0,0 +1,136 @@
+module Galaksija_MiST(
+   input         CLOCK_27,
+   output  [5:0] VGA_R,
+   output  [5:0] VGA_G,
+   output  [5:0] VGA_B,
+   output        VGA_HS,
+   output        VGA_VS,
+   output        LED,
+   output        AUDIO_L,
+   output        AUDIO_R,
+   input         SPI_SCK,
+   output        SPI_DO,
+   input         SPI_DI,
+   input         SPI_SS2,
+   input         SPI_SS3,
+   input         CONF_DATA0/*,
+   output [12:0] SDRAM_A,
+   inout  [15:0] SDRAM_DQ,
+   output        SDRAM_DQML,
+   output        SDRAM_DQMH,
+   output        SDRAM_nWE,
+   output        SDRAM_nCAS,
+   output        SDRAM_nRAS,
+   output        SDRAM_nCS,
+   output  [1:0] SDRAM_BA,
+   output        SDRAM_CLK,
+   output        SDRAM_CKE*/
+	);
+
+`include "build_id.v"
+localparam CONF_STR = {
+	"Galaksija;;",
+//	"F,GAL,Load Program;",
+	"O23,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
+	"T9,Reset;",
+	"V,v1.00.",`BUILD_DATE
+};
+wire clk_1p7, clk_25, clk_6p25;
+wire ps2_kbd_clk, ps2_kbd_data;
+wire [2:0] r, g; 
+wire [1:0] b; 
+wire hs, vs;
+wire  [1:0] buttons, switches;
+wire			ypbpr;
+wire        forced_scandoubler;
+wire [31:0] status;
+wire [7:0] audio;
+
+
+pll pll (
+	 .inclk0 ( CLOCK_27   ),
+	 .c0     ( clk_1p7  ),
+	 .c1     ( clk_25  ),
+	 .c2     ( clk_6p25 )
+	);
+
+
+mist_io #(
+	.STRLEN($size(CONF_STR)>>3)) 
+user_io (
+	.clk_sys(clk_25),
+	.CONF_DATA0(CONF_DATA0),
+	.SPI_SCK(SPI_SCK),
+	.SPI_DI(SPI_DI),
+	.SPI_DO(SPI_DO),
+	.SPI_SS2(SPI_SS2),	
+	.conf_str(CONF_STR),
+	.ypbpr(ypbpr),
+	.status(status),
+	.scandoubler_disable(forced_scandoubler),
+	.buttons(buttons),
+	.switches(switches),
+	.ps2_kbd_clk(ps2_kbd_clk),
+	.ps2_kbd_data(ps2_kbd_data)/*,
+	.joystick_0(joystick_0),
+	.joystick_1(joystick_1),
+	.ioctl_wr(ioctl_wr),
+	.ioctl_index(ioctl_index),
+	.ioctl_download(ioctl_download),	
+	.ioctl_addr(ioctl_addr),
+	.ioctl_dout(ioctl_dout)*/
+	);
+
+video_mixer #(
+	.LINE_LENGTH(320), 
+	.HALF_DEPTH(0)) 
+video_mixer (
+	.clk_sys			( clk_25		),
+	.ce_pix			( clk_6p25		),
+	.ce_pix_actual	( clk_6p25		),
+	.SPI_SCK			( SPI_SCK		),
+	.SPI_SS3			( SPI_SS3		),
+	.SPI_DI			( SPI_DI			),
+	.R					( {r,r}),
+	.G					( {g,g}),
+	.B					( {2'b0,b,b}),
+	.HSync			( hs				),
+	.VSync			( vs	   		),
+	.VGA_R			( VGA_R			),
+	.VGA_G			( VGA_G			),
+	.VGA_B			( VGA_B			),
+	.VGA_VS			( VGA_VS			),
+	.VGA_HS			( VGA_HS			),
+	.scanlines		(forced_scandoubler ? 2'b00 : {status[3:2] == 3, status[3:2] == 2}),
+	.scandoubler_disable(1'b1),//forced_scandoubler),
+	.hq2x				(status[3:2]==1),
+	.ypbpr			( ypbpr			),
+	.ypbpr_full		( 1				),
+	.line_start		( 0				),
+	.mono				( 0				)
+	);
+	
+galaksija_top galaksija_top (
+   .clk(clk_25),
+	.a_en(clk_1p7),
+   .pixclk(clk_25),
+   .reset_n(~(status[0] | status[9] | buttons[1])),
+   .PS2_DATA(ps2_kbd_data),
+	.PS2_CLK(ps2_kbd_clk),
+	.audio(audio),
+   .LCD_DAT({b,g,r}),//todo
+   .LCD_HS(hs),
+   .LCD_VS(vs)
+);	
+
+dac #(
+   .msbi_g(7))
+dac (
+   .clk_i(clk_25),
+   .res_n_i(1'b1),
+   .dac_i(audio),
+   .dac_o(AUDIO_L)
+  );
+
+assign AUDIO_R = AUDIO_L;	
+endmodule

Galaksija_MiST/rtl/ay8910.sv

@@ -0,0 +1,308 @@
+// ports are not identical to the actual AY chip - no need for that.
+// Also the parallel ports are not very useful, so they are not connected
+
+
+
+
+module ay8910(rst_n,clk,clk_en,asel,wr_n,cs_n,din,dout,A,B,C,audio);
+    input rst_n;
+    input clk;        // 28 MHz clock from the system
+    input clk_en;    // 1.7 (?) clock to run the sound timing
+    input asel;
+    input wr_n;
+    input cs_n;
+    input [7:0] din;
+    output [7:0] dout;
+    output [7:0] A;
+    output [7:0] B;
+    output [7:0] C;
+	 output [7:0] audio;
+
+
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Write Register
+/////////////////////////////////////////////////////////////////////////////
+
+
+reg [3:0] addr;
+
+
+// registers
+reg [11:0] period_a,period_b,period_c;
+reg [4:0] period_n;
+reg [7:0] reg_en;
+reg [4:0] vol_a,vol_b,vol_c;
+reg [15:0] period_e;
+reg [3:0] shape_e;
+reg [7:0] pa_r,pb_r;
+
+
+wire pb_od = reg_en[7];
+wire pa_od = reg_en[6];
+wire na  = reg_en[5];
+wire nb  = reg_en[4];
+wire nc  = reg_en[3];
+wire ena = reg_en[2];
+wire enb = reg_en[1];
+wire enc = reg_en[0];
+
+
+always @(posedge clk)
+if(~rst_n) begin 
+       vol_a          <= 0;
+       vol_b          <= 0;
+       vol_c          <= 0;
+end else
+
+
+if(~wr_n  && ~cs_n) begin
+   if(asel)
+    begin
+      // address write
+      addr <= din[3:0];
+    end else begin
+      // register write
+      case(addr)
+       0:period_a[ 7:0] <= din;
+       1:period_a[11:8] <= din[3:0];
+       2:period_b[ 7:0] <= din;
+       3:period_b[11:8] <= din[3:0];
+       4:period_c[ 7:0] <= din;
+       5:period_c[11:8] <= din[3:0];
+       6:period_n[ 4:0] <= din[4:0];
+       7:reg_en         <= din;
+       8:vol_a          <= din[4:0];
+       9:vol_b          <= din[4:0];
+      10:vol_c          <= din[4:0];
+      11:period_e[7:0]  <= din;
+      12:period_e[15:8] <= din;
+      13:shape_e        <= din[3:0];
+      14:pa_r        <= din;
+      15:pb_r        <= din;
+      endcase
+    end
+end
+
+
+/////////////////////////////////////////////////////////////////////////////
+// Read Register
+/////////////////////////////////////////////////////////////////////////////
+assign dout = addr==4'h0 ? period_a[7:0] :
+            addr==4'h1 ? {4'h0,period_a[11:0]} :
+            addr==4'h2 ? period_b[7:0] :
+            addr==4'h3 ? {4'h0,period_b[11:0]} :
+            addr==4'h4 ? period_c[7:0] :
+            addr==4'h5 ? {4'h0,period_c[11:0]} :
+            addr==4'h6 ? {3'h0,period_n} :
+            addr==4'h7 ? reg_en :
+            addr==4'h8 ? {3'h0,vol_a} :
+            addr==4'h9 ? {3'h0,vol_b} :
+            addr==4'ha ? {3'h0,vol_c} :
+            addr==4'hb ? period_e[7:0] :
+            addr==4'hc ? period_e[15:8] :
+            addr==4'hd ? {4'h0,shape_e} : 8'hff;
+            
+
+
+/////////////////////////////////////////////////////////////////////////////
+// PSG
+/////////////////////////////////////////////////////////////////////////////
+
+
+//
+// toneA 12bit | 12bit
+// toneB 12bit | 12bit
+// toneC 12bit | 12bit
+// env   15bit | 15bit
+//
+reg [2:0] pris;
+reg [11:0] cnt_a,cnt_b,cnt_c;
+
+
+reg out_a,out_b,out_c;
+
+
+always @(posedge clk)
+if(clk_en) begin
+  pris <= pris + 1;
+  if(pris==0)
+  begin
+    // tone generator
+    cnt_a <= cnt_a + 1;
+    if(cnt_a==period_a)
+    begin
+      out_a <= ~out_a;
+      cnt_a <= 0;
+    end
+    cnt_b <= cnt_b + 1;
+    if(cnt_b==period_b)
+    begin
+      out_b <= ~out_b;
+      cnt_b <= 0;
+    end
+    cnt_c <= cnt_c + 1;
+    if(cnt_c==period_c)
+    begin
+      out_c <= ~out_c;
+      cnt_c <= 0;
+    end
+  end
+end
+
+
+/////////////////////////////////////////////////////////////////////////////
+// envelope generator
+/////////////////////////////////////////////////////////////////////////////
+reg [15:0] env_cnt;
+reg [3:0] env_phase;
+reg env_start;
+reg env_en;
+reg env_inv;
+
+
+// write eshape
+wire env_clr = (addr==13) & ~cs_n & ~wr_n;
+
+
+// bit3 = turn reset , 0=on , 1=off
+// bit2 = start , 0=up , 1=down(inv)
+// bit1 = turn invert, 0=tggle , 1=fix
+// bit0 = turn repeat, 0=off, 1=on
+
+
+wire next_no_reset  = shape_e[3];
+wire start_no_inv   = shape_e[2];
+wire next_toggle    = shape_e[1];
+wire next_repeat    = shape_e[0];
+
+
+// envelope volume output
+wire [3:0] vol_e = env_phase ^ {4{env_inv}};
+
+
+//
+always @(posedge clk or posedge env_clr)
+begin
+  if(env_clr) env_start <= 1'b1;
+  else  if(clk_en) env_start <= 1'b0;
+end
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(~rst_n)
+  begin
+    env_en    <= 1'b0;
+  end else 
+      if(clk_en)begin
+
+
+    // start trigger
+    if(env_start)
+    begin
+      env_cnt   <= 0;
+      env_phase <= 0;
+      env_inv   <= ~start_no_inv;
+      env_en    <= 1'b1;
+    end
+
+
+    // count
+    if(pris==0 && env_en)
+    begin
+      // phase up
+      env_cnt <= env_cnt + 1;
+      if(env_cnt==period_e)
+      begin
+        env_cnt <= 0;
+        env_phase <= env_phase+1;
+        // turn over
+        if(env_phase==15)
+        begin
+          if(~next_no_reset)
+          begin
+           env_inv <= (env_inv ^ next_toggle) & next_no_reset;
+           env_en  <= next_repeat & next_no_reset;
+          end
+        end
+      end
+    end
+  end
+end
+
+
+/////////////////////////////////////////////////////////////////////////////
+// noise generator
+/////////////////////////////////////////////////////////////////////////////
+reg [16:0] shift_n;
+reg [4:0] cnt_n;
+
+
+always @(posedge clk or negedge rst_n)
+begin
+  if(~rst_n)
+  begin
+    shift_n <= 17'b00000000000000001;
+  end else if((pris==0) &&(clk_en))
+  begin
+    cnt_n <= cnt_n +1;
+    if(cnt_n == period_n)
+    begin
+      cnt_n <= 0;
+      shift_n <= {shift_n[0]^shift_n[3],shift_n[16:1]};
+    end
+  end
+end
+
+
+wire out_n = shift_n[0];
+
+
+/////////////////////////////////////////////////////////////////////////////
+// volume table 3db / step
+/////////////////////////////////////////////////////////////////////////////
+function [7:0] vol_tbl;
+input [4:0] vol;
+input [3:0] vole;
+input out;
+begin
+  if(~out)
+     vol_tbl = 0;
+  else case(vol[4]?vole:vol[3:0])
+  15:vol_tbl = 255;
+  14:vol_tbl = 180;
+  13:vol_tbl = 127;
+  12:vol_tbl = 90;
+  11:vol_tbl = 64;
+  10:vol_tbl = 45;
+   9:vol_tbl = 32;
+   8:vol_tbl = 22;
+   7:vol_tbl = 16;
+   6:vol_tbl = 11;
+   5:vol_tbl = 8;
+   4:vol_tbl = 5;
+   3:vol_tbl = 4;
+   2:vol_tbl = 3;
+   1:vol_tbl = 2;
+   0:vol_tbl = 0; //1;
+  endcase
+end
+endfunction
+
+
+/////////////////////////////////////////////////////////////////////////////
+// output
+/////////////////////////////////////////////////////////////////////////////
+assign A = vol_tbl(vol_a,vol_e,(out_a | ena) & (out_n | na) );
+assign B = vol_tbl(vol_b,vol_e,(out_b | enb) & (out_n | nb) );
+assign C = vol_tbl(vol_c,vol_e,(out_c | enc) & (out_n | nc) );
+assign audio = {"00",A} + {"00",B} + {"00",C};//todo gehstock
+
+
+
+
+
+
+endmodule 

Galaksija_MiST/rtl/build_id.tcl

@@ -0,0 +1,35 @@
+# ================================================================================
+#
+# Build ID Verilog Module Script
+# Jeff Wiencrot - 8/1/2011
+#
+# Generates a Verilog module that contains a timestamp,
+# from the current build. These values are available from the build_date, build_time,
+# physical_address, and host_name output ports of the build_id module in the build_id.v
+# Verilog source file.
+#
+# ================================================================================
+
+proc generateBuildID_Verilog {} {
+
+	# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
+	set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
+	set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
+
+	# Create a Verilog file for output
+	set outputFileName "sys/build_id.v"
+	set outputFile [open $outputFileName "w"]
+
+	# Output the Verilog source
+	puts $outputFile "`define BUILD_DATE \"$buildDate\""
+	puts $outputFile "`define BUILD_TIME \"$buildTime\""
+	close $outputFile
+
+	# Send confirmation message to the Messages window
+	post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
+	post_message "Date:             $buildDate"
+	post_message "Time:             $buildTime"
+}
+
+# Comment out this line to prevent the process from automatically executing when the file is sourced:
+generateBuildID_Verilog

Galaksija_MiST/rtl/build_id.v

@@ -0,0 +1,2 @@
+`define BUILD_DATE "180816"
+`define BUILD_TIME "200421"

Galaksija_MiST/rtl/dac.vhd

@@ -0,0 +1,71 @@
+-------------------------------------------------------------------------------
+--
+-- Delta-Sigma DAC
+--
+-- $Id: dac.vhd,v 1.1 2005/10/25 21:09:42 arnim Exp $
+--
+-- Refer to Xilinx Application Note XAPP154.
+--
+-- This DAC requires an external RC low-pass filter:
+--
+--   dac_o 0---XXXXX---+---0 analog audio
+--              3k3    |
+--                    === 4n7
+--                     |
+--                    GND
+--
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dac is
+
+  generic (
+    msbi_g : integer := 7
+  );
+  port (
+    clk_i   : in  std_logic;
+    res_n_i : in  std_logic;
+    dac_i   : in  std_logic_vector(msbi_g downto 0);
+    dac_o   : out std_logic
+  );
+
+end dac;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dac is
+
+  signal DACout_q      : std_logic;
+  signal DeltaAdder_s,
+         SigmaAdder_s,
+         SigmaLatch_q,
+         DeltaB_s      : unsigned(msbi_g+2 downto 0);
+
+begin
+
+  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
+                                        SigmaLatch_q(msbi_g+2);
+  DeltaB_s(msbi_g   downto        0) <= (others => '0');
+
+  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
+
+  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
+
+  seq: process (clk_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
+      DACout_q     <= '0';
+
+    elsif clk_i'event and clk_i = '1' then
+      SigmaLatch_q <= SigmaAdder_s;
+      DACout_q     <= SigmaLatch_q(msbi_g+2);
+    end if;
+  end process seq;
+
+  dac_o <= DACout_q;
+
+end rtl;

Galaksija_MiST/rtl/dpram.vhd

@@ -0,0 +1,131 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY dpram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		--numwords_a		: natural;
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED";
+    outdata_reg_b : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock_a		: IN STD_LOGIC ;
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '1';
+		wren_b		: IN STD_LOGIC  := '1';
+		q_a		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END dpram;
+
+
+ARCHITECTURE SYN OF dpram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			wren_b	: IN STD_LOGIC ;
+			clock1	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			address_b	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_b	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(width_a-1 DOWNTO 0);
+	q_b    <= sub_wire1(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		numwords_b => 2**widthad_a,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		outdata_reg_b => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		widthad_b => widthad_a,
+		width_a => width_a,
+		width_b => width_a,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		wren_a => wren_a,
+		clock0 => clock_a,
+		wren_b => wren_b,
+		clock1 => clock_b,
+		address_a => address_a,
+		address_b => address_b,
+		data_a => data_a,
+		data_b => data_b,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;

Galaksija_MiST/rtl/font_rom.v

@@ -0,0 +1,16 @@
+module font_rom(
+  input clk,
+  input [10:0] addr,
+  output reg [7:0] data_out
+);
+
+  reg [7:0] store[0:2047] /* verilator public_flat */;
+
+  initial
+  begin
+		$readmemh("galchr.mem", store);
+  end
+
+  always @(posedge clk)
+		data_out <= store[addr];
+endmodule

Galaksija_MiST/rtl/hq2x.sv

@@ -0,0 +1,454 @@
+//
+//
+// Copyright (c) 2012-2013 Ludvig Strigeus
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+`define BITS_TO_FIT(N) ( \
+     N <=   2 ? 0 : \
+     N <=   4 ? 1 : \
+     N <=   8 ? 2 : \
+     N <=  16 ? 3 : \
+     N <=  32 ? 4 : \
+     N <=  64 ? 5 : \
+     N <= 128 ? 6 : \
+     N <= 256 ? 7 : \
+     N <= 512 ? 8 : \
+     N <=1024 ? 9 : 10 )
+
+module hq2x_in #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input            rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input            wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+	wire [DWIDTH:0] out[2];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+endmodule
+
+
+module hq2x_out #(parameter LENGTH, parameter DWIDTH)
+(
+	input            clk,
+
+	input [AWIDTH:0] rdaddr,
+	input      [1:0] rdbuf,
+	output[DWIDTH:0] q,
+
+	input [AWIDTH:0] wraddr,
+	input      [1:0] wrbuf,
+	input [DWIDTH:0] data,
+	input            wren
+);
+
+	localparam AWIDTH = `BITS_TO_FIT(LENGTH*2);
+	wire  [DWIDTH:0] out[4];
+	assign q = out[rdbuf];
+
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]);
+	hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]);
+endmodule
+
+
+module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
+(
+	input	            clock,
+	input	 [DWIDTH:0] data,
+	input	 [AWIDTH:0] rdaddress,
+	input	 [AWIDTH:0] wraddress,
+	input	            wren,
+	output [DWIDTH:0] q
+);
+
+	altsyncram	altsyncram_component (
+				.address_a (wraddress),
+				.clock0 (clock),
+				.data_a (data),
+				.wren_a (wren),
+				.address_b (rdaddress),
+				.q_b(q),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_b ({(DWIDTH+1){1'b1}}),
+				.eccstatus (),
+				.q_a (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_b = "NONE",
+		altsyncram_component.address_reg_b = "CLOCK0",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_input_b = "BYPASS",
+		altsyncram_component.clock_enable_output_b = "BYPASS",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = NUMWORDS,
+		altsyncram_component.numwords_b = NUMWORDS,
+		altsyncram_component.operation_mode = "DUAL_PORT",
+		altsyncram_component.outdata_aclr_b = "NONE",
+		altsyncram_component.outdata_reg_b = "UNREGISTERED",
+		altsyncram_component.power_up_uninitialized = "FALSE",
+		altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
+		altsyncram_component.widthad_a = AWIDTH+1,
+		altsyncram_component.widthad_b = AWIDTH+1,
+		altsyncram_component.width_a = DWIDTH+1,
+		altsyncram_component.width_b = DWIDTH+1,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module DiffCheck
+(
+	input [17:0] rgb1,
+	input [17:0] rgb2,
+	output result
+);
+
+	wire [5:0] r = rgb1[5:1] - rgb2[5:1];
+	wire [5:0] g = rgb1[11:7] - rgb2[11:7];
+	wire [5:0] b = rgb1[17:13] - rgb2[17:13];
+	wire [6:0] t = $signed(r) + $signed(b);
+	wire [6:0] gx = {g[5], g};
+	wire [7:0] y = $signed(t) + $signed(gx);
+	wire [6:0] u = $signed(r) - $signed(b);
+	wire [7:0] v = $signed({g, 1'b0}) - $signed(t);
+
+	// if y is inside (-24..24)
+	wire y_inside = (y < 8'h18 || y >= 8'he8);
+
+	// if u is inside (-4, 4)
+	wire u_inside = (u < 7'h4 || u >= 7'h7c);
+
+	// if v is inside (-6, 6)
+	wire v_inside = (v < 8'h6 || v >= 8'hfA);
+	assign result = !(y_inside && u_inside && v_inside);
+endmodule
+
+module InnerBlend
+(
+	input  [8:0] Op,
+	input  [5:0] A,
+	input  [5:0] B,
+	input  [5:0] C,
+	output [5:0] O
+);
+
+	function  [8:0] mul6x3;
+		input  [5:0] op1;
+		input  [2:0] op2;
+	begin
+		mul6x3 = 9'd0;
+		if(op2[0]) mul6x3 = mul6x3 + op1;
+		if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0};
+		if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00};
+	end
+	endfunction
+
+	wire OpOnes = Op[4];
+	wire [8:0] Amul = mul6x3(A, Op[7:5]);
+	wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0});
+	wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0});
+	wire [8:0] At =  Amul;
+	wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
+	wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
+	wire [9:0] Res = {At, 1'b0} + Bt + Ct;
+	assign O = Op[8] ? A : Res[9:4];
+endmodule
+
+module Blend
+(
+	input   [5:0] rule,
+	input         disable_hq2x,
+	input  [17:0] E,
+	input  [17:0] A,
+	input  [17:0] B,
+	input  [17:0] D,
+	input  [17:0] F,
+	input  [17:0] H,
+	output [17:0] Result
+);
+
+	reg [1:0] input_ctrl;
+	reg [8:0] op;
+	localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
+	localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
+	localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
+	localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
+	localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
+	localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
+	localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
+	localparam AB = 2'b00;
+	localparam AD = 2'b01;
+	localparam DB = 2'b10;
+	localparam BD = 2'b11;
+	wire is_diff;
+	DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
+
+	always @* begin
+		case({!is_diff, rule[5:2]})
+			1,17:  {op, input_ctrl} = {BLEND1, AB};
+			2,18:  {op, input_ctrl} = {BLEND1, DB};
+			3,19:  {op, input_ctrl} = {BLEND1, BD};
+			4,20:  {op, input_ctrl} = {BLEND2, DB};
+			5,21:  {op, input_ctrl} = {BLEND2, AB};
+			6,22:  {op, input_ctrl} = {BLEND2, AD};
+
+			8: {op, input_ctrl} = {BLEND0, 2'bxx};
+			9: {op, input_ctrl} = {BLEND0, 2'bxx};
+			10: {op, input_ctrl} = {BLEND0, 2'bxx};
+			11: {op, input_ctrl} = {BLEND1, AB};
+			12: {op, input_ctrl} = {BLEND1, AB};
+			13: {op, input_ctrl} = {BLEND1, AB};
+			14: {op, input_ctrl} = {BLEND1, DB};
+			15: {op, input_ctrl} = {BLEND1, BD};
+
+			24: {op, input_ctrl} = {BLEND2, DB};
+			25: {op, input_ctrl} = {BLEND5, DB};
+			26: {op, input_ctrl} = {BLEND6, DB};
+			27: {op, input_ctrl} = {BLEND2, DB};
+			28: {op, input_ctrl} = {BLEND4, DB};
+			29: {op, input_ctrl} = {BLEND5, DB};
+			30: {op, input_ctrl} = {BLEND3, BD};
+			31: {op, input_ctrl} = {BLEND3, DB};
+			default: {op, input_ctrl} = 11'bx;
+		endcase
+
+		// Setting op[8] effectively disables HQ2X because blend will always return E.
+		if (disable_hq2x) op[8] = 1;
+	end
+
+	// Generate inputs to the inner blender. Valid combinations.
+	// 00: E A B
+	// 01: E A D 
+	// 10: E D B
+	// 11: E B D
+	wire [17:0] Input1 = E;
+	wire [17:0] Input2 = !input_ctrl[1] ? A :
+                        !input_ctrl[0] ? D : B;
+
+	wire [17:0] Input3 = !input_ctrl[0] ? B : D;
+	InnerBlend inner_blend1(op, Input1[5:0],   Input2[5:0],   Input3[5:0],   Result[5:0]);
+	InnerBlend inner_blend2(op, Input1[11:6],  Input2[11:6],  Input3[11:6],  Result[11:6]);
+	InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]);
+endmodule
+
+
+////////////////////////////////////////////////////////////////////////////////////////////////////
+
+module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	input               clk,
+	input               ce_x4,
+	input    [DWIDTH:0] inputpixel,
+	input               mono,
+	input               disable_hq2x,
+	input               reset_frame,
+	input               reset_line,
+	input         [1:0] read_y,
+	input  [AWIDTH+1:0] read_x,
+	output   [DWIDTH:0] outpixel
+);
+
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+localparam DWIDTH = HALF_DEPTH ? 8 : 17;
+
+wire [5:0] hqTable[256] = '{
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7,  35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  35,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7,  43,
+	19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7,  35, 23, 15, 7,  43
+};
+
+reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2;
+reg [17:0] A, B, D, F, G, H;
+reg  [7:0] pattern, nextpatt;
+reg  [1:0] i;
+reg  [7:0] y;
+
+wire curbuf = y[0];
+reg  prevbuf = 0;
+wire iobuf = !curbuf;
+
+wire diff0, diff1;
+DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0);
+DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1);
+
+wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
+
+wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G;
+wire [17:0] blend_result;
+Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result);
+
+reg             Curr2_addr1;
+reg  [AWIDTH:0] Curr2_addr2;
+wire     [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp;
+wire [DWIDTH:0] Curr2tmp;
+
+reg  [AWIDTH:0] wrin_addr2;
+reg  [DWIDTH:0] wrpix;
+reg             wrin_en;
+
+function [17:0] h2rgb;
+	input  [8:0] v;
+begin
+	h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]};
+end
+endfunction
+
+function  [8:0] rgb2h;
+	input [17:0] v;
+begin
+	rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]};
+end
+endfunction
+
+hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
+(
+	.clk(clk),
+
+	.rdaddr(Curr2_addr2),
+	.rdbuf(Curr2_addr1),
+	.q(Curr2tmp),
+
+	.wraddr(wrin_addr2),
+	.wrbuf(iobuf),
+	.data(wrpix),
+	.wren(wrin_en)
+);
+
+reg         [1:0] wrout_addr1;
+reg  [AWIDTH+1:0] wrout_addr2;
+reg               wrout_en;
+reg    [DWIDTH:0] wrdata;
+
+hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out
+(
+	.clk(clk),
+
+	.rdaddr(read_x),
+	.rdbuf(read_y),
+	.q(outpixel),
+
+	.wraddr(wrout_addr2),
+	.wrbuf(wrout_addr1),
+	.data(wrdata),
+	.wren(wrout_en)
+);
+
+always @(posedge clk) begin
+	reg [AWIDTH:0] offs;
+	reg old_reset_line;
+	reg old_reset_frame;
+
+	wrout_en <= 0;
+	wrin_en  <= 0;
+
+	if(ce_x4) begin
+
+		pattern <= new_pattern;
+
+		if(~&offs) begin
+			if (i == 0) begin
+				Curr2_addr1 <= prevbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 1) begin
+				Prev2 <= Curr2;
+				Curr2_addr1 <= curbuf;
+				Curr2_addr2 <= offs;
+			end
+			if (i == 2) begin
+				Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
+				wrpix <= inputpixel;
+				wrin_addr2 <= offs;
+				wrin_en <= 1;
+			end
+			if (i == 3) begin
+				offs <= offs + 1'd1;
+			end
+
+			if(HALF_DEPTH) wrdata <= rgb2h(blend_result);
+			else           wrdata <= blend_result;
+
+			wrout_addr1 <= {curbuf, i[1]};
+			wrout_addr2 <= {offs, i[1]^i[0]};
+			wrout_en    <= 1;
+		end
+
+		if(i==3) begin
+			nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
+			{A, G} <= {Prev0, Next0};
+			{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
+			{Prev0, Prev1} <= {Prev1, Prev2};
+			{Curr0, Curr1} <= {Curr1, Curr2};
+			{Next0, Next1} <= {Next1, Next2};
+		end else begin
+			nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
+			{B, F, H, D} <= {F, H, D, B};
+		end
+
+		i <= i + 1'b1;
+		if(old_reset_line && ~reset_line) begin
+			old_reset_frame <= reset_frame;
+			offs <= 0;
+			i <= 0;
+			y <= y + 1'd1;
+			prevbuf <= curbuf;
+			if(old_reset_frame & ~reset_frame) begin
+				y <= 0;
+				prevbuf <= 0;
+			end
+		end
+
+		old_reset_line  <= reset_line;
+	end
+end
+
+endmodule  // Hq2x

Galaksija_MiST/rtl/mist_io.v

@@ -0,0 +1,496 @@
+//
+// mist_io.v
+//
+// mist_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+// Copyright (c) 2015-2017 Sorgelig
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+///////////////////////////////////////////////////////////////////////
+
+//
+// Use buffer to access SD card. It's time-critical part.
+// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
+//                                                           (Sorgelig)
+//
+// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
+// clk_ps2 = clk_sys/(PS2DIV*2)
+//
+
+module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
+(
+
+	// parameter STRLEN and the actual length of conf_str have to match
+	input [(8*STRLEN)-1:0] conf_str,
+
+	// Global clock. It should be around 100MHz (higher is better).
+	input             clk_sys,
+
+	// Global SPI clock from ARM. 24MHz
+	input             SPI_SCK,
+
+	input             CONF_DATA0,
+	input             SPI_SS2,
+	output            SPI_DO,
+	input             SPI_DI,
+
+	output reg  [7:0] joystick_0,
+	output reg  [7:0] joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output      [1:0] buttons,
+	output      [1:0] switches,
+	output            scandoubler_disable,
+	output            ypbpr,
+
+	output reg [31:0] status,
+
+	// SD config
+	input             sd_conf,
+	input             sd_sdhc,
+	output      [1:0] img_mounted, // signaling that new image has been mounted
+	output reg [31:0] img_size,    // size of image in bytes
+
+	// SD block level access
+	input      [31:0] sd_lba,
+	input       [1:0] sd_rd,
+	input       [1:0] sd_wr,
+	output reg        sd_ack,
+	output reg        sd_ack_conf,
+
+	// SD byte level access. Signals for 2-PORT altsyncram.
+	output reg  [8:0] sd_buff_addr,
+	output reg  [7:0] sd_buff_dout,
+	input       [7:0] sd_buff_din,
+	output reg        sd_buff_wr,
+
+	// ps2 keyboard emulation
+	output            ps2_kbd_clk,
+	output reg        ps2_kbd_data,
+	output            ps2_mouse_clk,
+	output reg        ps2_mouse_data,
+
+	// ps2 alternative interface. 
+
+	// [8] - extended, [9] - pressed, [10] - toggles with every press/release
+	output reg [10:0] ps2_key = 0,
+
+	// [24] - toggles with every event
+	output reg [24:0] ps2_mouse = 0,
+
+	// ARM -> FPGA download
+	input             ioctl_ce,
+	input             ioctl_wait,
+	output reg        ioctl_download = 0, // signal indicating an active download
+	output reg  [7:0] ioctl_index,        // menu index used to upload the file
+	output reg        ioctl_wr = 0,
+	output reg [13:0] ioctl_addr,
+	output reg  [7:0] ioctl_dout
+);
+
+reg [7:0] but_sw;
+reg [2:0] stick_idx;
+
+reg [1:0] mount_strobe = 0;
+assign img_mounted  = mount_strobe;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire       drive_sel = sd_rd[1] | sd_wr[1];
+wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
+
+reg [7:0] cmd;
+reg [2:0] bit_cnt;    // counts bits 0-7 0-7 ...
+reg [9:0] byte_cnt;   // counts bytes
+
+reg spi_do;
+assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
+
+reg [7:0] spi_data_out;
+
+// SPI transmitter
+always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
+
+reg [7:0] spi_data_in;
+reg       spi_data_ready = 0;
+
+// SPI receiver
+always@(posedge SPI_SCK or posedge CONF_DATA0) begin
+	reg [6:0]  sbuf;
+	reg [31:0] sd_lba_r;
+	reg        drive_sel_r;
+
+	if(CONF_DATA0) begin
+	   bit_cnt <= 0;
+	   byte_cnt <= 0;
+		spi_data_out <= core_type;
+	end
+	else
+	begin
+		bit_cnt <= bit_cnt + 1'd1;
+		sbuf <= {sbuf[5:0], SPI_DI};
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(!byte_cnt) cmd <= {sbuf, SPI_DI};
+
+			spi_data_in <= {sbuf, SPI_DI};
+			spi_data_ready <= ~spi_data_ready;
+			if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
+			
+			spi_data_out <= 0;
+			case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
+				// reading config string
+				8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
+
+				// reading sd card status
+				8'h16: if(byte_cnt == 0) begin
+							spi_data_out <= sd_cmd;
+							sd_lba_r <= sd_lba;
+							drive_sel_r <= drive_sel;
+						 end else if (byte_cnt == 1) begin
+							spi_data_out <= drive_sel_r;
+						 end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
+
+				// reading sd card write data
+				8'h18: spi_data_out <= sd_buff_din;
+			endcase
+		end
+	end
+end
+
+reg [31:0] ps2_key_raw = 0;
+wire       pressed  = (ps2_key_raw[15:8] != 8'hf0);
+wire       extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
+
+// transfer to clk_sys domain
+always@(posedge clk_sys) begin
+	reg old_ss1, old_ss2;
+	reg old_ready1, old_ready2;
+	reg [2:0] b_wr;
+	reg       got_ps2 = 0;
+
+	old_ss1 <= CONF_DATA0;
+	old_ss2 <= old_ss1;
+	old_ready1 <= spi_data_ready;
+	old_ready2 <= old_ready1;
+	
+	sd_buff_wr <= b_wr[0];
+	if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
+	b_wr <= (b_wr<<1);
+
+	if(old_ss2) begin
+		got_ps2      <= 0;
+		sd_ack       <= 0;
+		sd_ack_conf  <= 0;
+		sd_buff_addr <= 0;
+		if(got_ps2) begin
+			if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24]; 
+			if(cmd == 5) begin
+				ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
+				if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
+				if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
+				if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause  pressed
+			end
+		end
+	end
+	else
+	if(old_ready2 ^ old_ready1) begin
+
+		if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
+
+		if(byte_cnt < 2) begin
+
+			if (cmd == 8'h19) sd_ack_conf  <= 1;
+			if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
+			mount_strobe <= 0;
+
+			if(cmd == 5) ps2_key_raw <= 0;
+		end else begin
+		
+			case(cmd)
+				// buttons and switches
+				8'h01: but_sw <= spi_data_in; 
+				8'h02: joystick_0 <= spi_data_in;
+				8'h03: joystick_1 <= spi_data_in;
+
+				// store incoming ps2 mouse bytes 
+				8'h04: begin
+						got_ps2 <= 1;
+						case(byte_cnt)
+							2: ps2_mouse[7:0]   <= spi_data_in;
+							3: ps2_mouse[15:8]  <= spi_data_in;
+							4: ps2_mouse[23:16] <= spi_data_in;
+						endcase 
+						ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in; 
+						ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
+					end
+
+				// store incoming ps2 keyboard bytes 
+				8'h05: begin
+						got_ps2 <= 1;
+						ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in}; 						
+						ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in; 
+						ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
+					end
+			
+				8'h15: status[7:0] <= spi_data_in;
+			
+				// send SD config IO -> FPGA
+				// flag that download begins
+				// sd card knows data is config if sd_dout_strobe is asserted
+				// with sd_ack still being inactive (low)
+				8'h19,
+				// send sector IO -> FPGA
+				// flag that download begins
+				8'h17: begin
+						sd_buff_dout <= spi_data_in;
+						b_wr <= 1;
+					end
+
+				// joystick analog
+				8'h1a: begin
+						// first byte is joystick index
+						if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
+						else if(byte_cnt == 3) begin
+							// second byte is x axis
+							if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
+						end else if(byte_cnt == 4) begin
+							// third byte is y axis
+							if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
+								else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
+						end
+					end
+
+				// notify image selection
+				8'h1c: mount_strobe[spi_data_in[0]] <= 1;
+
+				// send image info
+				8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+
+				// status, 32bit version
+				8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
+				default: ;
+			endcase
+		end
+	end
+end
+
+
+///////////////////////////////   PS2   ///////////////////////////////
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+reg clk_ps2;
+always @(negedge clk_sys) begin
+	integer cnt;
+	cnt <= cnt + 1'd1;
+	if(cnt == PS2DIV) begin
+		clk_ps2 <= ~clk_ps2;
+		cnt <= 0;
+	end
+end
+
+// keyboard
+reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_kbd_r_inc <= 0;
+
+		if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_kbd_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+				// load tx register from fifo
+				ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+				ps2_kbd_r_inc <= 1;
+
+				// reset parity
+				ps2_kbd_parity <= 1;
+
+				// start transmitter
+				ps2_kbd_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_kbd_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+				ps2_kbd_data <= ps2_kbd_tx_byte[0];	          // data bits
+				ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+				if(ps2_kbd_tx_byte[0]) 
+					ps2_kbd_parity <= !ps2_kbd_parity;
+			end
+
+			// transmission of parity
+			if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
+
+			// transmission of stop bit
+			if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1;    // stop bit is 1
+
+			// advance state machine
+			if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
+				else ps2_kbd_tx_state <= 0;
+		end
+	end
+end
+
+// mouse
+reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge clk_sys) begin
+	reg old_clk;
+	old_clk <= clk_ps2;
+	if(~old_clk & clk_ps2) begin
+		ps2_mouse_r_inc <= 0;
+
+		if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
+
+		// transmitter is idle?
+		if(ps2_mouse_tx_state == 0) begin
+			// data in fifo present?
+			if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+				// load tx register from fifo
+				ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+				ps2_mouse_r_inc <= 1;
+
+				// reset parity
+				ps2_mouse_parity <= 1;
+
+				// start transmitter
+				ps2_mouse_tx_state <= 1;
+
+				// put start bit on data line
+				ps2_mouse_data <= 0;			// start bit is 0
+			end
+		end else begin
+
+			// transmission of 8 data bits
+			if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+				ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+				ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+				if(ps2_mouse_tx_byte[0]) 
+					ps2_mouse_parity <= !ps2_mouse_parity;
+			end
+
+			// transmission of parity
+			if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
+
+			// transmission of stop bit
+			if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1;	  // stop bit is 1
+
+			// advance state machine
+			if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
+				else ps2_mouse_tx_state <= 0;
+		end
+	end
+end
+
+
+///////////////////////////////   DOWNLOADING   ///////////////////////////////
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS2) begin
+	reg  [6:0] sbuf;
+	reg  [7:0] cmd;
+	reg  [4:0] cnt;
+	reg [13:0] addr;
+
+	if(SPI_SS2) cnt <= 0;
+	else begin
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
+
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		// finished command byte
+      if(cnt == 7) cmd <= {sbuf, SPI_DI};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare 
+			if(SPI_DI) begin
+//				addr <= ioctl_index ? 14'd9 : 14'd0; //.p files loaded at $4009, ROM is at 0
+				addr <= 14'd0;
+				ioctl_download <= 1; 
+			end else begin
+				ioctl_addr <= addr;
+				ioctl_download <= 0;
+			end
+		end
+
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			ioctl_addr <= addr;
+			ioctl_dout <= {sbuf, SPI_DI};
+			addr <= addr + 1'd1;
+			ioctl_wr <= 1;
+		end else
+			ioctl_wr <= 0;
+
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
+	end
+end
+
+endmodule

Galaksija_MiST/rtl/osd.v

@@ -0,0 +1,179 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input        clk_sys,
+
+	// SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// VGA signals coming from core
+	input  [5:0] R_in,
+	input  [5:0] G_in,
+	input  [5:0] B_in,
+	input        HSync,
+	input        VSync,
+	
+	// VGA signals going to video connector
+	output [5:0] R_out,
+	output [5:0] G_out,
+	output [5:0] B_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH   = 10'd256;
+localparam OSD_HEIGHT  = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg        osd_enable;
+(* ramstyle = "no_rw_check" *) reg  [7:0] osd_buffer[2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge SPI_SCK, posedge SPI_SS3) begin
+	reg  [4:0] cnt;
+	reg [10:0] bcnt;
+	reg  [7:0] sbuf;
+	reg  [7:0] cmd;
+
+	if(SPI_SS3) begin
+		cnt  <= 0;
+		bcnt <= 0;
+	end else begin
+		sbuf <= {sbuf[6:0], SPI_DI};
+
+		// 0:7 is command, rest payload
+		if(cnt < 15) cnt <= cnt + 1'd1;
+			else cnt <= 8;
+
+		if(cnt == 7) begin
+			cmd <= {sbuf[6:0], SPI_DI};
+      
+			// lower three command bits are line address
+			bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
+
+			// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+			if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
+		end
+
+		// command 0x20: OSDCMDWRITE
+		if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+			osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
+			bcnt <= bcnt + 1'd1;
+		end
+	end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg  [9:0] h_cnt;
+reg  [9:0] hs_low, hs_high;
+wire       hs_pol = hs_high < hs_low;
+wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
+
+// vertical counter
+reg  [9:0] v_cnt;
+reg  [9:0] vs_low, vs_high;
+wire       vs_pol = vs_high < vs_low;
+wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
+
+wire doublescan = (dsp_height>350); 
+
+reg ce_pix;
+always @(negedge clk_sys) begin
+	integer cnt = 0;
+	integer pixsz, pixcnt;
+	reg hs;
+
+	cnt <= cnt + 1;
+	hs <= HSync;
+
+	pixcnt <= pixcnt + 1;
+	if(pixcnt == pixsz) pixcnt <= 0;
+	ce_pix <= !pixcnt;
+
+	if(hs && ~HSync) begin
+		cnt    <= 0;
+		pixsz  <= (cnt >> 9) - 1;
+		pixcnt <= 0;
+		ce_pix <= 1;
+	end
+end
+
+always @(posedge clk_sys) begin
+	reg hsD, hsD2;
+	reg vsD, vsD2;
+
+	if(ce_pix) begin
+		// bring hsync into local clock domain
+		hsD <= HSync;
+		hsD2 <= hsD;
+
+		// falling edge of HSync
+		if(!hsD && hsD2) begin	
+			h_cnt <= 0;
+			hs_high <= h_cnt;
+		end
+
+		// rising edge of HSync
+		else if(hsD && !hsD2) begin	
+			h_cnt <= 0;
+			hs_low <= h_cnt;
+			v_cnt <= v_cnt + 1'd1;
+		end else begin
+			h_cnt <= h_cnt + 1'd1;
+		end
+
+		vsD <= VSync;
+		vsD2 <= vsD;
+
+		// falling edge of VSync
+		if(!vsD && vsD2) begin	
+			v_cnt <= 0;
+			vs_high <= v_cnt;
+		end
+
+		// rising edge of VSync
+		else if(vsD && !vsD2) begin	
+			v_cnt <= 0;
+			vs_low <= v_cnt;
+		end
+	end
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
+wire [9:0] h_osd_end   = h_osd_start + OSD_WIDTH;
+wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
+wire [9:0] v_osd_end   = v_osd_start + (OSD_HEIGHT<<doublescan);
+wire [9:0] osd_hcnt    = h_cnt - h_osd_start + 1'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt    = v_cnt - v_osd_start;
+
+wire osd_de = osd_enable && 
+              (HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
+              (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
+
+reg  [7:0] osd_byte; 
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
+
+assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
+assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
+assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
+
+endmodule

Galaksija_MiST/rtl/pll.v

@@ -0,0 +1,357 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
+// ************************************************************
+
+
+//Copyright (C) 1991-2013 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll (
+	inclk0,
+	c0,
+	c1,
+	c2);
+
+	input	  inclk0;
+	output	  c0;
+	output	  c1;
+	output	  c2;
+
+	wire [4:0] sub_wire0;
+	wire [0:0] sub_wire6 = 1'h0;
+	wire [2:2] sub_wire3 = sub_wire0[2:2];
+	wire [0:0] sub_wire2 = sub_wire0[0:0];
+	wire [1:1] sub_wire1 = sub_wire0[1:1];
+	wire  c1 = sub_wire1;
+	wire  c0 = sub_wire2;
+	wire  c2 = sub_wire3;
+	wire  sub_wire4 = inclk0;
+	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+
+	altpll	altpll_component (
+				.inclk (sub_wire5),
+				.clk (sub_wire0),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.locked (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 1000,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 63,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.clk1_divide_by = 27,
+		altpll_component.clk1_duty_cycle = 50,
+		altpll_component.clk1_multiply_by = 25,
+		altpll_component.clk1_phase_shift = "0",
+		altpll_component.clk2_divide_by = 108,
+		altpll_component.clk2_duty_cycle = 50,
+		altpll_component.clk2_multiply_by = 25,
+		altpll_component.clk2_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_UNUSED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk2 = "PORT_USED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1000"
+// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
+// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "108"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "1.701000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "25.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.250000"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "63"
+// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
+// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "1.70000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "25.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.25000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1000"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "63"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "108"
+// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
+// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON

Galaksija_MiST/rtl/scandoubler.v

@@ -0,0 +1,183 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// Copyright (c) 2017 Sorgelig
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
+(
+	// system interface
+	input             clk_sys,
+	input             ce_pix,
+	input             ce_pix_actual,
+
+	input             hq2x,
+
+	// shifter video interface
+	input             hs_in,
+	input             vs_in,
+	input             line_start,
+
+	input  [DWIDTH:0] r_in,
+	input  [DWIDTH:0] g_in,
+	input  [DWIDTH:0] b_in,
+	input             mono,
+
+	// output interface
+	output reg        hs_out,
+	output            vs_out,
+	output [DWIDTH:0] r_out,
+	output [DWIDTH:0] g_out,
+	output [DWIDTH:0] b_out
+);
+
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+assign vs_out = vs_in;
+
+reg  [2:0] phase;
+reg  [2:0] ce_div;
+reg  [7:0] pix_len = 0;
+wire [7:0] pl = pix_len + 1'b1;
+
+reg ce_x1, ce_x4;
+reg req_line_reset;
+wire ls_in = hs_in | line_start;
+always @(negedge clk_sys) begin
+	reg old_ce;
+	reg [2:0] ce_cnt;
+
+	reg [7:0] pixsz2, pixsz4 = 0;
+
+	old_ce <= ce_pix;
+	if(~&pix_len) pix_len <= pix_len + 1'd1;
+
+	ce_x4 <= 0;
+	ce_x1 <= 0;
+
+	// use such odd comparison to place c_x4 evenly if master clock isn't multiple 4.
+	if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
+		phase <= phase + 1'd1;
+		ce_x4 <= 1;
+	end
+
+	if(~old_ce & ce_pix) begin
+		pixsz2 <= {1'b0,  pl[7:1]};
+		pixsz4 <= {2'b00, pl[7:2]};
+		ce_x1 <= 1;
+		ce_x4 <= 1;
+		pix_len <= 0;
+		phase <= phase + 1'd1;
+
+		ce_cnt <= ce_cnt + 1'd1;
+		if(ce_pix_actual) begin
+			phase <= 0;
+			ce_div <= ce_cnt + 1'd1;
+			ce_cnt <= 0;
+			req_line_reset <= 0;
+		end
+
+		if(ls_in) req_line_reset <= 1;
+	end
+end
+
+reg ce_sd;
+always @(*) begin
+	case(ce_div)
+		2: ce_sd = !phase[0];
+		4: ce_sd = !phase[1:0];
+		default: ce_sd <= 1;
+	endcase
+end
+
+localparam AWIDTH = `BITS_TO_FIT(LENGTH);
+Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
+(
+	.clk(clk_sys),
+	.ce_x4(ce_x4 & ce_sd),
+	.inputpixel({b_in,g_in,r_in}),
+	.mono(mono),
+	.disable_hq2x(~hq2x),
+	.reset_frame(vs_in),
+	.reset_line(req_line_reset),
+	.read_y(sd_line),
+	.read_x(sd_h_actual),
+	.outpixel({b_out,g_out,r_out})
+);
+
+reg [10:0] sd_h_actual;
+always @(*) begin
+	case(ce_div)
+		2: sd_h_actual = sd_h[10:1];
+		4: sd_h_actual = sd_h[10:2];
+		default: sd_h_actual = sd_h;
+	endcase
+end
+
+reg [10:0] sd_h;
+reg  [1:0] sd_line;
+always @(posedge clk_sys) begin
+
+	reg [11:0] hs_max,hs_rise,hs_ls;
+	reg [10:0] hcnt;
+	reg [11:0] sd_hcnt;
+
+	reg hs, hs2, vs, ls;
+
+	if(ce_x1) begin
+		hs <= hs_in;
+		ls <= ls_in;
+
+		if(ls && !ls_in) hs_ls <= {hcnt,1'b1};
+
+		// falling edge of hsync indicates start of line
+		if(hs && !hs_in) begin
+			hs_max <= {hcnt,1'b1};
+			hcnt <= 0;
+			if(ls && !ls_in) hs_ls <= {10'd0,1'b1};
+		end else begin
+			hcnt <= hcnt + 1'd1;
+		end
+
+		// save position of rising edge
+		if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
+
+		vs <= vs_in;
+		if(vs && ~vs_in) sd_line <= 0;
+	end
+
+	if(ce_x4) begin
+		hs2 <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 1'd1;
+		sd_h    <= sd_h    + 1'd1;
+		if(hs2 && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_out <= 0;
+		if(sd_hcnt == hs_rise) hs_out <= 1;
+
+		if(sd_hcnt == hs_ls)   sd_h    <= 0;
+		if(sd_hcnt == hs_ls)   sd_line <= sd_line + 1'd1;
+	end
+end
+
+endmodule

Galaksija_MiST/rtl/spram.vhd

@@ -0,0 +1,90 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY spram IS
+	GENERIC
+	(
+		init_file			: string := "";
+		widthad_a			: natural;
+		width_a				: natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		data		: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END spram;
+
+
+ARCHITECTURE SYN OF spram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			wren_a	: IN STD_LOGIC ;
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		wren_a => wren,
+		clock0 => clock,
+		address_a => address,
+		data_a => data,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;

Galaksija_MiST/rtl/sprom.vhd

@@ -0,0 +1,82 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY sprom IS
+	GENERIC
+	(
+		init_file		  : string := "";
+		widthad_a		  : natural;
+		width_a			  : natural := 8;
+    outdata_reg_a : string := "UNREGISTERED"
+	);
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+		clock		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+END sprom;
+
+
+ARCHITECTURE SYN OF sprom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(width_a-1 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => init_file,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2**widthad_a,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => outdata_reg_a,
+		widthad_a => widthad_a,
+		width_a => width_a,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		clock0 => clock,
+		address_a => address,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;

Galaksija_MiST/rtl/vga_controller_640_60.vhd

@@ -0,0 +1,200 @@
+------------------------------------------------------------------------
+-- vga_controller_640_60.vhd
+------------------------------------------------------------------------
+-- Author : Ulrich Zolt
+--          Copyright 2006 Digilent, Inc.
+------------------------------------------------------------------------
+-- Software version : Xilinx ISE 7.1.04i
+--                    WebPack
+-- Device	        : 3s200ft256-4
+------------------------------------------------------------------------
+-- This file contains the logic to generate the synchronization signals,
+-- horizontal and vertical pixel counter and video disable signal
+-- for the 640x480@60Hz resolution.
+------------------------------------------------------------------------
+--  Behavioral description
+------------------------------------------------------------------------
+-- Please read the following article on the web regarding the
+-- vga video timings:
+-- http://www.epanorama.net/documents/pc/vga_timing.html
+
+-- This module generates the video synch pulses for the monitor to
+-- enter 640x480@60Hz resolution state. It also provides horizontal
+-- and vertical counters for the currently displayed pixel and a blank
+-- signal that is active when the pixel is not inside the visible screen
+-- and the color outputs should be reset to 0.
+
+-- timing diagram for the horizontal synch signal (HS)
+-- 0                         648    744           800 (pixels)
+-- -------------------------|______|-----------------
+-- timing diagram for the vertical synch signal (VS)
+-- 0                                  482    484  525 (lines)
+-- -----------------------------------|______|-------
+
+-- The blank signal is delayed one pixel clock period (40ns) from where
+-- the pixel leaves the visible screen, according to the counters, to
+-- account for the pixel pipeline delay. This delay happens because
+-- it takes time from when the counters indicate current pixel should
+-- be displayed to when the color data actually arrives at the monitor
+-- pins (memory read delays, synchronization delays).
+------------------------------------------------------------------------
+--  Port definitions
+------------------------------------------------------------------------
+-- rst               - global reset signal
+-- pixel_clk         - input pin, from dcm_25MHz
+--                   - the clock signal generated by a DCM that has
+--                   - a frequency of 25MHz.
+-- HS                - output pin, to monitor
+--                   - horizontal synch pulse
+-- VS                - output pin, to monitor
+--                   - vertical synch pulse
+-- hcount            - output pin, 11 bits, to clients
+--                   - horizontal count of the currently displayed
+--                   - pixel (even if not in visible area)
+-- vcount            - output pin, 11 bits, to clients
+--                   - vertical count of the currently active video
+--                   - line (even if not in visible area)
+-- blank             - output pin, to clients
+--                   - active when pixel is not in visible area.
+------------------------------------------------------------------------
+-- Revision History:
+-- 09/18/2006(UlrichZ): created
+------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+-- the vga_controller_640_60 entity declaration
+-- read above for behavioral description and port definitions.
+entity vga_controller_640_60 is
+port(
+   rst         : in std_logic;
+   pixel_clk   : in std_logic;
+
+   HS          : out std_logic;
+   VS          : out std_logic;
+   hcount      : out std_logic_vector(10 downto 0);
+   vcount      : out std_logic_vector(10 downto 0);
+   blank       : out std_logic
+);
+end vga_controller_640_60;
+
+architecture Behavioral of vga_controller_640_60 is
+
+------------------------------------------------------------------------
+-- CONSTANTS
+------------------------------------------------------------------------
+
+-- maximum value for the horizontal pixel counter
+constant HMAX  : std_logic_vector(10 downto 0) := "01100100000"; -- 800
+-- maximum value for the vertical pixel counter
+constant VMAX  : std_logic_vector(10 downto 0) := "01000001101"; -- 525
+-- total number of visible columns
+constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640
+-- value for the horizontal counter where front porch ends
+constant HFP   : std_logic_vector(10 downto 0) := "01010001000"; -- 648
+-- value for the horizontal counter where the synch pulse ends
+constant HSP   : std_logic_vector(10 downto 0) := "01011101000"; -- 744
+-- total number of visible lines
+constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480
+-- value for the vertical counter where the front porch ends
+constant VFP   : std_logic_vector(10 downto 0) := "00111100010"; -- 482
+-- value for the vertical counter where the synch pulse ends
+constant VSP   : std_logic_vector(10 downto 0) := "00111100100"; -- 484
+-- polarity of the horizontal and vertical synch pulse
+-- only one polarity used, because for this resolution they coincide.
+constant SPP   : std_logic := '0';
+
+------------------------------------------------------------------------
+-- SIGNALS
+------------------------------------------------------------------------
+
+-- horizontal and vertical counters
+signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
+signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
+
+-- active when inside visible screen area.
+signal video_enable: std_logic;
+
+begin
+
+   -- output horizontal and vertical counters
+   hcount <= hcounter;
+   vcount <= vcounter;
+
+   -- blank is active when outside screen visible area
+   -- color output should be blacked (put on 0) when blank in active
+   -- blank is delayed one pixel clock period from the video_enable
+   -- signal to account for the pixel pipeline delay.
+   blank <= not video_enable when rising_edge(pixel_clk);
+
+   -- increment horizontal counter at pixel_clk rate
+   -- until HMAX is reached, then reset and keep counting
+   h_count: process(pixel_clk)
+   begin
+      if(rising_edge(pixel_clk)) then
+         if(rst = '1') then
+            hcounter <= (others => '0');
+         elsif(hcounter = HMAX) then
+            hcounter <= (others => '0');
+         else
+            hcounter <= hcounter + 1;
+         end if;
+      end if;
+   end process h_count;
+
+   -- increment vertical counter when one line is finished
+   -- (horizontal counter reached HMAX)
+   -- until VMAX is reached, then reset and keep counting
+   v_count: process(pixel_clk)
+   begin
+      if(rising_edge(pixel_clk)) then
+         if(rst = '1') then
+            vcounter <= (others => '0');
+         elsif(hcounter = HMAX) then
+            if(vcounter = VMAX) then
+               vcounter <= (others => '0');
+            else
+               vcounter <= vcounter + 1;
+            end if;
+         end if;
+      end if;
+   end process v_count;
+
+   -- generate horizontal synch pulse
+   -- when horizontal counter is between where the
+   -- front porch ends and the synch pulse ends.
+   -- The HS is active (with polarity SPP) for a total of 96 pixels.
+   do_hs: process(pixel_clk)
+   begin
+      if(rising_edge(pixel_clk)) then
+         if(hcounter >= HFP and hcounter < HSP) then
+            HS <= SPP;
+         else
+            HS <= not SPP;
+         end if;
+      end if;
+   end process do_hs;
+
+   -- generate vertical synch pulse
+   -- when vertical counter is between where the
+   -- front porch ends and the synch pulse ends.
+   -- The VS is active (with polarity SPP) for a total of 2 video lines
+   -- = 2*HMAX = 1600 pixels.
+   do_vs: process(pixel_clk)
+   begin
+      if(rising_edge(pixel_clk)) then
+         if(vcounter >= VFP and vcounter < VSP) then
+            VS <= SPP;
+         else
+            VS <= not SPP;
+         end if;
+      end if;
+   end process do_vs;
+   
+   -- enable video output when pixel is in visible area
+   video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
+
+end Behavioral;

Galaksija_MiST/rtl/video_mixer.sv

@@ -0,0 +1,242 @@
+//
+//
+// Copyright (c) 2017 Sorgelig
+//
+// This program is GPL Licensed. See COPYING for the full license.
+//
+//
+////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+//
+// LINE_LENGTH: Length of  display line in pixels
+//              Usually it's length from HSync to HSync.
+//              May be less if line_start is used.
+//
+// HALF_DEPTH:  If =1 then color dept is 3 bits per component
+//              For half depth 6 bits monochrome is available with
+//              mono signal enabled and color = {G, R}
+
+module video_mixer
+#(
+	parameter LINE_LENGTH  = 768,
+	parameter HALF_DEPTH   = 0,
+
+	parameter OSD_COLOR    = 3'd4,
+	parameter OSD_X_OFFSET = 10'd0,
+	parameter OSD_Y_OFFSET = 10'd0
+)
+(
+	// master clock
+	// it should be multiple by (ce_pix*4).
+	input        clk_sys,
+	
+	// Pixel clock or clock_enable (both are accepted).
+	input        ce_pix,
+
+	// Some systems have multiple resolutions.
+	// ce_pix_actual should match ce_pix where every second or fourth pulse is enabled,
+	// thus half or qurter resolutions can be used without brake video sync while switching resolutions.
+	// For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix.
+	input        ce_pix_actual,
+
+	// OSD SPI interface
+	input        SPI_SCK,
+	input        SPI_SS3,
+	input        SPI_DI,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input  [1:0] scanlines,
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	input        scandoubler_disable,
+
+	// High quality 2x scaling
+	input        hq2x,
+
+	// YPbPr always uses composite sync
+	input        ypbpr,
+
+	// 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space)
+	input        ypbpr_full,
+
+	// color
+	input [DWIDTH:0] R,
+	input [DWIDTH:0] G,
+	input [DWIDTH:0] B,
+
+	// Monochrome mode (for HALF_DEPTH only)
+	input            mono,
+
+	// interlace sync. Positive pulses.
+	input        HSync,
+	input        VSync,
+
+	// Falling of this signal means start of informative part of line.
+	// It can be horizontal blank signal.
+	// This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler
+	// If FPGA RAM is not an issue, then simply set it to 0 for whole line processing.
+	// Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts.
+	// Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel 
+	// before first informative pixel.
+	input        line_start,
+
+	// MiST video output signals
+	output [5:0] VGA_R,
+	output [5:0] VGA_G,
+	output [5:0] VGA_B,
+	output       VGA_VS,
+	output       VGA_HS
+);
+
+localparam DWIDTH = HALF_DEPTH ? 2 : 5;
+
+wire [DWIDTH:0] R_sd;
+wire [DWIDTH:0] G_sd;
+wire [DWIDTH:0] B_sd;
+wire hs_sd, vs_sd;
+
+scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler
+(
+	.*,
+	.hs_in(HSync),
+	.vs_in(VSync),
+	.r_in(R),
+	.g_in(G),
+	.b_in(B),
+
+	.hs_out(hs_sd),
+	.vs_out(vs_sd),
+	.r_out(R_sd),
+	.g_out(G_sd),
+	.b_out(B_sd)
+);
+
+wire [DWIDTH:0] rt  = (scandoubler_disable ? R : R_sd);
+wire [DWIDTH:0] gt  = (scandoubler_disable ? G : G_sd);
+wire [DWIDTH:0] bt  = (scandoubler_disable ? B : B_sd);
+
+generate
+	if(HALF_DEPTH) begin
+		wire [5:0] r  = mono ? {gt,rt} : {rt,rt};
+		wire [5:0] g  = mono ? {gt,rt} : {gt,gt};
+		wire [5:0] b  = mono ? {gt,rt} : {bt,bt};
+	end else begin
+		wire [5:0] r  = rt;
+		wire [5:0] g  = gt;
+		wire [5:0] b  = bt;
+	end
+endgenerate
+
+wire       hs = (scandoubler_disable ? HSync : hs_sd);
+wire       vs = (scandoubler_disable ? VSync : vs_sd);
+
+reg scanline = 0;
+always @(posedge clk_sys) begin
+	reg old_hs, old_vs;
+	
+	old_hs <= hs;
+	old_vs <= vs;
+	
+	if(old_hs && ~hs) scanline <= ~scanline;
+	if(old_vs && ~vs) scanline <= 0;
+end
+
+wire [5:0] r_out, g_out, b_out;
+always @(*) begin
+	case(scanlines & {scanline, scanline})
+		1: begin // reduce 25% = 1/2 + 1/4
+			r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]};
+			g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]};
+			b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]};
+		end
+
+		2: begin // reduce 50% = 1/2
+			r_out = {1'b0, r[5:1]};
+			g_out = {1'b0, g[5:1]};
+			b_out = {1'b0, b[5:1]};
+		end
+
+		3: begin // reduce 75% = 1/4
+			r_out = {2'b00, r[5:2]};
+			g_out = {2'b00, g[5:2]};
+			b_out = {2'b00, b[5:2]};
+		end
+
+		default: begin
+			r_out = r;
+			g_out = g;
+			b_out = b;
+		end
+	endcase
+end
+
+wire [5:0] red, green, blue;
+osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd
+(
+	.*,
+
+	.R_in(r_out),
+	.G_in(g_out),
+	.B_in(b_out),
+	.HSync(hs),
+	.VSync(vs),
+
+	.R_out(red),
+	.G_out(green),
+	.B_out(blue)
+);
+
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+// http://marsee101.blog19.fc2.com/blog-entry-2311.html
+// Y  =  16 + 0.257*R + 0.504*G + 0.098*B (Y  =  0.299*R + 0.587*G + 0.114*B)
+// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B)
+// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr =  0.500*R - 0.419*G - 0.081*B)
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign VGA_R  = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) :   red;
+assign VGA_G  = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] :  y[7:2]) : green;
+assign VGA_B  = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) :  blue;
+assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd;
+assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd;
+
+endmodule