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New Core Centipede

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Gehstock
2018-11-23 20:19:26 +01:00
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2017 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 17.0.1 Build 598 06/07/2017 SJ Standard Edition
# Date created = 04:04:47 October 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "17.0"
DATE = "04:04:47 October 16, 2017"
# Revisions
PROJECT_REVISION = "Centipede"

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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full Version
# Date created = 18:42:48 November 23, 2018
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Centipede_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.2
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:53:30 APRIL 20, 2017"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/cent_top_mist.sv
set_global_assignment -name VERILOG_FILE rtl/centipede.v
set_global_assignment -name VERILOG_FILE rtl/pokey_atosm.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/keyboard.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VERILOG_FILE rtl/addsub.v
set_global_assignment -name VERILOG_FILE rtl/p6502.v
set_global_assignment -name VERILOG_FILE rtl/bc6502.v
set_global_assignment -name VERILOG_FILE rtl/pf_ram.v
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY cent_top_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# ---------------------------
# start ENTITY(cent_top_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(cent_top_mist)
# -------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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{ "" "" "" "Verilog HDL assignment warning at bc6502.v(600): truncated value with size 32 to match size of target (16)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL or VHDL warning at bc6502.v(338): object \"styy\" assigned a value but never read" { } { } 0 10036 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL assignment warning at bc6502.v(678): truncated value with size 32 to match size of target (16)" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL Always Construct warning at bc6502.v(1113): inferring latch(es) for variable \"sc\", which holds its previous value in one or more paths through the always construct" { } { } 0 10240 "" 0 0 "Quartus II" 0 -1 0 ""}

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---------------------------------------------------------------------------------
--
-- Arcade: Centipede
-- Port to MiST by Gehstock
-- 23 November 2018
--
---------------------------------------------------------------------------------
--
-- Brad Parker <brad@heeltoe.com> 10/2015
--
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- 1 : Start
-- SPACE : Fire
-- Arrow keys : Controls
-- ESC : Coin
--
--
--
---------------------------------------------------------------------------------
ToDo: Fix OSD
Fix Joystick
Fix Sound

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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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/* ===============================================================
(C) 2002 Bird Computer
All rights reserved.
addsub.v
Please read the Licensing Agreement (license.html file).
Use of this file is subject to the license agreement.
You are free to use and modify this code for non-commercial
or evaluation purposes.
If you do modify the code, please state the origin and
note that you have modified the code.
Adder / subtractor module with carry in, carry and overflow
outputs. Parameterized width with a default of 32 bits.
Note: we use a trick in the adder to get carry generated
and an adder / subtractor packed into 1 LUT per bit. The
'a' and 'b' inputs are specified with an extra unused bit
on the left (pass a zero for this bit).
Also note that the carry (borrow) input for a subtract has
to be inverted. IE. ci = 1 = no borrow in.
=============================================================== */
`timescale 1ns / 100ps
module addsub(op, ci, a, b, o, co, v);
parameter DBW = 32;
input op; // 0 = add, 1 = sub
input ci; // carry in
input [DBW:0] a, b; // operands input
output [DBW-1:0] o; // result
output co; // carry out
output v; // overflow
reg [DBW+1:0] sum;
// Note XST does not like assignments to bit group on LHS
// for subtract
always @(op or ci or a or b) begin
case(op)
1'd0: sum = {a,ci} + {b,1'b1};
1'd1: sum = {a,ci} - {b,1'b1};
endcase
end
assign o = sum[DBW:1];
assign co = sum[DBW+1];
// compute overflow
assign v = (op ^ o[DBW-1] ^ b[DBW-1]) & (~op ^ a[DBW-1] ^ b[DBW-1]);
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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`define BUILD_DATE "181123"
`define BUILD_TIME "201219"

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module cent_top_mist(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Centipede;;",
// "T1,Add Coin (ESC);",
// "T2,Player 1 Start (1);",
// "T3,Player 2 Start (2);",
// "O1,Test,off,on;",
// "O2,Cocktail,off,on;",
// "O3,Slam,off,on;",
"O45,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%;",
"T6,Reset;",
"V,v1.00.",`BUILD_DATE
};
wire clk24, clk12, clk6;
pll pll(
.inclk0(CLOCK_27),
.c0(clk24),
.c1(clk12),
.c2(clk6)
);
reg [3:0] reset_reg;
initial reset_reg = 4'b1111;
always @ (posedge clk24)
reset_reg <= {reset_reg[2:0],1'b0};
assign LED = 1'b1;
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire scandoubler_disable;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [7:0] kb_joy, joystick_0, joystick_1;
mist_io #(
.STRLEN(($size(CONF_STR)>>3)))
mist_io(
.clk_sys (clk24 ),
.conf_str (CONF_STR ),
.SPI_SCK (SPI_SCK ),
.CONF_DATA0 (CONF_DATA0 ),
.SPI_SS2 (SPI_SS2 ),
.SPI_DO (SPI_DO ),
.SPI_DI (SPI_DI ),
.buttons (buttons ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.switches (switches ),
.scandoubler_disable (scandoubler_disable ),
.ypbpr (ypbpr ),
.ps2_kbd_clk (ps2_kbd_clk ),
.ps2_kbd_data (ps2_kbd_data ),
.status (status )
);
keyboard keyboard(
.clk(clk24),
.reset(),
.ps2_kbd_clk(ps2_kbd_clk),
.ps2_kbd_data(ps2_kbd_data),
.joystick(kb_joy)
);
wire hs, vs;
wire hb, vb;
wire [2:0] r, g, b;
video_mixer #(
.LINE_LENGTH(480),
.HALF_DEPTH(1))//to dark if 0
video_mixer(
.clk_sys(clk24),
.ce_pix(clk6),
.ce_pix_out(),
.R({r,r}),
.G({g,g}),
.B({b,b}),
.HSync(hs),
.VSync(vs),
.HBlank(hb),
.VBlank(vb),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.scandoubler(~scandoubler_disable),
.scanlines(scandoubler_disable ? 2'b00 : {status[5:4] == 3, status[5:4] == 2}),
.hq2x(status[5:4]==1),
.mono(0)
);
wire [7:0] audio_o;
assign AUDIO_R = AUDIO_L;
sigma_delta_dac #(
.MSBI(7))
sigma_delta_dac(
.CLK(clk24),
.RESET(1'b0),
.DACin(audio_o),
.DACout(AUDIO_L)
);
wire coin_r, coin_c, coin_l, self_test, cocktail, slam, start1, start2, fire2, fire1;
wire [9:0] playerinput_i = { coin_r, coin_c, coin_l, self_test, cocktail, slam, start1, start2, fire2, fire1 };
//ACTIVE LOW
assign coin_r = ~kb_joy[3];
assign coin_c = 1;
assign coin_l = 1;
assign self_test = 1;//status[1];
assign cocktail = 1;//status[2];
assign slam = 1;//status[3];
assign start1 = ~kb_joy[2];//
assign start2 = ~kb_joy[1];//this is ok
assign fire2 = ~kb_joy[0];
assign fire1 = ~kb_joy[0];
//Note Cennected Joysticks breaks Controls
centipede centipede(
.clk_12mhz(clk12),
.reset(reset_reg[3] | status[0] | buttons[1] | status[6]),
.playerinput_i(playerinput_i),
.trakball_i(),
// .joystick_i({joystick_0[1],joystick_0[0],joystick_0[3],joystick_0[2], joystick_1[1],joystick_1[0],joystick_1[3],joystick_1[2]}),
.joystick_i({~kb_joy[7], ~kb_joy[6], ~kb_joy[5], ~kb_joy[4], ~kb_joy[7], ~kb_joy[6], ~kb_joy[5], ~kb_joy[4]}),
.sw1_i(8'h54),//"01010100"),//Credit Minimum, Difficulty, Bonus Life, Bonus Life, Lives, Lives, Language, Language;
.sw2_i(8'b0),//"11101010"),//Bonus Coins, Bonus Coins, Bonus Coins, Left Coin, Right Coin, Right Coin, Coinage, Coinage;
.led_o(),
.audio_o(audio_o),
.rgb_o({b,g,r}),
.sync_o(),
.hsync_o(hs),
.vsync_o(vs),
.hblank_o(hb),
.vblank_o(vb)
);
endmodule

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-------------------------------------------------------------------------------
-- $Id: dpram.vhd,v 1.1 2006/02/23 21:46:45 arnim Exp $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dpram is
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
port (
clk_a_i : in std_logic;
we_i : in std_logic;
addr_a_i : in std_logic_vector(addr_width_g-1 downto 0);
data_a_i : in std_logic_vector(data_width_g-1 downto 0);
data_a_o : out std_logic_vector(data_width_g-1 downto 0);
clk_b_i : in std_logic;
addr_b_i : in std_logic_vector(addr_width_g-1 downto 0);
data_b_o : out std_logic_vector(data_width_g-1 downto 0)
);
end entity;
library ieee;
use ieee.numeric_std.all;
architecture rtl of dpram is
type ram_t is array (natural range 2**addr_width_g-1 downto 0) of
std_logic_vector(data_width_g-1 downto 0);
signal ram_q : ram_t;
begin
mem_a: process (clk_a_i)
variable read_addr_v : unsigned(addr_width_g-1 downto 0);
begin
if rising_edge(clk_a_i) then
read_addr_v := unsigned(addr_a_i);
if we_i = '1' then
ram_q(to_integer(read_addr_v)) <= data_a_i;
end if;
data_a_o <= ram_q(to_integer(read_addr_v));
end if;
end process mem_a;
mem_b: process (clk_b_i)
variable read_addr_v : unsigned(addr_width_g-1 downto 0);
begin
if rising_edge(clk_b_i) then
read_addr_v := unsigned(addr_b_i);
data_b_o <= ram_q(to_integer(read_addr_v));
end if;
end process mem_b;
end rtl;

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//
//
// Copyright (c) 2012-2013 Ludvig Strigeus
// Copyright (c) 2017,2018 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Hq2x #(parameter LENGTH, parameter HALF_DEPTH)
(
input clk,
input ce_x4,
input [DWIDTH:0] inputpixel,
input mono,
input disable_hq2x,
input reset_frame,
input reset_line,
input [1:0] read_y,
input hblank,
output [DWIDTH:0] outpixel
);
localparam AWIDTH = $clog2(LENGTH)-1;
localparam DWIDTH = HALF_DEPTH ? 11 : 23;
localparam DWIDTH1 = DWIDTH+1;
wire [5:0] hqTable[256] = '{
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43,
19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43
};
reg [23:0] Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2;
reg [23:0] A, B, D, F, G, H;
reg [7:0] pattern, nextpatt;
reg [1:0] cyc;
reg curbuf;
reg prevbuf = 0;
wire iobuf = !curbuf;
wire diff0, diff1;
DiffCheck diffcheck0(Curr1, (cyc == 0) ? Prev0 : (cyc == 1) ? Curr0 : (cyc == 2) ? Prev2 : Next1, diff0);
DiffCheck diffcheck1(Curr1, (cyc == 0) ? Prev1 : (cyc == 1) ? Next0 : (cyc == 2) ? Curr2 : Next2, diff1);
wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]};
wire [23:0] X = (cyc == 0) ? A : (cyc == 1) ? Prev1 : (cyc == 2) ? Next1 : G;
wire [23:0] blend_result_pre;
Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result_pre);
wire [DWIDTH:0] Curr20tmp;
wire [23:0] Curr20 = HALF_DEPTH ? h2rgb(Curr20tmp) : Curr20tmp;
wire [DWIDTH:0] Curr21tmp;
wire [23:0] Curr21 = HALF_DEPTH ? h2rgb(Curr21tmp) : Curr21tmp;
reg [AWIDTH:0] wrin_addr2;
reg [DWIDTH:0] wrpix;
reg wrin_en;
function [23:0] h2rgb;
input [11:0] v;
begin
h2rgb = mono ? {v[7:0], v[7:0], v[7:0]} : {v[11:8],v[11:8],v[7:4],v[7:4],v[3:0],v[3:0]};
end
endfunction
function [11:0] rgb2h;
input [23:0] v;
begin
rgb2h = mono ? {4'b0000, v[23:20], v[19:16]} : {v[23:20], v[15:12], v[7:4]};
end
endfunction
hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in
(
.clk(clk),
.rdaddr(offs),
.rdbuf0(prevbuf),
.rdbuf1(curbuf),
.q0(Curr20tmp),
.q1(Curr21tmp),
.wraddr(wrin_addr2),
.wrbuf(iobuf),
.data(wrpix),
.wren(wrin_en)
);
reg [AWIDTH+1:0] read_x;
reg [AWIDTH+1:0] wrout_addr;
reg wrout_en;
reg [DWIDTH1*4-1:0] wrdata, wrdata_pre;
wire [DWIDTH1*4-1:0] outpixel_x4;
reg [DWIDTH1*2-1:0] outpixel_x2;
assign outpixel = read_x[0] ? outpixel_x2[DWIDTH1*2-1:DWIDTH1] : outpixel_x2[DWIDTH:0];
hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH+1), .DWIDTH(DWIDTH1*4-1)) hq2x_out
(
.clock(clk),
.rdaddress({read_x[AWIDTH+1:1],read_y[1]}),
.q(outpixel_x4),
.data(wrdata),
.wraddress(wrout_addr),
.wren(wrout_en)
);
wire [DWIDTH:0] blend_result = HALF_DEPTH ? rgb2h(blend_result_pre) : blend_result_pre[DWIDTH:0];
reg [AWIDTH:0] offs;
always @(posedge clk) begin
reg old_reset_line;
reg old_reset_frame;
wrout_en <= 0;
wrin_en <= 0;
if(ce_x4) begin
pattern <= new_pattern;
if(read_x[0]) outpixel_x2 <= read_y[0] ? outpixel_x4[DWIDTH1*4-1:DWIDTH1*2] : outpixel_x4[DWIDTH1*2-1:0];
if(~&offs) begin
if (cyc == 1) begin
Prev2 <= Curr20;
Curr2 <= Curr21;
Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel;
wrpix <= inputpixel;
wrin_addr2 <= offs;
wrin_en <= 1;
end
case({cyc[1],^cyc})
0: wrdata[DWIDTH:0] <= blend_result;
1: wrdata[DWIDTH1+DWIDTH:DWIDTH1] <= blend_result;
2: wrdata[DWIDTH1*2+DWIDTH:DWIDTH1*2] <= blend_result;
3: wrdata[DWIDTH1*3+DWIDTH:DWIDTH1*3] <= blend_result;
endcase
if(cyc==3) begin
offs <= offs + 1'd1;
wrout_addr <= {offs, curbuf};
wrout_en <= 1;
end
end
if(cyc==3) begin
nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]};
{A, G} <= {Prev0, Next0};
{B, F, H, D} <= {Prev1, Curr2, Next1, Curr0};
{Prev0, Prev1} <= {Prev1, Prev2};
{Curr0, Curr1} <= {Curr1, Curr2};
{Next0, Next1} <= {Next1, Next2};
end else begin
nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]};
{B, F, H, D} <= {F, H, D, B};
end
cyc <= cyc + 1'b1;
if(old_reset_line && ~reset_line) begin
old_reset_frame <= reset_frame;
offs <= 0;
cyc <= 0;
curbuf <= ~curbuf;
prevbuf <= curbuf;
{Prev0, Prev1, Prev2, Curr0, Curr1, Curr2, Next0, Next1, Next2} <= '0;
if(old_reset_frame & ~reset_frame) begin
curbuf <= 0;
prevbuf <= 0;
end
end
if(~hblank & ~&read_x) read_x <= read_x + 1'd1;
if(hblank) read_x <= 0;
old_reset_line <= reset_line;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module hq2x_in #(parameter LENGTH, parameter DWIDTH)
(
input clk,
input [AWIDTH:0] rdaddr,
input rdbuf0, rdbuf1,
output[DWIDTH:0] q0,q1,
input [AWIDTH:0] wraddr,
input wrbuf,
input [DWIDTH:0] data,
input wren
);
localparam AWIDTH = $clog2(LENGTH)-1;
wire [DWIDTH:0] out[2];
assign q0 = out[rdbuf0];
assign q1 = out[rdbuf1];
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]);
hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]);
endmodule
module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH)
(
input clock,
input [DWIDTH:0] data,
input [AWIDTH:0] rdaddress,
input [AWIDTH:0] wraddress,
input wren,
output logic [DWIDTH:0] q
);
logic [DWIDTH:0] ram[0:NUMWORDS-1];
always_ff@(posedge clock) begin
if(wren) ram[wraddress] <= data;
q <= ram[rdaddress];
end
endmodule
////////////////////////////////////////////////////////////////////////////////////////////////////////
module DiffCheck
(
input [23:0] rgb1,
input [23:0] rgb2,
output result
);
wire [7:0] r = rgb1[7:1] - rgb2[7:1];
wire [7:0] g = rgb1[15:9] - rgb2[15:9];
wire [7:0] b = rgb1[23:17] - rgb2[23:17];
wire [8:0] t = $signed(r) + $signed(b);
wire [8:0] gx = {g[7], g};
wire [9:0] y = $signed(t) + $signed(gx);
wire [8:0] u = $signed(r) - $signed(b);
wire [9:0] v = $signed({g, 1'b0}) - $signed(t);
// if y is inside (-96..96)
wire y_inside = (y < 10'h60 || y >= 10'h3a0);
// if u is inside (-16, 16)
wire u_inside = (u < 9'h10 || u >= 9'h1f0);
// if v is inside (-24, 24)
wire v_inside = (v < 10'h18 || v >= 10'h3e8);
assign result = !(y_inside && u_inside && v_inside);
endmodule
module InnerBlend
(
input [8:0] Op,
input [7:0] A,
input [7:0] B,
input [7:0] C,
output [7:0] O
);
function [10:0] mul8x3;
input [7:0] op1;
input [2:0] op2;
begin
mul8x3 = 11'd0;
if(op2[0]) mul8x3 = mul8x3 + op1;
if(op2[1]) mul8x3 = mul8x3 + {op1, 1'b0};
if(op2[2]) mul8x3 = mul8x3 + {op1, 2'b00};
end
endfunction
wire OpOnes = Op[4];
wire [10:0] Amul = mul8x3(A, Op[7:5]);
wire [10:0] Bmul = mul8x3(B, {Op[3:2], 1'b0});
wire [10:0] Cmul = mul8x3(C, {Op[1:0], 1'b0});
wire [10:0] At = Amul;
wire [10:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B};
wire [10:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C};
wire [11:0] Res = {At, 1'b0} + Bt + Ct;
assign O = Op[8] ? A : Res[11:4];
endmodule
module Blend
(
input [5:0] rule,
input disable_hq2x,
input [23:0] E,
input [23:0] A,
input [23:0] B,
input [23:0] D,
input [23:0] F,
input [23:0] H,
output [23:0] Result
);
reg [1:0] input_ctrl;
reg [8:0] op;
localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A
localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4
localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4
localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4
localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4
localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4
localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4
localparam AB = 2'b00;
localparam AD = 2'b01;
localparam DB = 2'b10;
localparam BD = 2'b11;
wire is_diff;
DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff);
always @* begin
case({!is_diff, rule[5:2]})
1,17: {op, input_ctrl} = {BLEND1, AB};
2,18: {op, input_ctrl} = {BLEND1, DB};
3,19: {op, input_ctrl} = {BLEND1, BD};
4,20: {op, input_ctrl} = {BLEND2, DB};
5,21: {op, input_ctrl} = {BLEND2, AB};
6,22: {op, input_ctrl} = {BLEND2, AD};
8: {op, input_ctrl} = {BLEND0, 2'bxx};
9: {op, input_ctrl} = {BLEND0, 2'bxx};
10: {op, input_ctrl} = {BLEND0, 2'bxx};
11: {op, input_ctrl} = {BLEND1, AB};
12: {op, input_ctrl} = {BLEND1, AB};
13: {op, input_ctrl} = {BLEND1, AB};
14: {op, input_ctrl} = {BLEND1, DB};
15: {op, input_ctrl} = {BLEND1, BD};
24: {op, input_ctrl} = {BLEND2, DB};
25: {op, input_ctrl} = {BLEND5, DB};
26: {op, input_ctrl} = {BLEND6, DB};
27: {op, input_ctrl} = {BLEND2, DB};
28: {op, input_ctrl} = {BLEND4, DB};
29: {op, input_ctrl} = {BLEND5, DB};
30: {op, input_ctrl} = {BLEND3, BD};
31: {op, input_ctrl} = {BLEND3, DB};
default: {op, input_ctrl} = {11{1'bx}};
endcase
// Setting op[8] effectively disables HQ2X because blend will always return E.
if (disable_hq2x) op[8] = 1;
end
// Generate inputs to the inner blender. Valid combinations.
// 00: E A B
// 01: E A D
// 10: E D B
// 11: E B D
wire [23:0] Input1 = E;
wire [23:0] Input2 = !input_ctrl[1] ? A :
!input_ctrl[0] ? D : B;
wire [23:0] Input3 = !input_ctrl[0] ? B : D;
InnerBlend inner_blend1(op, Input1[7:0], Input2[7:0], Input3[7:0], Result[7:0]);
InnerBlend inner_blend2(op, Input1[15:8], Input2[15:8], Input3[15:8], Result[15:8]);
InnerBlend inner_blend3(op, Input1[23:16], Input2[23:16], Input3[23:16], Result[23:16]);
endmodule

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module keyboard
(
input clk,
input reset,
input ps2_kbd_clk,
input ps2_kbd_data,
output reg[7:0] joystick
);
reg [11:0] shift_reg = 12'hFFF;
wire[11:0] kdata = {ps2_kbd_data,shift_reg[11:1]};
wire [7:0] kcode = kdata[9:2];
reg release_btn = 0;
reg [7:0] code;
reg input_strobe = 0;
always @(negedge clk) begin
reg old_reset = 0;
old_reset <= reset;
if(~old_reset & reset)begin
joystick <= 0;
end
if(input_strobe) begin
case(code)
'h16: joystick[1] <= ~release_btn; // 1
'h1E: joystick[2] <= ~release_btn; // 2
'h75: joystick[4] <= ~release_btn; // arrow up
'h72: joystick[5] <= ~release_btn; // arrow down
'h6B: joystick[6] <= ~release_btn; // arrow left
'h74: joystick[7] <= ~release_btn; // arrow right
'h29: joystick[0] <= ~release_btn; // Space
'h11: joystick[1] <= ~release_btn; // Left Alt
'h0d: joystick[2] <= ~release_btn; // Tab
'h76: joystick[3] <= ~release_btn; // Escape
endcase
end
end
always @(posedge clk) begin
reg [3:0] prev_clk = 0;
reg old_reset = 0;
reg action = 0;
old_reset <= reset;
input_strobe <= 0;
if(~old_reset & reset)begin
prev_clk <= 0;
shift_reg <= 12'hFFF;
end else begin
prev_clk <= {ps2_kbd_clk,prev_clk[3:1]};
if(prev_clk == 1) begin
if (kdata[11] & ^kdata[10:2] & ~kdata[1] & kdata[0]) begin
shift_reg <= 12'hFFF;
if (kcode == 8'he0) ;
// Extended key code follows
else if (kcode == 8'hf0)
// Release code follows
action <= 1;
else begin
// Cancel extended/release flags for next time
action <= 0;
release_btn <= action;
code <= kcode;
input_strobe <= 1;
end
end else begin
shift_reg <= kdata;
end
end
end
end
endmodule

519
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//
// mist_io.v
//
// mist_io for the MiST board
// http://code.google.com/p/mist-board/
//
// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
// Copyright (c) 2015-2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
///////////////////////////////////////////////////////////////////////
//
// Use buffer to access SD card. It's time-critical part.
// Made module synchroneous with 2 clock domains: clk_sys and SPI_SCK
// (Sorgelig)
//
// for synchronous projects default value for PS2DIV is fine for any frequency of system clock.
// clk_ps2 = clk_sys/(PS2DIV*2)
//
module mist_io #(parameter STRLEN=0, parameter PS2DIV=100)
(
// parameter STRLEN and the actual length of conf_str have to match
input [(8*STRLEN)-1:0] conf_str,
// Global clock. It should be around 100MHz (higher is better).
input clk_sys,
// Global SPI clock from ARM. 24MHz
input SPI_SCK,
input CONF_DATA0,
input SPI_SS2,
output SPI_DO,
input SPI_DI,
output reg [7:0] joystick_0,
output reg [7:0] joystick_1,
output reg [15:0] joystick_analog_0,
output reg [15:0] joystick_analog_1,
output [1:0] buttons,
output [1:0] switches,
output scandoubler_disable,
output ypbpr,
output reg [31:0] status,
// SD config
input sd_conf,
input sd_sdhc,
output [1:0] img_mounted, // signaling that new image has been mounted
output reg [31:0] img_size, // size of image in bytes
// SD block level access
input [31:0] sd_lba,
input [1:0] sd_rd,
input [1:0] sd_wr,
output reg sd_ack,
output reg sd_ack_conf,
// SD byte level access. Signals for 2-PORT altsyncram.
output reg [8:0] sd_buff_addr,
output reg [7:0] sd_buff_dout,
input [7:0] sd_buff_din,
output reg sd_buff_wr,
// ps2 keyboard emulation
output ps2_kbd_clk,
output reg ps2_kbd_data,
output ps2_mouse_clk,
output reg ps2_mouse_data,
// ps2 alternative interface.
// [8] - extended, [9] - pressed, [10] - toggles with every press/release
output reg [10:0] ps2_key = 0,
// [24] - toggles with every event
output reg [24:0] ps2_mouse = 0,
// ARM -> FPGA download
input ioctl_ce,
output reg ioctl_download = 0, // signal indicating an active download
output reg [7:0] ioctl_index, // menu index used to upload the file
output reg ioctl_wr = 0,
output reg [24:0] ioctl_addr,
output reg [7:0] ioctl_dout
);
reg [7:0] but_sw;
reg [2:0] stick_idx;
reg [1:0] mount_strobe = 0;
assign img_mounted = mount_strobe;
assign buttons = but_sw[1:0];
assign switches = but_sw[3:2];
assign scandoubler_disable = but_sw[4];
assign ypbpr = but_sw[5];
// this variant of user_io is for 8 bit cores (type == a4) only
wire [7:0] core_type = 8'ha4;
// command byte read by the io controller
wire drive_sel = sd_rd[1] | sd_wr[1];
wire [7:0] sd_cmd = { 4'h6, sd_conf, sd_sdhc, sd_wr[drive_sel], sd_rd[drive_sel] };
reg [7:0] cmd;
reg [2:0] bit_cnt; // counts bits 0-7 0-7 ...
reg [9:0] byte_cnt; // counts bytes
reg spi_do;
assign SPI_DO = CONF_DATA0 ? 1'bZ : spi_do;
reg [7:0] spi_data_out;
// SPI transmitter
always@(negedge SPI_SCK) spi_do <= spi_data_out[~bit_cnt];
reg [7:0] spi_data_in;
reg spi_data_ready = 0;
// SPI receiver
always@(posedge SPI_SCK or posedge CONF_DATA0) begin
reg [6:0] sbuf;
reg [31:0] sd_lba_r;
reg drive_sel_r;
if(CONF_DATA0) begin
bit_cnt <= 0;
byte_cnt <= 0;
spi_data_out <= core_type;
end
else
begin
bit_cnt <= bit_cnt + 1'd1;
sbuf <= {sbuf[5:0], SPI_DI};
// finished reading command byte
if(bit_cnt == 7) begin
if(!byte_cnt) cmd <= {sbuf, SPI_DI};
spi_data_in <= {sbuf, SPI_DI};
spi_data_ready <= ~spi_data_ready;
if(~&byte_cnt) byte_cnt <= byte_cnt + 8'd1;
spi_data_out <= 0;
case({(!byte_cnt) ? {sbuf, SPI_DI} : cmd})
// reading config string
8'h14: if(byte_cnt < STRLEN) spi_data_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8];
// reading sd card status
8'h16: if(byte_cnt == 0) begin
spi_data_out <= sd_cmd;
sd_lba_r <= sd_lba;
drive_sel_r <= drive_sel;
end else if (byte_cnt == 1) begin
spi_data_out <= drive_sel_r;
end else if(byte_cnt < 6) spi_data_out <= sd_lba_r[(5-byte_cnt)<<3 +:8];
// reading sd card write data
8'h18: spi_data_out <= sd_buff_din;
endcase
end
end
end
reg [31:0] ps2_key_raw = 0;
wire pressed = (ps2_key_raw[15:8] != 8'hf0);
wire extended = (~pressed ? (ps2_key_raw[23:16] == 8'he0) : (ps2_key_raw[15:8] == 8'he0));
// transfer to clk_sys domain
always@(posedge clk_sys) begin
reg old_ss1, old_ss2;
reg old_ready1, old_ready2;
reg [2:0] b_wr;
reg got_ps2 = 0;
old_ss1 <= CONF_DATA0;
old_ss2 <= old_ss1;
old_ready1 <= spi_data_ready;
old_ready2 <= old_ready1;
sd_buff_wr <= b_wr[0];
if(b_wr[2] && (~&sd_buff_addr)) sd_buff_addr <= sd_buff_addr + 1'b1;
b_wr <= (b_wr<<1);
if(old_ss2) begin
got_ps2 <= 0;
sd_ack <= 0;
sd_ack_conf <= 0;
sd_buff_addr <= 0;
if(got_ps2) begin
if(cmd == 4) ps2_mouse[24] <= ~ps2_mouse[24];
if(cmd == 5) begin
ps2_key <= {~ps2_key[10], pressed, extended, ps2_key_raw[7:0]};
if(ps2_key_raw == 'hE012E07C) ps2_key[9:0] <= 'h37C; // prnscr pressed
if(ps2_key_raw == 'h7CE0F012) ps2_key[9:0] <= 'h17C; // prnscr released
if(ps2_key_raw == 'hF014F077) ps2_key[9:0] <= 'h377; // pause pressed
end
end
end
else
if(old_ready2 ^ old_ready1) begin
if(cmd == 8'h18 && ~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1;
if(byte_cnt < 2) begin
if (cmd == 8'h19) sd_ack_conf <= 1;
if((cmd == 8'h17) || (cmd == 8'h18)) sd_ack <= 1;
mount_strobe <= 0;
if(cmd == 5) ps2_key_raw <= 0;
end else begin
case(cmd)
// buttons and switches
8'h01: but_sw <= spi_data_in;
8'h02: joystick_0 <= spi_data_in;
8'h03: joystick_1 <= spi_data_in;
// store incoming ps2 mouse bytes
8'h04: begin
got_ps2 <= 1;
case(byte_cnt)
2: ps2_mouse[7:0] <= spi_data_in;
3: ps2_mouse[15:8] <= spi_data_in;
4: ps2_mouse[23:16] <= spi_data_in;
endcase
ps2_mouse_fifo[ps2_mouse_wptr] <= spi_data_in;
ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1;
end
// store incoming ps2 keyboard bytes
8'h05: begin
got_ps2 <= 1;
ps2_key_raw[31:0] <= {ps2_key_raw[23:0], spi_data_in};
ps2_kbd_fifo[ps2_kbd_wptr] <= spi_data_in;
ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1;
end
8'h15: status[7:0] <= spi_data_in;
// send SD config IO -> FPGA
// flag that download begins
// sd card knows data is config if sd_dout_strobe is asserted
// with sd_ack still being inactive (low)
8'h19,
// send sector IO -> FPGA
// flag that download begins
8'h17: begin
sd_buff_dout <= spi_data_in;
b_wr <= 1;
end
// joystick analog
8'h1a: begin
// first byte is joystick index
if(byte_cnt == 2) stick_idx <= spi_data_in[2:0];
else if(byte_cnt == 3) begin
// second byte is x axis
if(stick_idx == 0) joystick_analog_0[15:8] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[15:8] <= spi_data_in;
end else if(byte_cnt == 4) begin
// third byte is y axis
if(stick_idx == 0) joystick_analog_0[7:0] <= spi_data_in;
else if(stick_idx == 1) joystick_analog_1[7:0] <= spi_data_in;
end
end
// notify image selection
8'h1c: mount_strobe[spi_data_in[0]] <= 1;
// send image info
8'h1d: if(byte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_data_in;
// status, 32bit version
8'h1e: if(byte_cnt<6) status[(byte_cnt-2)<<3 +:8] <= spi_data_in;
default: ;
endcase
end
end
end
/////////////////////////////// PS2 ///////////////////////////////
// 8 byte fifos to store ps2 bytes
localparam PS2_FIFO_BITS = 3;
reg clk_ps2;
always @(negedge clk_sys) begin
integer cnt;
cnt <= cnt + 1'd1;
if(cnt == PS2DIV) begin
clk_ps2 <= ~clk_ps2;
cnt <= 0;
end
end
// keyboard
reg [7:0] ps2_kbd_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_kbd_tx_state;
reg [7:0] ps2_kbd_tx_byte;
reg ps2_kbd_parity;
assign ps2_kbd_clk = clk_ps2 || (ps2_kbd_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_kbd_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_kbd_r_inc <= 0;
if(ps2_kbd_r_inc) ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1;
// transmitter is idle?
if(ps2_kbd_tx_state == 0) begin
// data in fifo present?
if(ps2_kbd_wptr != ps2_kbd_rptr) begin
// load tx register from fifo
ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
ps2_kbd_r_inc <= 1;
// reset parity
ps2_kbd_parity <= 1;
// start transmitter
ps2_kbd_tx_state <= 1;
// put start bit on data line
ps2_kbd_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits
ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
if(ps2_kbd_tx_byte[0])
ps2_kbd_parity <= !ps2_kbd_parity;
end
// transmission of parity
if(ps2_kbd_tx_state == 9) ps2_kbd_data <= ps2_kbd_parity;
// transmission of stop bit
if(ps2_kbd_tx_state == 10) ps2_kbd_data <= 1; // stop bit is 1
// advance state machine
if(ps2_kbd_tx_state < 11) ps2_kbd_tx_state <= ps2_kbd_tx_state + 1'd1;
else ps2_kbd_tx_state <= 0;
end
end
end
// mouse
reg [7:0] ps2_mouse_fifo[1<<PS2_FIFO_BITS];
reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
// ps2 transmitter state machine
reg [3:0] ps2_mouse_tx_state;
reg [7:0] ps2_mouse_tx_byte;
reg ps2_mouse_parity;
assign ps2_mouse_clk = clk_ps2 || (ps2_mouse_tx_state == 0);
// ps2 transmitter
// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
reg ps2_mouse_r_inc;
always@(posedge clk_sys) begin
reg old_clk;
old_clk <= clk_ps2;
if(~old_clk & clk_ps2) begin
ps2_mouse_r_inc <= 0;
if(ps2_mouse_r_inc) ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1;
// transmitter is idle?
if(ps2_mouse_tx_state == 0) begin
// data in fifo present?
if(ps2_mouse_wptr != ps2_mouse_rptr) begin
// load tx register from fifo
ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
ps2_mouse_r_inc <= 1;
// reset parity
ps2_mouse_parity <= 1;
// start transmitter
ps2_mouse_tx_state <= 1;
// put start bit on data line
ps2_mouse_data <= 0; // start bit is 0
end
end else begin
// transmission of 8 data bits
if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits
ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
if(ps2_mouse_tx_byte[0])
ps2_mouse_parity <= !ps2_mouse_parity;
end
// transmission of parity
if(ps2_mouse_tx_state == 9) ps2_mouse_data <= ps2_mouse_parity;
// transmission of stop bit
if(ps2_mouse_tx_state == 10) ps2_mouse_data <= 1; // stop bit is 1
// advance state machine
if(ps2_mouse_tx_state < 11) ps2_mouse_tx_state <= ps2_mouse_tx_state + 1'd1;
else ps2_mouse_tx_state <= 0;
end
end
end
/////////////////////////////// DOWNLOADING ///////////////////////////////
reg [7:0] data_w;
reg [24:0] addr_w;
reg rclk = 0;
localparam UIO_FILE_TX = 8'h53;
localparam UIO_FILE_TX_DAT = 8'h54;
localparam UIO_FILE_INDEX = 8'h55;
reg rdownload = 0;
// data_io has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS2) begin
reg [6:0] sbuf;
reg [7:0] cmd;
reg [4:0] cnt;
reg [24:0] addr;
if(SPI_SS2) cnt <= 0;
else begin
// don't shift in last bit. It is evaluated directly
// when writing to ram
if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI};
// count 0-7 8-15 8-15 ...
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
// finished command byte
if(cnt == 7) cmd <= {sbuf, SPI_DI};
// prepare/end transmission
if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
// prepare
if(SPI_DI) begin
addr <= 25'h080000;
rdownload <= 1;
end else begin
addr_w <= addr;
rdownload <= 0;
end
end
// command 0x54: UIO_FILE_TX
if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
addr_w <= addr;
data_w <= {sbuf, SPI_DI};
addr <= addr + 1'd1;
rclk <= ~rclk;
end
// expose file (menu) index
if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI};
end
end
// transfer to ioctl_clk domain.
// ioctl_index is set before ioctl_download, so it's stable already
always@(posedge clk_sys) begin
reg rclkD, rclkD2;
if(ioctl_ce) begin
ioctl_download <= rdownload;
rclkD <= rclk;
rclkD2 <= rclkD;
ioctl_wr <= 0;
if(rclkD != rclkD2) begin
ioctl_dout <= data_w;
ioctl_addr <= addr_w;
ioctl_wr <= 1;
end
end
end
endmodule

179
Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/osd.v Normal file
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@@ -0,0 +1,179 @@
// A simple OSD implementation. Can be hooked up between a cores
// VGA output and the physical VGA pins
module osd (
// OSDs pixel clock, should be synchronous to cores pixel clock to
// avoid jitter.
input clk_sys,
// SPI interface
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// VGA signals coming from core
input [5:0] R_in,
input [5:0] G_in,
input [5:0] B_in,
input HSync,
input VSync,
// VGA signals going to video connector
output [5:0] R_out,
output [5:0] G_out,
output [5:0] B_out
);
parameter OSD_X_OFFSET = 10'd0;
parameter OSD_Y_OFFSET = 10'd0;
parameter OSD_COLOR = 3'd0;
localparam OSD_WIDTH = 10'd256;
localparam OSD_HEIGHT = 10'd128;
// *********************************************************************************
// spi client
// *********************************************************************************
// this core supports only the display related OSD commands
// of the minimig
reg osd_enable;
(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself
// the OSD has its own SPI interface to the io controller
always@(posedge SPI_SCK, posedge SPI_SS3) begin
reg [4:0] cnt;
reg [10:0] bcnt;
reg [7:0] sbuf;
reg [7:0] cmd;
if(SPI_SS3) begin
cnt <= 0;
bcnt <= 0;
end else begin
sbuf <= {sbuf[6:0], SPI_DI};
// 0:7 is command, rest payload
if(cnt < 15) cnt <= cnt + 1'd1;
else cnt <= 8;
if(cnt == 7) begin
cmd <= {sbuf[6:0], SPI_DI};
// lower three command bits are line address
bcnt <= {sbuf[1:0], SPI_DI, 8'h00};
// command 0x40: OSDCMDENABLE, OSDCMDDISABLE
if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI;
end
// command 0x20: OSDCMDWRITE
if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI};
bcnt <= bcnt + 1'd1;
end
end
end
// *********************************************************************************
// video timing and sync polarity anaylsis
// *********************************************************************************
// horizontal counter
reg [9:0] h_cnt;
reg [9:0] hs_low, hs_high;
wire hs_pol = hs_high < hs_low;
wire [9:0] dsp_width = hs_pol ? hs_low : hs_high;
// vertical counter
reg [9:0] v_cnt;
reg [9:0] vs_low, vs_high;
wire vs_pol = vs_high < vs_low;
wire [9:0] dsp_height = vs_pol ? vs_low : vs_high;
wire doublescan = (dsp_height>350);
reg ce_pix;
always @(negedge clk_sys) begin
integer cnt = 0;
integer pixsz, pixcnt;
reg hs;
cnt <= cnt + 1;
hs <= HSync;
pixcnt <= pixcnt + 1;
if(pixcnt == pixsz) pixcnt <= 0;
ce_pix <= !pixcnt;
if(hs && ~HSync) begin
cnt <= 0;
pixsz <= (cnt >> 9) - 1;
pixcnt <= 0;
ce_pix <= 1;
end
end
always @(posedge clk_sys) begin
reg hsD, hsD2;
reg vsD, vsD2;
if(ce_pix) begin
// bring hsync into local clock domain
hsD <= HSync;
hsD2 <= hsD;
// falling edge of HSync
if(!hsD && hsD2) begin
h_cnt <= 0;
hs_high <= h_cnt;
end
// rising edge of HSync
else if(hsD && !hsD2) begin
h_cnt <= 0;
hs_low <= h_cnt;
v_cnt <= v_cnt + 1'd1;
end else begin
h_cnt <= h_cnt + 1'd1;
end
vsD <= VSync;
vsD2 <= vsD;
// falling edge of VSync
if(!vsD && vsD2) begin
v_cnt <= 0;
vs_high <= v_cnt;
end
// rising edge of VSync
else if(vsD && !vsD2) begin
v_cnt <= 0;
vs_low <= v_cnt;
end
end
end
// area in which OSD is being displayed
wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET;
wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH;
wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<<doublescan))>> 1) + OSD_Y_OFFSET;
wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<<doublescan);
wire [9:0] osd_hcnt = h_cnt - h_osd_start + 1'd1; // one pixel offset for osd_byte register
wire [9:0] osd_vcnt = v_cnt - v_osd_start;
wire osd_de = osd_enable &&
(HSync != hs_pol) && (h_cnt >= h_osd_start) && (h_cnt < h_osd_end) &&
(VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end);
reg [7:0] osd_byte;
always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]};
assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]};
assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]};
endmodule

423
Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/p6502.v Normal file
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@@ -0,0 +1,423 @@
//`define no_cpu
`define bc_cpu
//`define sim_cpu
module p6502(
input clk,
input reset_n,
input nmi,
input irq,
input so,
input rdy,
input phi0,
output phi2,
output rw_n,
output [15:0] a,
input [7:0] din,
output [7:0] dout
);
`ifdef no_cpu
// assign rw_n = 1'b1;
// assign a = 0;
// assign dout = 0;
reg cpu_rw_n;
reg [15:0] cpu_a;
reg [7:0] cpu_dout;
reg [7:0] data;
assign rw_n = cpu_rw_n;
assign a = cpu_a;
assign dout = cpu_dout;
assign phi2 = ~phi0;
task cpu_wr;
input [15:0] addr;
input [7:0] data;
begin
$display("cpu_wr %x <- %x", addr, data);
@(posedge phi0);
cpu_a = addr;
cpu_dout = data;
@(posedge phi0);
cpu_rw_n = 1'b0;
@(posedge phi0);
cpu_rw_n = 1'b1;
@(posedge phi0);
end
endtask
task cpu_rd;
input [15:0] addr;
output [7:0] data;
begin
$display("cpu_rd %x", addr);
@(posedge phi0);
cpu_a = addr;
cpu_dout = data;
@(posedge phi0);
cpu_rw_n = 1'b1;
@(posedge phi0);
cpu_rw_n = 1'b1;
@(posedge phi0);
end
endtask
task cpu_wr_pf;
input [7:0] a;
input [31:0] d;
reg [5:0] atop;
reg [7:0] b0, b1, b2, b3;
reg [15:0] a0, a1, a2, a3;
begin
b0 = d[7:0];
b1 = d[15:8];
b2 = d[23:16];
b3 = d[31:24];
atop = 6'b000001;
a0 = {atop, a[7:4], 2'd0, a[3:0]};
a1 = {atop, a[7:4], 2'd1, a[3:0]};
a2 = {atop, a[7:4], 2'd2, a[3:0]};
a3 = {atop, a[7:4], 2'd3, a[3:0]};
$display("a %x -> a0 %x %x %x %x", a, a0, a1, a2, a3);
cpu_wr(a0, b0);
cpu_wr(a1, b1);
cpu_wr(a2, b2);
cpu_wr(a3, b3);
end
endtask
`ifdef never
task cpu_wr_mapped;
input [12:0] cpu_a;
input [7:0] cpu_d;
reg [7:0] r_a;
reg [3:0] r_w;
begin
r_a = { cpu_a[9:6], cpu_a[3:0] };
case (cpu_a[5:4])
2'b00: r_w = 4'b1110;
2'b01: r_w = 4'b1101;
2'b10: r_w = 4'b1011;
2'b11: r_w = 4'b0111;
endcase
$display("%x %x -> %x %b", cpu_a, cpu_d, r_a, r_w);
if (~r_w[3])
ram3[r_a] = cpu_d;
else
if (~r_w[2])
ram2[r_a] = cpu_d;
else
if (~r_w[1])
ram1[r_a] = cpu_d;
else
if (~r_w[0])
ram0[r_a] = cpu_d;
end
endtask
`endif
integer i;
initial
begin
cpu_rw_n = 1'b1;
cpu_a = 0;
cpu_dout = 0;
`ifdef never
for (i = 'h400; i < 'h7c0; i = i + 1)
cpu_wr(i, 8'h00);
`endif
#1000;
$display("nocpu: init");
`ifdef never
cpu_wr(16'h07c0, 8'h01);
cpu_rd(16'h07c0, data);
cpu_wr(16'h07d0, 8'h02);
cpu_rd(16'h07d0, data);
cpu_wr(16'h07e0, 8'h03);
cpu_rd(16'h07e0, data);
cpu_wr(16'h0400, 8'haa);
cpu_rd(16'h0400, data);
cpu_wr(16'h0410, 8'hbb);
cpu_rd(16'h0410, data);
#20;
$finish;
`endif
`ifdef never
cpu_wr(16'h0400, 8'h00);
cpu_wr(16'h0401, 8'h01);
cpu_wr(16'h0402, 8'h02);
cpu_wr(16'h0403, 8'h03);
cpu_wr(16'h0400, 8'h00);
cpu_wr(16'h0410, 8'h11);
cpu_wr(16'h0420, 8'h22);
cpu_wr(16'h0430, 8'h33);
cpu_rd(16'h0400, data);
cpu_rd(16'h0401, data);
cpu_rd(16'h0402, data);
cpu_rd(16'h0403, data);
cpu_rd(16'h0400, data);
cpu_rd(16'h0410, data);
cpu_rd(16'h0420, data);
cpu_rd(16'h0430, data);
`endif
`ifdef never
cpu_wr_pf(8'd240, 32'h39f08606);
cpu_wr_pf(8'd241, 32'h3df27e0d);
cpu_wr_pf(8'd242, 32'h3df88384);
cpu_wr_pf(8'd243, 32'h3df88b83);
cpu_wr_pf(8'd244, 32'h3df89382);
cpu_wr_pf(8'd245, 32'h3df89b81);
cpu_wr_pf(8'd246, 32'h3df8a380);
cpu_wr_pf(8'd247, 32'h3df8ab87);
cpu_wr_pf(8'd248, 32'h3df8b386);
cpu_wr_pf(8'd249, 32'h3df8bb85);
cpu_wr_pf(8'd250, 32'h3df8c384);
cpu_wr_pf(8'd251, 32'h3df8cb83);
cpu_wr_pf(8'd252, 32'h39f8dc1c);
cpu_wr_pf(8'd253, 32'h7960fff8);
cpu_wr_pf(8'd254, 32'h39388211);
cpu_wr_pf(8'd255, 32'h390f8710);
`endif
cpu_wr_pf(8'hf0, 32'h39f08606);
cpu_wr_pf(8'hf1, 32'h3df27e0d);
cpu_wr_pf(8'hf2, 32'h39e88384);
cpu_wr_pf(8'hf3, 32'h39e88b83);
cpu_wr_pf(8'hf4, 32'h39e89382);
cpu_wr_pf(8'hf5, 32'h39e8a986);
cpu_wr_pf(8'hf6, 32'h39e8a380);
cpu_wr_pf(8'hf7, 32'h39e8ab87);
cpu_wr_pf(8'hf8, 32'h39e8b386);
cpu_wr_pf(8'hf9, 32'h39e8bb85);
cpu_wr_pf(8'hfa, 32'h39e8c384);
cpu_wr_pf(8'hfb, 32'h39e8cb83);
cpu_wr_pf(8'hfc, 32'h39e8dc1c);
cpu_wr_pf(8'hfd, 32'h7960fff8);
cpu_wr_pf(8'hfe, 32'h39388211);
cpu_wr_pf(8'hff, 32'h390f8710);
cpu_wr(16'h501, 8'h01);
cpu_wr(16'h521, 8'h14);
cpu_wr(16'h541, 8'h01);
cpu_wr(16'h561, 8'h12);
cpu_wr(16'h581, 8'h09);
cpu_wr(16'h502, 8'h14);
cpu_wr(16'h522, 8'h05);
cpu_wr(16'h542, 8'h13);
cpu_wr(16'h562, 8'h14);
cpu_wr(16'h582, 8'h00);
cpu_wr(16'h503, 8'h1b);
cpu_wr(16'h523, 8'h21);
cpu_wr(16'h543, 8'h29);
cpu_wr(16'h563, 8'h28);
cpu_wr(16'h583, 8'h20);
#10000;
#100000000;
$finish;
`ifdef never
cpu_wr(16'h07c5, 8'h11);
cpu_wr(16'h07d5, 8'hb7);
cpu_wr(16'h07e5, 8'hf0);
cpu_wr(16'h07f5, 8'h39);
cpu_wr(16'h07c4, 8'h11);
cpu_wr(16'h07d4, 8'h10);
cpu_wr(16'h07e4, 8'hf0);
cpu_wr(16'h07f4, 8'h39);
cpu_wr(16'h07c3, 8'h11);
cpu_wr(16'h07d3, 8'h40);
cpu_wr(16'h07e3, 8'h2c);
cpu_wr(16'h07f3, 8'h39);
cpu_wr(16'h07c2, 8'h10);
cpu_wr(16'h07d2, 8'h60);
cpu_wr(16'h07e2, 8'hf8);
cpu_wr(16'h07f2, 8'h3d);
cpu_wr(16'h07c1, 8'h12);
cpu_wr(16'h07d1, 8'h80);
cpu_wr(16'h07e1, 8'h02);
cpu_wr(16'h07f1, 8'h39);
`endif
`ifdef never
cpu_wr(16'h07ee, 8'h2c);
cpu_wr(16'h07de, 8'hb7);
cpu_wr(16'h07ce, 8'h11);
cpu_wr(16'h07fe, 8'h39);
cpu_wr(16'h07ed, 8'h60);
cpu_wr(16'h07dd, 8'hff);
cpu_wr(16'h07cd, 8'hf8);
cpu_wr(16'h07fd, 8'h79);
cpu_wr(16'h07ec, 8'hf8);
cpu_wr(16'h07dc, 8'h14);
cpu_wr(16'h07cc, 8'h1c);
cpu_wr(16'h07fc, 8'h39);
cpu_wr(16'h07eb, 8'hf0);
cpu_wr(16'h07db, 8'h8e);
cpu_wr(16'h07cb, 8'h03);
cpu_wr(16'h07fb, 8'h3d);
cpu_wr(16'h07ea, 8'hf0);
cpu_wr(16'h07da, 8'h96);
cpu_wr(16'h07ca, 8'h04);
cpu_wr(16'h07fa, 8'h3d);
cpu_wr(16'h07e9, 8'hf0);
cpu_wr(16'h07d9, 8'h9e);
cpu_wr(16'h07c9, 8'h05);
cpu_wr(16'h07f9, 8'h3d);
cpu_wr(16'h07e8, 8'hf0);
cpu_wr(16'h07d8, 8'ha6);
cpu_wr(16'h07c8, 8'h06);
cpu_wr(16'h07f8, 8'h3d);
cpu_wr(16'h07e7, 8'hf0);
cpu_wr(16'h07d7, 8'hae);
cpu_wr(16'h07c7, 8'h07);
cpu_wr(16'h07f7, 8'h3d);
cpu_wr(16'h07e6, 8'hf0);
cpu_wr(16'h07d6, 8'hb6);
cpu_wr(16'h07c6, 8'h00);
cpu_wr(16'h07f6, 8'h3d);
cpu_wr(16'h07e5, 8'hf0);
cpu_wr(16'h07d5, 8'hbe);
cpu_wr(16'h07c5, 8'h01);
cpu_wr(16'h07f5, 8'h3d);
cpu_wr(16'h07e4, 8'hf0);
cpu_wr(16'h07d4, 8'hc6);
cpu_wr(16'h07c4, 8'h02);
cpu_wr(16'h07f4, 8'h3d);
cpu_wr(16'h07e3, 8'hf0);
cpu_wr(16'h07d3, 8'hce);
cpu_wr(16'h07c3, 8'h03);
cpu_wr(16'h07f3, 8'h3d);
cpu_wr(16'h07e2, 8'hf0);
cpu_wr(16'h07d2, 8'hd6);
cpu_wr(16'h07c2, 8'h04);
cpu_wr(16'h07f2, 8'h3d);
cpu_wr(16'h07e1, 8'hf0);
cpu_wr(16'h07d1, 8'hde);
cpu_wr(16'h07c1, 8'h05);
cpu_wr(16'h07f1, 8'h3d);
cpu_wr(16'h07e0, 8'hf0);
cpu_wr(16'h07d0, 8'he6);
cpu_wr(16'h07c0, 8'h06);
cpu_wr(16'h07f0, 8'h39);
`endif
$display("nocpu: done");
end
`endif
`ifdef bc_cpu
wire [15:0] ma;
wire reset;
wire rw;
wire rw_nxt;
wire [15:0] ma_nxt;
wire sync;
wire [31:0] state;
wire [4:0] flags;
bc6502 bc6502(reset, phi0, ~nmi, ~irq, rdy, so, din, dout, rw, ma,
rw_nxt, ma_nxt, sync, state, flags);
assign reset = ~reset_n;
assign a = ma;
assign rw_n = rw;
// assign phi2 = clk;
assign phi2 = ~phi0;
`ifdef SIMULATION
//
integer pccount;
initial
pccount = 0;
always @(posedge clk)
begin
if (bc6502.s_sync)
begin
pccount = pccount + 1;
if (pccount == 1000/* || $time > 9999999*/)
begin
pccount = 0;
`ifdef debug_cpu
$display("%t; cpu: pc %x; a=%x x=%x", $time, bc6502.pc_reg, bc6502.a_reg, bc6502.x_reg);
`ifndef verilator
$fflush;
$flushlog;
`endif
`endif
end
if (^bc6502.pc_reg === 1'bX ||
^bc6502.a_reg === 1'bX ||
^bc6502.x_reg === 1'bX ||
^bc6502.y_reg === 1'bX)
begin
$display("%t; cpu: x's in pc, a, x or y", $time);
$finish;
end
if (^a === 1'bX || ^din === 1'bX || ^dout === 1'bX)
begin
$display("%t; cpu: x's in addr bus or data bus", $time);
$finish;
end
end
end
`endif // SIMULATION
`endif // bc_cpu
`ifdef sim_cpu
reg cpu_rw_n;
reg [15:0] cpu_a;
reg [7:0] cpu_dout;
reg [7:0] data;
assign rw_n = cpu_rw_n;
assign a = cpu_a;
assign dout = cpu_dout;
assign phi2 = ~phi0;
`endif
endmodule // p6502

82
Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pf_ram.v Normal file
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@@ -0,0 +1,82 @@
module pf_ram(
input clk_a,
input clk_b,
input reset,
input [7:0] addr_a,
input [7:0] din_a,
output [7:0] dout_a,
input [3:0] ce_a,
input [3:0] we_a,
input [7:0] addr_b,
output [31:0] dout_b,
input [3:0] ce_b
);
assign dout_a =
~ce_a[3] ? d_a3 :
~ce_a[2] ? d_a2 :
~ce_a[1] ? d_a1 :
~ce_a[0] ? d_a0 :
8'b0;
assign dout_b = { d_b3, d_b2, d_b1, d_b0 };
wire [7:0] d_a0, d_a1, d_a2, d_a3;
wire [7:0] d_b0, d_b1, d_b2, d_b3;
dpram #(
.addr_width_g(8),
.data_width_g(8))
ram0(
.clk_a_i(clk_a & ~ce_a[0]),
.we_i(~we_a[0]),
.addr_a_i(addr_a),
.data_a_i(din_a),
.data_a_o(d_a0),
.clk_b_i(clk_b & ~ce_b[0]),
.addr_b_i(addr_b),
.data_b_o(d_b0)
);
dpram #(
.addr_width_g(8),
.data_width_g(8))
ram1(
.clk_a_i(clk_a & ~ce_a[1]),
.we_i(~we_a[1]),
.addr_a_i(addr_a),
.data_a_i(din_a),
.data_a_o(d_a1),
.clk_b_i(clk_b & ~ce_b[1]),
.addr_b_i(addr_b),
.data_b_o(d_b1)
);
dpram #(
.addr_width_g(8),
.data_width_g(8))
ram2(
.clk_a_i(clk_a & ~ce_a[2]),
.we_i(~we_a[2]),
.addr_a_i(addr_a),
.data_a_i(din_a),
.data_a_o(d_a2),
.clk_b_i(clk_b & ~ce_b[2]),
.addr_b_i(addr_b),
.data_b_o(d_b2)
);
dpram #(
.addr_width_g(8),
.data_width_g(8))
ram3(
.clk_a_i(clk_a & ~ce_a[3]),
.we_i(~we_a[3]),
.addr_a_i(addr_a),
.data_a_i(din_a),
.data_a_o(d_a3),
.clk_b_i(clk_b & ~ce_b[3]),
.addr_b_i(addr_b),
.data_b_o(d_b3)
);
endmodule

357
Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/pll.v Normal file
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@@ -0,0 +1,357 @@
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
c2);
input inclk0;
output c0;
output c1;
output c2;
wire [4:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 8,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 4,
altpll_component.clk1_phase_shift = "0",
altpll_component.clk2_divide_by = 9,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 2,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "9"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "24.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "12.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "6.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "8"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "4"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "2"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "24.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "12.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "6.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "4"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

553
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// Atosm Chip
// Copyright (C) 2008 Tomasz Malesinski <tmal@mimuw.edu.pl>
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
module pokey_counter(clk_i, dat_i,
freq_ld, start, cnt_en,
out, borrow);
input clk_i;
input [7:0] dat_i;
input freq_ld;
input start;
input cnt_en;
output [7:0] out;
output borrow;
reg [7:0] freq;
reg [7:0] out;
assign borrow = (out == 0);
always @ (posedge clk_i)
if (start)
out <= freq;
else if (cnt_en)
out <= out - 8'd1;
always @ (posedge clk_i)
if (freq_ld)
freq <= dat_i;
endmodule
module pokey_basefreq(rst, clk_i, base15, out);
input rst;
input clk_i;
input base15;
output out;
reg [5:0] div57;
reg [1:0] div4;
assign out = (div57 == 0) && (!base15 || div4 == 0);
always @ (posedge clk_i)
if (rst) begin
div57 <= 6'b0;
div4 <= 2'b0;
end else if (div57 == 56) begin
div57 <= 0;
div4 <= div4 + 2'd1;
end else
div57 <= div57 + 6'd1;
endmodule
module pokey_poly4(rst, clk_i, out);
input rst;
input clk_i;
output out;
reg [3:0] shift;
assign out = shift[3];
always @ (posedge clk_i)
if (rst)
shift <= {shift[2:0], 1'b0};
else
shift <= {shift[2:0], shift[3] ~^ shift[2]};
endmodule
module pokey_poly5(rst, clk_i, out);
input rst;
input clk_i;
output out;
reg [4:0] shift;
assign out = shift[4];
always @ (posedge clk_i)
if (rst)
shift <= {shift[3:0], 1'b0};
else
shift <= {shift[3:0], shift[4] ~^ shift[2]};
endmodule
module pokey_poly17(rst, clk_i, short, out, random);
input rst;
input clk_i;
input short;
output out;
output [7:0] random;
reg [16:0] shift;
wire new_bit;
reg last_short;
assign out = shift[16];
assign random = shift[16:9];
assign new_bit = shift[16] ~^ shift[11];
// last_short is used to reset the shortened shift register when
// switching from long to short.
always @ (posedge clk_i)
if (rst)
last_short <= 0;
else
last_short <= short;
always @ (posedge clk_i)
if (rst)
shift <= 0;
else
shift <= {shift[15:8],
(short ? new_bit : shift[7]) & ~rst & (last_short | ~short),
shift[6:0], new_bit};
endmodule
module pokey_audout(rst, clk_i, dat_i,
audc_we,
poly4, poly5, poly17,
in, filter_en, filter_in,
out);
input rst;
input clk_i;
input [7:0] dat_i;
input audc_we;
input poly4, poly5, poly17;
input in, filter_en, filter_in;
output [3:0] out;
reg [3:0] vol;
reg vol_only;
reg no_poly5;
reg poly4_sel;
reg no_poly17_4;
reg nf, filter_reg;
wire change;
wire ch_out;
assign out = (ch_out | vol_only) ? vol : 4'b0;
assign change = in & (no_poly5 | poly5);
assign ch_out = filter_en ? filter_reg ^ nf : nf;
always @ (posedge clk_i)
if (audc_we) begin
vol <= dat_i[3:0];
vol_only <= dat_i[4];
no_poly5 <= dat_i[7];
poly4_sel <= dat_i[6];
no_poly17_4 <= dat_i[5];
end
always @ (posedge clk_i)
if (rst)
nf <= 0;
else if (change)
if (no_poly17_4)
nf <= ~nf;
else if (poly4_sel)
nf <= poly4;
else
nf <= poly17;
always @ (posedge clk_i)
if (!filter_en || rst)
filter_reg <= 0;
else if (filter_in)
filter_reg <= nf;
endmodule
module pokey_atosm(rst_i,
clk_i,
adr_i,
dat_i,
dat_o,
we_i,
stb_i,
ack_o,
irq,
audout,
p_i,
key_code, key_pressed, key_shift, key_break,
serout, serout_rdy_o, serout_ack_i,
serin, serin_rdy_i, serin_ack_o);
input rst_i;
input clk_i;
input [3:0] adr_i;
input [7:0] dat_i;
input we_i;
input stb_i;
input [7:0] key_code;
input key_pressed, key_shift, key_break;
input serout_ack_i;
input [7:0] serin;
input serin_rdy_i;
input [7:0] p_i;
output [7:0] dat_o;
output ack_o;
output irq;
output [5:0] audout;
output [7:0] serout;
output serout_rdy_o, serin_ack_o;
wire rst_i, clk_i;
wire [3:0] adr_i;
wire [7:0] dat_i;
wire we_i;
wire stb_i;
wire [7:0] key_code;
wire key_pressed, key_shift, key_break;
reg last_key_pressed, last_key_break;
wire ack_o;
reg [7:0] dat_o;
wire [5:0] audout;
wire [7:0] serin;
wire serin_rdy_i;
reg last_serin_rdy_i;
reg serin_ack_o;
reg [7:0] serout;
reg serout_rdy_o;
wire serout_ack_i;
reg last_serout_ack_i;
wire rst;
wire start_timer;
reg irq;
parameter [2:0] IRQ_BREAK = 7;
parameter [2:0] IRQ_KEY = 6;
parameter [2:0] IRQ_SERIN = 5;
parameter [2:0] IRQ_SEROUT = 4;
parameter [2:0] IRQ_SERFIN = 3;
parameter [2:0] IRQ_TIMER4 = 2;
parameter [2:0] IRQ_TIMER2 = 1;
parameter [2:0] IRQ_TIMER1 = 1;
reg [7:0] irqen;
reg [7:0] irqst;
// SKCTL bits.
reg [1:0] rst_bits;
// AUDCTL bits.
reg poly9;
reg fast_ch0;
reg fast_ch2;
reg ch01;
reg ch23;
reg fi02;
reg fi13;
reg base15;
reg [3:0] audf_we;
reg [3:0] audc_we;
wire [3:0] start;
wire [3:0] cnt_en;
wire [31:0] ctr_out;
wire [3:0] borrow;
wire poly4, poly5, poly17;
reg [3:1] poly4_shift, poly5_shift, poly17_shift;
wire base;
wire [3:0] audout0, audout1, audout2, audout3;
integer i, irq_i;
wire [7:0] random;
assign audout = {1'b0, audout0} + {1'b0, audout1} + {1'b0, audout2} + {1'b0, audout3};
assign rst = (rst_bits == 2'b00) | rst_i;
assign ack_o = stb_i;
//
reg [7:0] pot_done = 0;
reg [7:0] pot_cntr[0:7];
reg [7:0] pot_count;
// POTGO
always @ (posedge clk_i)
if (we_i && stb_i && adr_i == 'hb)
begin
pot_cntr[0] <= 8'h00;
pot_cntr[1] <= 8'h00;
pot_cntr[2] <= 8'h00;
pot_cntr[3] <= 8'h00;
pot_cntr[4] <= 8'h00;
pot_cntr[5] <= 8'h00;
pot_cntr[6] <= 8'h00;
pot_cntr[7] <= 8'h00;
pot_done <= 8'h00;
pot_count <= 0;
end // if (we_i && stb_i && adr_i == 'hb)
else
begin
if (pot_count != 8'hff)
pot_count <= pot_count + 8'd1;
else
pot_done <= 8'hff;
pot_cntr[0] <= p_i[0] ? 8'hff : 8'h00;
pot_cntr[1] <= p_i[1] ? 8'hff : 8'h00;
pot_cntr[2] <= p_i[2] ? 8'hff : 8'h00;
pot_cntr[3] <= p_i[3] ? 8'hff : 8'h00;
pot_cntr[4] <= p_i[4] ? 8'hff : 8'h00;
pot_cntr[5] <= p_i[5] ? 8'hff : 8'h00;
pot_cntr[6] <= p_i[6] ? 8'hff : 8'h00;
pot_cntr[7] <= p_i[7] ? 8'hff : 8'h00;
end
`ifdef never
always @ (adr_i or key_code or random or serin or irqst or irqen or
key_shift or key_pressed)
if (adr_i == 'h9)
// KBCODE
dat_o = key_code;
else if (adr_i == 'ha)
// RANDOM
dat_o = random;
else if (adr_i == 'hd)
// SERIN
dat_o = serin;
else if (adr_i == 'he)
// IRQST
dat_o = ~(irqst & irqen);
else if (adr_i == 'hf)
// SKSTAT
dat_o = {1'b1, // no framing error
1'b1, // no keyboard overrun
1'b1, // no serial data input over-run
1'b1, // serial input pad
~key_shift,
~key_pressed,
1'b1, // serial input shift register busy
1'b1}; // not used
else
dat_o = 'hff;
`else // !`ifdef never
always @ (adr_i or key_code or random or serin or irqst or irqen or
key_shift or key_pressed or pot_done or
pot_cntr[0] or pot_cntr[1] or pot_cntr[2] or pot_cntr[3] or
pot_cntr[4] or pot_cntr[5] or pot_cntr[6] or pot_cntr[7])
case (adr_i)
4'h0, 4'h1, 4'h2, 4'h3, 4'h4, 4'h5, 4'h6, 4'h7:
dat_o = pot_cntr[adr_i[2:0]];
4'h8: // ALLPOT
dat_o = pot_done;
4'h9: // KBCODE
dat_o = key_code;
4'ha: // RANDOM
dat_o = random;
4'hd: // SERIN
dat_o = serin;
4'he: // IRQST
dat_o = ~(irqst & irqen);
4'hf: // SKSTAT
dat_o = {1'b1, // no framing error
1'b1, // no keyboard overrun
1'b1, // no serial data input over-run
1'b1, // serial input pad
~key_shift,
~key_pressed,
1'b1, // serial input shift register busy
1'b1}; // not used
default:
dat_o = 'hff;
endcase
`endif // !`ifdef never
always @ (adr_i) begin
for (i = 0; i < 4; i = i + 1)
audf_we[i] = {28'b0, adr_i} == (i << 1);
for (i = 0; i < 4; i = i + 1)
audc_we[i] = {28'b0, adr_i} == ((i << 1) + 32'd1);
end
assign start_timer = (we_i && stb_i && adr_i == 9);
always @ (posedge clk_i)
if (rst) begin
poly9 <= 0;
fast_ch0 <= 0;
fast_ch2 <= 0;
ch01 <= 0;
ch23 <= 0;
fi02 <= 0;
fi13 <= 0;
base15 <= 0;
end
else
if (we_i && stb_i && adr_i == 8) begin
poly9 <= dat_i[7];
fast_ch0 <= dat_i[6];
fast_ch2 <= dat_i[5];
ch01 <= dat_i[4];
ch23 <= dat_i[3];
fi02 <= dat_i[2];
fi13 <= dat_i[1];
base15 <= dat_i[0];
end
// SKRES
always @ (posedge clk_i)
if (we_i && stb_i && adr_i == 'ha) begin
// TODO: reset SKSTAT[7:5] if they are implemented
end
always @ (posedge clk_i) begin
last_serin_rdy_i <= serin_rdy_i;
if (rst)
serin_ack_o <= 0;
else if (stb_i && !we_i && adr_i == 'hd && serin_rdy_i)
serin_ack_o <= 1;
else if (!serin_rdy_i)
serin_ack_o <= 0;
end
// SEROUT
always @ (posedge clk_i) begin
last_serout_ack_i <= serout_ack_i;
if (rst)
serout_rdy_o <= 0;
else if (we_i && stb_i && adr_i == 'hd) begin
serout <= dat_i;
serout_rdy_o <= 1;
end else if (serout_ack_i)
serout_rdy_o <= 0;
end
// IRQEN
always @ (posedge clk_i)
if (we_i && stb_i && adr_i == 'he)
irqen <= dat_i;
always @ (posedge clk_i or posedge rst_i)
if (rst_i)
rst_bits <= 0;
else
if (we_i && stb_i && adr_i == 'hf) begin
rst_bits <= dat_i[1:0];
// TODO: rest of the bits.
end
always @ (posedge clk_i) begin
last_key_pressed <= key_pressed;
last_key_break <= key_break;
end
always @ (posedge clk_i)
// IRQ_SERFIN has no latch.
irqst <= irqen & ({irqst[7:4],
!serout_ack_i && !serout_rdy_o,
irqst[2:0]} |
{key_break && !last_key_break,
key_pressed && !last_key_pressed,
serin_rdy_i && !last_serin_rdy_i,
serout_ack_i && !last_serout_ack_i,
1'b0, borrow[3], borrow[1:0]});
always @ (irqst) begin
irq = 0;
for (i = 0; i < 8; i = i + 1)
irq = irq || irqst[i];
end
pokey_basefreq u_base(rst, clk_i, base15, base);
pokey_poly4 u_poly4(rst, clk_i, poly4);
pokey_poly5 u_poly5(rst, clk_i, poly5);
pokey_poly17 u_poly17(rst, clk_i, poly9, poly17, random);
always @ (posedge clk_i) begin
poly4_shift <= {poly4_shift[2:1], poly4};
poly5_shift <= {poly5_shift[2:1], poly5};
poly17_shift <= {poly17_shift[2:1], poly17};
end
assign cnt_en[0] = fast_ch0 ? 1'b1 : base;
assign cnt_en[1] = ch01 ? borrow[0] : base;
assign cnt_en[2] = fast_ch2 ? 1'b1 : base;
assign cnt_en[3] = ch23 ? borrow[2] : base;
assign start[0] = start_timer | (ch01 ? borrow[1] : borrow[0]);
assign start[1] = start_timer | borrow[1];
assign start[2] = start_timer | (ch23 ? borrow[3] : borrow[2]);
assign start[3] = start_timer | borrow[3];
// TODO: clean it up after removing the array of instances
// (remove assignments above)
// TODO: do we need ctr_out?
pokey_counter u_ctr0(clk_i, dat_i,
audf_we[0], start[0], cnt_en[0],
ctr_out[7:0], borrow[0]);
pokey_counter u_ctr1(clk_i, dat_i,
audf_we[1], start[1], cnt_en[1],
ctr_out[15:8], borrow[1]);
pokey_counter u_ctr2(clk_i, dat_i,
audf_we[2], start[2], cnt_en[2],
ctr_out[23:16], borrow[2]);
pokey_counter u_ctr3(clk_i, dat_i,
audf_we[3], start[3], cnt_en[3],
ctr_out[31:24], borrow[3]);
pokey_audout u_audout0(start_timer, clk_i, dat_i,
audc_we[0],
poly4, poly5, poly17,
borrow[0], fi02, borrow[2],
audout0);
pokey_audout u_audout1(start_timer, clk_i, dat_i,
audc_we[1],
poly4_shift[1], poly5_shift[1], poly17_shift[1],
borrow[1], fi13, borrow[3],
audout1);
pokey_audout u_audout2(start_timer, clk_i, dat_i,
audc_we[2],
poly4_shift[2], poly5_shift[2], poly17_shift[2],
borrow[2], 1'b0, 1'b0,
audout2);
pokey_audout u_audout3(start_timer, clk_i, dat_i,
audc_we[3],
poly4_shift[3], poly5_shift[3], poly17_shift[3],
borrow[3], 1'b0, 1'b0,
audout3);
endmodule

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//
// scandoubler.v
//
// Copyright (c) 2015 Till Harbaum <till@harbaum.org>
// Copyright (c) 2017 Sorgelig
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
// TODO: Delay vsync one line
module scandoubler #(parameter LENGTH, parameter HALF_DEPTH)
(
// system interface
input clk_sys,
input ce_pix,
output ce_pix_out,
input hq2x,
// shifter video interface
input hs_in,
input vs_in,
input hb_in,
input vb_in,
input [DWIDTH:0] r_in,
input [DWIDTH:0] g_in,
input [DWIDTH:0] b_in,
input mono,
// output interface
output reg hs_out,
output vs_out,
output hb_out,
output vb_out,
output [DWIDTH:0] r_out,
output [DWIDTH:0] g_out,
output [DWIDTH:0] b_out
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
assign vs_out = vso[3];
assign ce_pix_out = hq2x ? ce_x4 : ce_x2;
//Compensate picture shift after HQ2x
assign vb_out = vbo[2];
assign hb_out = hq2x ? hbo[4] : hbo[2];
reg [7:0] pix_len = 0;
wire [7:0] pl = pix_len + 1'b1;
reg ce_x1, ce_x4, ce_x2;
reg req_line_reset;
always @(negedge clk_sys) begin
reg old_ce;
reg [2:0] ce_cnt;
reg [7:0] pixsz2, pixsz4 = 0;
old_ce <= ce_pix;
if(~&pix_len) pix_len <= pix_len + 1'd1;
ce_x4 <= 0;
ce_x2 <= 0;
ce_x1 <= 0;
// use such odd comparison to place ce_x4 evenly if master clock isn't multiple 4.
if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin
ce_x4 <= 1;
end
if(pl == pixsz2) begin
ce_x2 <= 1;
end
if(~old_ce & ce_pix) begin
pixsz2 <= {1'b0, pl[7:1]};
pixsz4 <= {2'b00, pl[7:2]};
ce_x1 <= 1;
ce_x2 <= 1;
ce_x4 <= 1;
pix_len <= 0;
req_line_reset <= 0;
if(hb_in) req_line_reset <= 1;
end
end
Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x
(
.clk(clk_sys),
.ce_x4(ce_x4),
.inputpixel({b_d,g_d,r_d}),
.mono(mono),
.disable_hq2x(~hq2x),
.reset_frame(vs_in),
.reset_line(req_line_reset),
.read_y(sd_line),
.hblank(hbo[0]),
.outpixel({b_out,g_out,r_out})
);
reg [1:0] sd_line;
reg [2:0] vbo;
reg [4:0] hbo;
reg [DWIDTH:0] r_d;
reg [DWIDTH:0] g_d;
reg [DWIDTH:0] b_d;
reg [3:0] vso;
always @(posedge clk_sys) begin
reg [11:0] hs_max,hs_rise;
reg [10:0] hcnt;
reg [11:0] sd_hcnt;
reg [11:0] hde_start, hde_end;
reg hs, hs2, vs, hb;
if(ce_x1) begin
hs <= hs_in;
hb <= hb_in;
r_d <= r_in;
g_d <= g_in;
b_d <= b_in;
if(hb && !hb_in) begin
hde_start <= {hcnt,1'b0};
vbo <= {vbo[1:0], vb_in};
end
if(!hb && hb_in) hde_end <= {hcnt,1'b0};
// falling edge of hsync indicates start of line
if(hs && !hs_in) begin
vso <= (vso<<1) | vs_in;
hs_max <= {hcnt,1'b1};
hcnt <= 0;
end else begin
hcnt <= hcnt + 1'd1;
end
// save position of rising edge
if(!hs && hs_in) hs_rise <= {hcnt,1'b1};
vs <= vs_in;
if(vs && ~vs_in) sd_line <= 0;
end
if(ce_x4) begin
hs2 <= hs_in;
hbo[4:1] <= hbo[3:0];
// output counter synchronous to input and at twice the rate
sd_hcnt <= sd_hcnt + 1'd1;
if(hs2 && !hs_in) sd_hcnt <= hs_max;
if(sd_hcnt == hs_max) sd_hcnt <= 0;
//prepare to read in advance
if(sd_hcnt == (hde_start-2)) begin
sd_line <= sd_line + 1'd1;
end
if(sd_hcnt == hde_start) hbo[0] <= 0;
if(sd_hcnt == hde_end) hbo[0] <= 1;
// replicate horizontal sync at twice the speed
if(sd_hcnt == hs_max) hs_out <= 0;
if(sd_hcnt == hs_rise) hs_out <= 1;
end
end
endmodule

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Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/sigma_delta_dac.v Normal file
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//
// PWM DAC
//
// MSBI is the highest bit number. NOT amount of bits!
//
module sigma_delta_dac #(parameter MSBI=7)
(
output reg DACout, //Average Output feeding analog lowpass
input [MSBI:0] DACin, //DAC input (excess 2**MSBI)
input CLK,
input RESET
);
reg [MSBI+2:0] DeltaAdder; //Output of Delta Adder
reg [MSBI+2:0] SigmaAdder; //Output of Sigma Adder
reg [MSBI+2:0] SigmaLatch; //Latches output of Sigma Adder
reg [MSBI+2:0] DeltaB; //B input of Delta Adder
always @(*) DeltaB = {SigmaLatch[MSBI+2], SigmaLatch[MSBI+2]} << (MSBI+1);
always @(*) DeltaAdder = DACin + DeltaB;
always @(*) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge CLK or posedge RESET) begin
if(RESET) begin
SigmaLatch <= 1'b1 << (MSBI+1);
DACout <= 1;
end else begin
SigmaLatch <= SigmaAdder;
DACout <= ~SigmaLatch[MSBI+2];
end
end
endmodule

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

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Arcade_MiST/Atari-Hardware/Centipede_MiST/rtl/video_mixer.sv Normal file
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//
//
// Copyright (c) 2017 Sorgelig
//
// This program is GPL Licensed. See COPYING for the full license.
//
//
////////////////////////////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
//
// LINE_LENGTH: Length of display line in pixels
// Usually it's length from HSync to HSync.
// May be less if line_start is used.
//
// HALF_DEPTH: If =1 then color dept is 4 bits per component
// For half depth 8 bits monochrome is available with
// mono signal enabled and color = {G, R}
module video_mixer
#(
parameter LINE_LENGTH = 768,
parameter HALF_DEPTH = 0
)
(
// master clock
// it should be multiple by (ce_pix*4).
input clk_sys,
// Pixel clock or clock_enable (both are accepted).
input ce_pix,
output ce_pix_out,
input scandoubler,
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// High quality 2x scaling
input hq2x,
// color
input [DWIDTH:0] R,
input [DWIDTH:0] G,
input [DWIDTH:0] B,
// Monochrome mode (for HALF_DEPTH only)
input mono,
input ypbpr,
// Positive pulses.
input HSync,
input VSync,
input HBlank,
input VBlank,
input SPI_SCK,
input SPI_SS3,
input SPI_DI,
// video output signals
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output reg VGA_VS,
output reg VGA_HS,
output reg VGA_DE
);
localparam DWIDTH = HALF_DEPTH ? 3 : 7;
wire [DWIDTH:0] R_sd;
wire [DWIDTH:0] G_sd;
wire [DWIDTH:0] B_sd;
wire hs_sd, vs_sd, hb_sd, vb_sd, ce_pix_sd;
scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) sd
(
.*,
.hs_in(HSync),
.vs_in(VSync),
.hb_in(HBlank),
.vb_in(VBlank),
.r_in(R),
.g_in(G),
.b_in(B),
.ce_pix_out(ce_pix_sd),
.hs_out(hs_sd),
.vs_out(vs_sd),
.hb_out(hb_sd),
.vb_out(vb_sd),
.r_out(R_sd),
.g_out(G_sd),
.b_out(B_sd)
);
wire [DWIDTH:0] rt = (scandoubler ? R_sd : R);
wire [DWIDTH:0] gt = (scandoubler ? G_sd : G);
wire [DWIDTH:0] bt = (scandoubler ? B_sd : B);
generate
if(HALF_DEPTH) begin
wire [7:0] r = mono ? {gt,rt} : {rt,rt};
wire [7:0] g = mono ? {gt,rt} : {gt,gt};
wire [7:0] b = mono ? {gt,rt} : {bt,bt};
end else begin
wire [7:0] r = rt;
wire [7:0] g = gt;
wire [7:0] b = bt;
end
endgenerate
wire hs = (scandoubler ? hs_sd : HSync);
wire vs = (scandoubler ? vs_sd : VSync);
assign ce_pix_out = scandoubler ? ce_pix_sd : ce_pix;
reg scanline = 0;
always @(posedge clk_sys) begin
reg old_hs, old_vs;
old_hs <= hs;
old_vs <= vs;
if(old_hs && ~hs) scanline <= ~scanline;
if(old_vs && ~vs) scanline <= 0;
end
wire hde = scandoubler ? ~hb_sd : ~HBlank;
wire vde = scandoubler ? ~vb_sd : ~VBlank;
reg hsync, vsync;
reg [7:0] R_in,G_in,B_in;
always @(posedge clk_sys) begin
reg old_hde;
case(scanlines & {scanline, scanline})
1: begin // reduce 25% = 1/2 + 1/4
R_in <= {1'b0, r[7:1]} + {2'b00, r[7:2]};
G_in <= {1'b0, g[7:1]} + {2'b00, g[7:2]};
B_in <= {1'b0, b[7:1]} + {2'b00, b[7:2]};
end
2: begin // reduce 50% = 1/2
R_in <= {1'b0, r[7:1]};
G_in <= {1'b0, g[7:1]};
B_in <= {1'b0, b[7:1]};
end
3: begin // reduce 75% = 1/4
R_in <= {2'b00, r[7:2]};
G_in <= {2'b00, g[7:2]};
B_in <= {2'b00, b[7:2]};
end
default: begin
R_in <= r;
G_in <= g;
B_in <= b;
end
endcase
vsync <= vs;
hsync <= hs;
old_hde <= hde;
if(~old_hde && hde) VGA_DE <= vde;
if(old_hde && ~hde) VGA_DE <= 0;
end
assign VGA_VS = (~scandoubler | ypbpr) ? 1'b1 : ~vsync;
assign VGA_HS = (~scandoubler | ypbpr) ? ~(vsync ^ hsync) : ~hsync;
wire [5:0] R_out,G_out,B_out;
osd osd
(
.*,
.R_in(VGA_DE ? R_in[7:2] : 6'd0),
.G_in(VGA_DE ? G_in[7:2] : 6'd0),
.B_in(VGA_DE ? B_in[7:2] : 6'd0),
.R_out(VGA_R),
.G_out(VGA_G),
.B_out(VGA_B),
.HSync(hsync),
.VSync(vsync)
);
endmodule

1
Arcade_MiST/Konami Classic/Time_Pilot_MiST/time_pilot_mist.qsf
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@@ -117,6 +117,7 @@ set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0