github.com/Gehstock.Mist_FPGA
1
0
Fork 0
mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-17 00:22:41 +00:00
Code Issues Releases Wiki Activity

Sync Repo

Browse Source
This commit is contained in:
Marcel 2019-03-07 21:01:17 +01:00
parent 9bb526151b
commit e0fb401121
4 changed files with 113 additions and 99 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

193
Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/ComputerSpace_MiST.qsf
View File

@ -46,29 +46,82 @@ set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SDC_FILE ComputerSpace_MiST.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ComputerSpace_MiST.sv
set_global_assignment -name VHDL_FILE rtl/computer_space_top.vhd
set_global_assignment -name VHDL_FILE rtl/computer_space_logic.vhd
set_global_assignment -name VHDL_FILE rtl/sync_star_board.vhd
set_global_assignment -name VHDL_FILE rtl/motion_board.vhd
set_global_assignment -name VHDL_FILE rtl/scan_counter.vhd
set_global_assignment -name VHDL_FILE rtl/v74161.vhd
set_global_assignment -name VHDL_FILE rtl/v74161_16bit.vhd
set_global_assignment -name VHDL_FILE rtl/memory_board.vhd
set_global_assignment -name VHDL_FILE rtl/saucer_diode_image.vhd
set_global_assignment -name VHDL_FILE rtl/rocket_diode_images.vhd
set_global_assignment -name VHDL_FILE rtl/clocks.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/computer_space_sound.vhd
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
# Pin & Location Assignments
# ==========================
# Classic Timing Assignments
# ==========================
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY ComputerSpace_MiST
# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------------
# start ENTITY(ComputerSpace_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(ComputerSpace_MiST)
# ----------------------------------
# start ENTITY(computer_space_logic)
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
@ -100,39 +153,16 @@ set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
# Classic Timing Assignments
# ==========================
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
# end ENTITY(computer_space_logic)
# --------------------------------
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name SAVE_DISK_SPACE OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY ComputerSpace_MiST
# --------------------------------
# start ENTITY(computer_space_top)
# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# end ENTITY(computer_space_top)
# ------------------------------
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
@ -141,44 +171,25 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
# Assembler Assignments
# =====================
set_global_assignment -name GENERATE_RBF_FILE ON
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp3.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# --------------------------------
# start ENTITY(ComputerSpace_MiST)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(ComputerSpace_MiST)
# ------------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/ComputerSpace_MiST.sv
set_global_assignment -name VHDL_FILE rtl/computer_space_top.vhd
set_global_assignment -name VHDL_FILE rtl/computer_space_logic.vhd
set_global_assignment -name VHDL_FILE rtl/sync_star_board.vhd
set_global_assignment -name VHDL_FILE rtl/motion_board.vhd
set_global_assignment -name VHDL_FILE rtl/scan_counter.vhd
set_global_assignment -name VHDL_FILE rtl/v74161.vhd
set_global_assignment -name VHDL_FILE rtl/v74161_16bit.vhd
set_global_assignment -name VHDL_FILE rtl/memory_board.vhd
set_global_assignment -name VHDL_FILE rtl/saucer_diode_image.vhd
set_global_assignment -name VHDL_FILE rtl/rocket_diode_images.vhd
set_global_assignment -name VHDL_FILE rtl/clocks.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv
set_global_assignment -name VHDL_FILE rtl/computer_space_sound.vhd
set_global_assignment -name VERILOG_FILE rtl/scandoubler.v
set_global_assignment -name SDC_FILE ComputerSpace_MiST.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/dac.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/hq2x.sv
set_global_assignment -name VERILOG_FILE rtl/osd.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/mist_io.v
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

13
Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/ComputerSpace_MiST.sv
View File

@ -26,6 +26,9 @@ localparam CONF_STR = {
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign AUDIO_R = AUDIO_L;
assign LED = 1;
wire [31:0] status;
wire [1:0] buttons;
@ -34,14 +37,13 @@ wire scandoublerD;
wire ypbpr;
wire ps2_kbd_clk, ps2_kbd_data;
wire [15:0] audio;
wire [3:0] video;
wire [3:0] video;
wire hs, vs, blank;
assign LED = 1;
wire clk_sys, clk_25, clk_6p25, clk_5;
wire clk_sys, clk_25, clk_6p25, clk_5;
pll pll(
.inclk0(CLOCK_27),
.c0(clk_sys),//50 for game/sound generator?
.c0(clk_sys),//50 MHz for game/sound generator?
.c1(clk_25), //4x pixel clock
.c3(clk_5) //5,842 MHz pixel/game clock
);
@ -95,7 +97,7 @@ dac #(
.MSBI(15))
dac(
.DACout(AUDIO_L),
.DACin(audio),
.DACin({~audio[15], audio[14:0]}),
.CLK(clk_sys),
.RESET(0)
);
@ -149,7 +151,6 @@ computer_space_top computerspace(
.audio(audio)
);
assign AUDIO_R = AUDIO_L;
wire [5:0] rs,gs,bs, ro,go,bo, rc,gc,bc, rm,gm,bm;
wire [3:0] r, g, b;
assign r = blank ? 0 : (rm[5:4] ? 4'b1111 : rm[3:0]) ^ {4{inv}};

2
Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/build_id.v
View File

@ -1,2 +1,2 @@
`define BUILD_DATE "190307"
`define BUILD_TIME "202304"
`define BUILD_TIME "205523"

4
Arcade_MiST/Atari Discrete Logic/ComputerSpace_MiST/rtl/scan_counter.vhd
View File

@ -204,7 +204,9 @@ f1_12 <= ver_scan_q(6);
-----------------------------------------------------------------------------
-- Clear signal to star generator --
-----------------------------------------------------------------------------
b2_6 <= not f1_15;
b2_6 <= not f1_15;
-----------------------------------------------------------------------------
-- COUNT ENABLE & BLANK --