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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-11 23:43:09 +00:00

Vectrex: missed the .qsf changes

This commit is contained in:
Gyorgy Szombathelyi 2021-08-05 18:22:21 +02:00
parent 59446e123a
commit e2857a7443

View File

@ -347,18 +347,19 @@ set_global_assignment -name USE_SIGNALTAP_FILE output_files/sdram.stp
set_global_assignment -name SDC_FILE vectrex_MiST.out.sdc
set_global_assignment -name SYSTEMVERILOG_FILE rtl/vectrex_mist.sv
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VHDL_FILE rtl/vectrex.vhd
set_global_assignment -name VHDL_FILE rtl/vectrex_exec_prom.vhd
set_global_assignment -name VHDL_FILE rtl/m6522a.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/cpu09l_128a.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name VERILOG_FILE rtl/mc6809is.v
set_global_assignment -name VERILOG_FILE rtl/mc6809.v
set_global_assignment -name VHDL_FILE rtl/sp0256.vhd
set_global_assignment -name VHDL_FILE rtl/sp0256_al2_decoded.vhd
set_global_assignment -name VHDL_FILE rtl/vectrex_speakjet.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/YM2149.sv
set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
set_global_assignment -name VERILOG_FILE rtl/mc6809.v
set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/YM2149.vhd
set_global_assignment -name VHDL_FILE ../../common/Sound/ym2149/vol_table_array.vhd
set_global_assignment -name VERILOG_FILE ../../common/CPU/MC6809/mc6809is.v
set_global_assignment -name VHDL_FILE ../../common/CPU/MC6809/cpu09l_128a.vhd
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_global_assignment -name SIGNALTAP_FILE output_files/sdram.stp
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top