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Marcel
2019-07-17 22:47:43 +02:00
parent b338add40c
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30
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/MoonWar_MiST.qpf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 23:59:05 March 16, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "23:59:05 March 16, 2017"
# Revisions
PROJECT_REVISION = "MoonWar_MiST"

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Arcade_MiST/Berzerk Hardware/MoonWar_MiST/MoonWar_MiST.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 00:18:18 July 17, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# MoonWar_MiST_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:59:05 MARCH 16, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY Output
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/MoonWar_mist.sv
set_global_assignment -name VHDL_FILE rtl/berzerk.vhd
set_global_assignment -name VHDL_FILE rtl/video_gen.vhd
set_global_assignment -name VHDL_FILE rtl/berzerk_speech.vhd
set_global_assignment -name VHDL_FILE rtl/berzerk_sound_fx.vhd
set_global_assignment -name VHDL_FILE rtl/gen_ram.vhd
set_global_assignment -name VHDL_FILE rtl/rom/MoonWar_speech_rom.vhd
set_global_assignment -name VHDL_FILE rtl/rom/MoonWar_program2.vhd
set_global_assignment -name VHDL_FILE rtl/rom/MoonWar_program1.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80se.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name QIP_FILE ../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PIN_31 -to UART_RX
set_location_assignment PIN_46 -to UART_TX
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY MoonWar_mist
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# --------------------------
# start ENTITY(MoonWar_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(MoonWar_mist)
# ------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Berzerk Hardware/MoonWar_MiST/MoonWar_MiST.srf Normal file
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{ "" "" "" "VHDL Signal Declaration warning at berzerk.vhd(107): used implicit default value for signal \"dbg_cpu_di\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { } 0 10541 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL information at scandoubler.v(114): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""}
{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""}

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Arcade_MiST/Berzerk Hardware/MoonWar_MiST/README.txt Normal file
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Moon War Port to MiST
-------------------------------------------------
-- Berzerk FPGA by Dar - (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-------------------------------------------------
-- Berzerk releases
--
-- Release 0.0 - 07/07/2018 - Dar
-------------------------------------------------
Educational use only
Do not redistribute synthetized file with roms
Do not redistribute roms whatever the form
Use at your own risk
--------------------------------------------------------------------
make sure to use berzerk.zip roms
--------------------------------------------------------------------
--
-- Main features :
-- PS2 keyboard input @gpio pins 35/34 (beware voltage translation/protection)
-- Audio pwm output @gpio pins 1/3 (beware voltage translation/protection)
--
-- Uses 1 pll for 10MHz generation from 50MHz
--
-- Board key :
-- 0 : reset game
--
-- Board switch :
-- 1 : tv 15Khz mode / VGA 640x480 mode
--
-- Keyboard players inputs :
--
-- F3 : Add coin
-- F2 : Start 2 players
-- F1 : Start 1 player
-- SPACE : fire
-- RIGHT arrow : move right
-- LEFT arrow : move left
-- UP arrow : move up
-- DOWN arrow : move down
--
-- Sound effects : OK
-- Speech synthesis : todo
--
---------------
VHDL File list
---------------
max10_pll_10M.vhd Pll 10MHz from 50MHz altera mf
berzerk_de10_lite.vhd Top level for de10-lite board
berzerk.vhd Main logic
berzerk_sound_fx.vhd Music logic
berzerk_program1.vhd
berzerk_program2.vhd
video_gen.vhd Video scheduler, syncs (h,v and composite)
line_doubler.vhd Line doubler 15kHz -> 31kHz VGA
kbd_joystick.vhd Keyboard key to player/coin input
T80se.vhd T80 release 304
T80_Reg.vhd
T80_Pack.vhd
T80_MCode.vhd
T80_ALU.vhd
T80.vhd
io_ps2_keyboard.vhd Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
gen_ram.vhd
decodeur_7_seg.vhd for debug
----------------------
Quartus project files
----------------------
de10_lite/berzerk_de10_lite.qsf de10_lite settings (files,pins,...)
de10_lite/berzerk_de10_lite.qpf de10_lite project
de10_lite/berzerk_de10_lite.sdc timequest constraints
+----------------------------------------------------------------------------------+
; Fitter Summary ;
+------------------------------------+---------------------------------------------+
; Fitter Status ; Successful - Sat Jul 07 07:38:44 2018 ;
; Quartus Prime Version ; 16.1.0 Build 196 10/24/2016 SJ Lite Edition ;
; Revision Name ; berzerk_de10_lite ;
; Top-level Entity Name ; berzerk_de10_lite ;
; Family ; MAX 10 ;
; Device ; 10M50DAF484C6GES ;
; Timing Models ; Preliminary ;
; Total logic elements ; 3,277 / 49,760 ( 7 % ) ;
; Total combinational functions ; 3,043 / 49,760 ( 6 % ) ;
; Dedicated logic registers ; 886 / 49,760 ( 2 % ) ;
; Total registers ; 886 ;
; Total pins ; 121 / 360 ( 34 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 241,664 / 1,677,312 ( 14 % ) ;
; Embedded Multiplier 9-bit elements ; 0 / 288 ( 0 % ) ;
; Total PLLs ; 1 / 4 ( 25 % ) ;
; UFM blocks ; 0 / 1 ( 0 % ) ;
; ADC blocks ; 0 / 2 ( 0 % ) ;
+------------------------------------+---------------------------------------------+
-----------------------------
Required ROMs (Not included)
-----------------------------
You need the following 8 ROMs from berzerk.zip
berzerk_rc31_1c.rom0.1c CRC(ca566dbc) SHA1(fae2647f12f1cd82826db61b53b116a5e0c9f995)
berzerk_rc31_1d.rom1.1d CRC(7ba69fde) SHA1(69af170c4a39a3494dcd180737e5c87b455f9203)
berzerk_rc31_3d.rom2.3d CRC(a1d5248b) SHA1(a0b7842f6a5f86c16d80d78e7012c78b3ea11d1d)
berzerk_rc31_5d.rom3.5d CRC(fcaefa95) SHA1(07f849aa39f1e3db938187ffde4a46a588156ddc)
berzerk_rc31_6d.rom4.6d CRC(1e35b9a0) SHA1(5a5e549ec0e4803ab2d1eac6b3e7171aedf28244)
berzerk_rc31_5c.rom5.5c CRC(c8c665e5) SHA1(e9eca4b119549e0061384abf52327c14b0d56624)
berzerk_r_vo_1c.1c CRC(2cfe825d) SHA1(f12fed8712f20fa8213f606c4049a8144bfea42e)
berzerk_r_vo_2c.2c CRC(d2b6324e) SHA1(20a6611ad6ec19409ac138bdae7bdfaeab6c47cf)
------
Tools
------
You need to build vhdl ROM image files from the binary file :
- Unzip the roms file in the tools/berzerk_unzip directory
- Double click (execute) the script tools/berzerk_unzip/make_berzerk_proms.bat to get the following files
berzerk_program1.vhd
berzerk_program2.vhd
*DO NOT REDISTRIBUTE THESE FILES*
The script make_berzerk_proms uses make_vhdl_prom and and duplicate_byte executables delivered both in linux and windows version. The script itself is delivered only in windows version (.bat) but should be easily ported to linux.
Source code of make_vhdl_prom.c and and duplicate_byte.c is also delivered.
---------------------------------
Compiling for de10_lite
---------------------------------
You can rebuild the project with ROM image embeded in the sof file. DO NOT REDISTRIBUTE THESE FILES.
4 steps
- put the VHDL rom files into the project directory
- rebuild berzerk_de10_lite
- program berzerk_de10_lite.sof into the fpga
------------------------
End of file
------------------------

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Arcade_MiST/Berzerk Hardware/MoonWar_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
del /s *~
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
rmdir /s /q hc_output
rmdir /s /q .qsys_edit
rmdir /s /q hps_isw_handoff
rmdir /s /q sys\.qsys_edit
rmdir /s /q sys\vip
cd sys
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
cd ..
for /d %%i in (*_sim) do rmdir /s /q "%%~nxi"
del build_id.v
del c5_pin_model_dump.txt
del PLLJ_PLLSPE_INFO.txt
del /s *.qws
del /s *.ppf
del /s *.ddb
del /s *.csv
del /s *.cmp
del /s *.sip
del /s *.spd
del /s *.bsf
del /s *.f
del /s *.sopcinfo
del /s *.xml
del /s new_rtl_netlist
del /s old_rtl_netlist
pause

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Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/MoonWar_mist.sv Normal file
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module MoonWar_mist(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Moon War;;",
"O34,Scanlines,None,CRT 25%,CRT 50%,CRT 75%;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_10, clk_20;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_10),
.c1(clk_20)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [9:0] kbjoy;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [10:0] ps2_key;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire r, g, b;
wire [15:0] audio;
berzerk berzerk(
.clock_10(clk_10),
.reset(status[0] | status[6] | buttons[1]),
.video_r(r),
.video_g(g),
.video_b(b),
.video_hi(),
.video_clk(),
.video_csync(),
.video_hs(hs),
.video_vs(vs),
.video_hb(hb),
.video_vb(vb),
.audio_out(audio),
.hyperflip(m_hyperflip),//Cocktail Only
.coin1(btn_coin),
.start1(btn_one_player),//not working- activate hyperflip maybe DIP Setting
.start2(btn_two_players),
.fire3(m_fire3),//mines
.fire2(m_fire2),//thrust
.fire1(m_fire1),//bolts
.cleft(m_left),
.cright(m_right),
.ledr(),
.dbg_cpu_di(),
.dbg_cpu_addr(),
.dbg_cpu_addr_latch()
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(9)) mist_video(
.clk_sys(clk_20),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R(blankn ? {r,r,r} : 0),
.G(blankn ? {g,g,g} : 0),
.B(blankn ? {b,b,b} : 0),
.HSync(~hs),
.VSync(~vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.ce_divider(0),
.rotate({1'b1,status[2]}),
.scandoubler_disable(scandoublerD),
.scanlines(scandoublerD ? 2'b00 : status[4:3]),
.ypbpr(ypbpr)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_20 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.C_bits(15))
dac(
.clk_i(clk_20),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
wire m_up = btn_up | joystick_0[3] | joystick_1[3];
wire m_down = btn_down | joystick_0[2] | joystick_1[2];
wire m_left = btn_left | joystick_0[1] | joystick_1[1];
wire m_right = btn_right | joystick_0[0] | joystick_1[0];
wire m_fire1 = btn_fire1 | joystick_0[4] | joystick_1[4];//Bolts
wire m_fire2 = btn_fire2 | joystick_0[5] | joystick_1[5];//thrust
wire m_fire3 = btn_fire3 | joystick_0[6] | joystick_1[6];//mines
wire m_hyperflip = btn_test | joystick_0[7] | joystick_1[7];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_test = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
reg btn_fire3 = 0;
reg btn_coin = 0;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
always @(posedge clk_20) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_test <= key_pressed; // F3
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <=key_pressed; // Space
endcase
end
end
endmodule

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T8080se.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 1 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
RD_n <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
RD_n <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
RD_n <= '1';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
RD_n <= '1';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80_ALU.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
-- bug fix - parity flag is just parity for 8080, also overflow for Z80
process (Carry_v, Carry7_v, Q_v)
begin
if(Mode=2) then
OverFlow_v <= not (Q_v(0) xor Q_v(1) xor Q_v(2) xor Q_v(3) xor
Q_v(4) xor Q_v(5) xor Q_v(6) xor Q_v(7)); else
OverFlow_v <= Carry_v xor Carry7_v;
end if;
end process;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80_Pack.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 304 init values of registers on first startup (better simulation)
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80_Reg.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- T80 Registers, technology independent
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
-- Wolfgang Scherr 2011-2015 (email: WoS <at> pin4 <dot> at)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7) := (others => (others => '0'));
signal RegsL : Register_Image(0 to 7) := (others => (others => '0'));
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80a.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- Z80 compatible microprocessor core, asynchronous top level
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0211 : Fixed interrupt cycle
--
-- 0235 : Updated for T80 interface change
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80a is
generic(
Mode : integer := 0 -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
D : inout std_logic_vector(7 downto 0)
);
end T80a;
architecture rtl of T80a is
signal CEN : std_logic;
signal Reset_s : std_logic;
signal IntCycle_n : std_logic;
signal IORQ : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal MREQ : std_logic;
signal MReq_Inhibit : std_logic;
signal Req_Inhibit : std_logic;
signal RD : std_logic;
signal MREQ_n_i : std_logic;
signal IORQ_n_i : std_logic;
signal RD_n_i : std_logic;
signal WR_n_i : std_logic;
signal RFSH_n_i : std_logic;
signal BUSAK_n_i : std_logic;
signal A_i : std_logic_vector(15 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector (7 downto 0); -- Input synchroniser
signal Wait_s : std_logic;
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
CEN <= '1';
BUSAK_n <= BUSAK_n_i;
MREQ_n_i <= not MREQ or (Req_Inhibit and MReq_Inhibit);
RD_n_i <= not RD or Req_Inhibit;
MREQ_n <= MREQ_n_i when BUSAK_n_i = '1' else 'Z';
IORQ_n <= IORQ_n_i when BUSAK_n_i = '1' else 'Z';
RD_n <= RD_n_i when BUSAK_n_i = '1' else 'Z';
WR_n <= WR_n_i when BUSAK_n_i = '1' else 'Z';
RFSH_n <= RFSH_n_i when BUSAK_n_i = '1' else 'Z';
A <= A_i when BUSAK_n_i = '1' else (others => 'Z');
D <= DO when Write = '1' and BUSAK_n_i = '1' else (others => 'Z');
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
Reset_s <= '0';
elsif CLK_n'event and CLK_n = '1' then
Reset_s <= '1';
end if;
end process;
u0 : T80
generic map(
Mode => Mode,
IOWait => 1)
port map(
CEN => CEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n_i,
HALT_n => HALT_n,
WAIT_n => Wait_s,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => Reset_s,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n_i,
CLK_n => CLK_n,
A => A_i,
DInst => D,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (CLK_n)
begin
if CLK_n'event and CLK_n = '0' then
Wait_s <= WAIT_n;
if TState = "011" and BUSAK_n_i = '1' then
DI_Reg <= to_x01(D);
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
WR_n_i <= '1';
elsif CLK_n'event and CLK_n = '1' then
WR_n_i <= '1';
if TState = "001" then -- To short for IO writes !!!!!!!!!!!!!!!!!!!
WR_n_i <= not Write;
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
Req_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '1' then
if MCycle = "001" and TState = "010" then
Req_Inhibit <= '1';
else
Req_Inhibit <= '0';
end if;
end if;
end process;
process (Reset_s,CLK_n)
begin
if Reset_s = '0' then
MReq_Inhibit <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" and TState = "010" then
MReq_Inhibit <= '1';
else
MReq_Inhibit <= '0';
end if;
end if;
end process;
process(Reset_s,CLK_n)
begin
if Reset_s = '0' then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
elsif CLK_n'event and CLK_n = '0' then
if MCycle = "001" then
if TState = "001" then
RD <= IntCycle_n;
MREQ <= IntCycle_n;
IORQ_n_i <= IntCycle_n;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '1';
end if;
if TState = "100" then
MREQ <= '0';
end if;
else
if TState = "001" and NoRead = '0' then
RD <= not Write;
IORQ_n_i <= not IORQ;
MREQ <= not IORQ;
end if;
if TState = "011" then
RD <= '0';
IORQ_n_i <= '1';
MREQ <= '0';
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80se.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- Z80 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original z80
-- Inputs needs to be synchronous and outputs may glitch
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80se is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0; -- 0 => WR_n active in T3, /=0 => WR_n active in T2
IOWait : integer := 1 -- 0 => Single cycle I/O, 1 => Std I/O cycle
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80se;
architecture rtl of T80se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => Mode,
IOWait => IOWait)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
else
if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
--
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- $Id: T80sed.vhd 1330 2015-05-22 19:55:46Z wolfgang.scherr $
--
-- ****
--
-- ** CUSTOM 2 CLOCK MEMORY ACCESS FOR PACMAN, MIKEJ **
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0235 : First release
--
-- 0236 : Added T2Write generic
--
-- 0237 : Fixed T2Write with wait state
--
-- 0238 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80sed is
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CLKEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
MREQ_n : out std_logic;
IORQ_n : out std_logic;
RD_n : out std_logic;
WR_n : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T80sed;
architecture rtl of T80sed is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
begin
u0 : T80
generic map(
Mode => 0,
IOWait => 1)
port map(
CEN => CLKEN,
M1_n => M1_n,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => RFSH_n,
HALT_n => HALT_n,
WAIT_n => Wait_n,
INT_n => INT_n,
NMI_n => NMI_n,
RESET_n => RESET_n,
BUSRQ_n => BUSRQ_n,
BUSAK_n => BUSAK_n,
CLK_n => CLK_n,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n);
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
DI_Reg <= "00000000";
elsif CLK_n'event and CLK_n = '1' then
if CLKEN = '1' then
RD_n <= '1';
WR_n <= '1';
IORQ_n <= '1';
MREQ_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and Wait_n = '0') then
RD_n <= not IntCycle_n;
MREQ_n <= not IntCycle_n;
IORQ_n <= IntCycle_n;
end if;
if TState = "011" then
MREQ_n <= '0';
end if;
else
if (TState = "001" or TState = "010") and NoRead = '0' and Write = '0' then
RD_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
if ((TState = "001") or (TState = "010")) and Write = '1' then
WR_n <= '0';
IORQ_n <= not IORQ;
MREQ_n <= IORQ;
end if;
end if;
if TState = "010" and Wait_n = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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@@ -0,0 +1,617 @@
----------------------------------------------------------------------------------
-- berzerk by Dar (darfpga@aol.fr) (June 2018)
-- http://darfpga.blogspot.fr
----------------------------------------------------------------------------------
-- Educational use only
-- Do not redistribute synthetized file with roms
-- Do not redistribute roms whatever the form
-- Use at your own risk
---------------------------------------------------------------------------------
-- T80/T80se - Version : 0304 /!\ (0247 has some interrupt vector problems)
-----------------------------
-- Z80 compatible microprocessor core
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
-- MikeJ March 2005
-- Wolfgang Scherr 2011-2015 (email: WoS <at> pin4 <dot> at)
---------------------------------------------------------------------------------
-- gen_ram.vhd & io_ps2_keyboard
--------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
-- Use berzerk_de10_lite.sdc to compile (Timequest constraints)
-- /!\
-- Don't forget to set device configuration mode with memory initialization
-- (Assignments/Device/Pin options/Configuration mode)
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
--
-- Berzerk has not graphics tile nor sprite. Instead berzerk use a 1 pixel video
-- buffer and a color map buffer.
--
-- Video buffer is 256 pixels x 224 lines : 32 x 224 bytes
--
-- Video buffer can be written by cpu @4000-5fff (normal write : cpu_do => vram_di)
-- video buffer and working ram share the same ram.
--
-- Video buffer can be written by cpu @6000-7fff
-- in that case the written cpu data can be shifted and completed with previous written data
-- then the result can be bit reversed 0..7 => 7..0 (flopper)
-- then the result can be combined (alu) with the current video data at that address
-- shift/flop and alu function are controled by data written at I/O 0x4B
-- during such write flopper output is compared with current video data to detect
-- pixel colision (called intercept)
--
-- color buffer is @8000-87ff :32x64 area of 1 byte
-- one byte covers 2x4 pixels and 4 lines.
-- bits 7-4 => 4 pixels of color1
-- bits 3-0 => 4 pixels of color2
-- color 4bits : intensity/blue/green/red
--
-- Sound effects uses a ptm6840 timer (3 channel) + noise generator and volume control
--
--
-----------------------------------------------------------------------------------------------
-- Problème rencontré : cpu_int acquitée par iorq durant le cylce de capture du vecteur
-- d'interruption => mauvais vecteur lu => plantage un peu plus tard.
--
-- Solution : ajouter m1_n dans l'equation d'acquitement de int.
-----------------------------------------------------------------------------------------------
-- Mame command reminder
-- wpiset 40,1,w,1,{printf "a:%08x d:%02X",wpaddr,wpdata; g}
-- wpiset 40,1,w,(wpdata!=0) && (wpdata!=90) && (wpdata!=92),{printf "a:%08x d:%02X",wpaddr,wpdata; g}
-----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity berzerk is
port(
clock_10 : in std_logic;
reset : in std_logic;
video_r : out std_logic;
video_g : out std_logic;
video_b : out std_logic;
video_hi : out std_logic;
video_clk : out std_logic;
video_csync : out std_logic;
video_hs : out std_logic;
video_vs : out std_logic;
video_hb : out std_logic;
video_vb : out std_logic;
audio_out : out std_logic_vector(15 downto 0);
hyperflip : in std_logic;
coin1 : in std_logic;
start1 : in std_logic;
start2 : in std_logic;
fire3 : in std_logic;
fire2 : in std_logic;
fire1 : in std_logic;
cleft : in std_logic;
cright : in std_logic;
sw : in std_logic_vector(9 downto 0);
ledr : out std_logic_vector(9 downto 0) := "0000000000";
dbg_cpu_di : out std_logic_vector( 7 downto 0);
dbg_cpu_addr : out std_logic_vector(15 downto 0);
dbg_cpu_addr_latch : out std_logic_vector(15 downto 0)
);
end berzerk;
architecture struct of berzerk is
-- clocks
signal clock_10n : std_logic;
signal reset_n : std_logic;
-- video syncs
signal hsync : std_logic;
signal vsync : std_logic;
signal csync : std_logic;
signal blank : std_logic;
-- global synchronisation
signal ena_pixel : std_logic := '0';
signal hcnt : std_logic_vector(8 downto 0);
signal vcnt : std_logic_vector(8 downto 0);
signal hcnt_r : std_logic_vector(8 downto 0);
signal vcnt_r : std_logic_vector(8 downto 0);
-- Z80 interface
signal cpu_clock : std_logic;
signal cpu_wr_n : std_logic;
signal cpu_addr : std_logic_vector(15 downto 0);
signal cpu_do : std_logic_vector(7 downto 0);
signal cpu_di : std_logic_vector(7 downto 0);
signal cpu_di_r : std_logic_vector(7 downto 0);
signal cpu_mreq_n : std_logic;
signal cpu_m1_n : std_logic;
signal cpu_int_n : std_logic := '1';
signal cpu_nmi_n : std_logic := '1';
signal cpu_iorq_n : std_logic;
signal cpu_di_mem : std_logic_vector(7 downto 0);
signal cpu_di_io : std_logic_vector(7 downto 0);
-- rom/ram addr/we/do
signal prog2_rom_addr : std_logic_vector(15 downto 0);
signal prog1_do : std_logic_vector(7 downto 0);
signal prog2_do : std_logic_vector(7 downto 0);
signal mosram_do : std_logic_vector(7 downto 0);
signal mosram_we : std_logic;
signal vram_addr : std_logic_vector(12 downto 0);
signal vram_di : std_logic_vector( 7 downto 0);
signal vram_do : std_logic_vector( 7 downto 0);
signal vram_we : std_logic;
signal cram_addr : std_logic_vector(10 downto 0);
signal cram_do : std_logic_vector(7 downto 0);
signal cram_we : std_logic;
-- I/O chip seclect
signal io1_cs : std_logic;
signal io2_cs : std_logic;
-- misc
signal int_enable : std_logic;
signal nmi_enable : std_logic;
signal inta : std_logic;
signal vcnt_int : std_logic;
signal vcnt_int_r : std_logic;
signal led_on : std_logic;
--signal intercept : std_logic;
signal intercept_latch : std_logic;
-- grapihcs computation
signal shifter_flopper_alu_cmd : std_logic_vector(7 downto 0);
signal last_data_written : std_logic_vector(6 downto 0);
signal shifter_do : std_logic_vector(7 downto 0);
signal flopper_do : std_logic_vector(7 downto 0);
signal alu_do : std_logic_vector(7 downto 0);
signal vram_do_latch : std_logic_vector(7 downto 0);
-- graphics data
signal graphx : std_logic_vector (7 downto 0);
signal colors : std_logic_vector (7 downto 0);
signal color : std_logic_vector (3 downto 0);
-- player I/O
signal player1 : std_logic_vector(7 downto 0);
signal player2 : std_logic_vector(7 downto 0);
signal system : std_logic_vector(7 downto 0);
-- line doubler I/O
signal video : std_logic_vector (3 downto 0);
signal video_i : std_logic_vector (3 downto 0);
signal video_o : std_logic_vector (3 downto 0);
signal video_s : std_logic_vector (3 downto 0);
signal hsync_o : std_logic;
signal vsync_o : std_logic;
signal sound_out : std_logic_vector(11 downto 0);
signal speech_out : std_logic_vector(11 downto 0);
signal speech_busy : std_logic;
signal dail : std_logic_vector(4 downto 0);
begin
process(cpu_clock)
begin
--dail <= "01111";
if (cleft = '1') then dail <= dail-1; elsif (cright = '1') then dail <= dail+1; end if;
end process;
audio_out <= ("00"&speech_out&"00")+('0'&sound_out&"000");
clock_10n <= not clock_10;
reset_n <= not reset;
ledr(0) <= led_on;
----------
-- debug
----------
dbg_cpu_addr <= cpu_addr;
process(cpu_clock, reset)
begin
if rising_edge(cpu_clock) then
if cpu_m1_n = '0' then
dbg_cpu_addr_latch <= cpu_addr;
end if;
end if;
end process;
-----------------------
-- Enable pixel counter
-- and cpu clock
-----------------------
process(clock_10, reset)
begin
if reset = '1' then
ena_pixel <= '0';
else
if rising_edge(clock_10) then
ena_pixel <= not ena_pixel;
end if;
end if;
end process;
cpu_clock <= hcnt(0);
------------------
-- video output
------------------
-- demux color nibbles
color <= colors(7 downto 4) when hcnt(2) = '0' else colors(3 downto 0);
-- serialize video byte
video <= color when graphx(to_integer(unsigned(not hcnt(2 downto 0)))) = '1' else "0000";
-----------------------
-- cpu write addressing
-- cpu I/O chips select
----------------------- 111110 0000000000
mosram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 10) = "111110" else '0'; -- 0800-0bff 000010 0000000000
vram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 14) = "01" and cpu_clock = '0' else '0'; -- 4000-5fff mirror 6000-7fff
cram_we <= '1' when cpu_mreq_n = '0' and cpu_wr_n = '0' and cpu_addr(15 downto 11) = "10000" and cpu_clock = '0' else '0'; -- 8000-87ff
io1_cs <= '1' when cpu_iorq_n ='0' and cpu_m1_n = '1' and cpu_addr(7 downto 4) = "0100" else '0'; -- x40-x4f
io2_cs <= '1' when cpu_iorq_n ='0' and cpu_m1_n = '1' and cpu_addr(7 downto 5) = "011" else '0'; -- x60-x7f
---------------------------
-- enable/disable interrupt
-- latch/clear interrupt
-- led
---------------------------
vcnt_int <= (not(vcnt(6)) and vcnt(7)) or vcnt(8);
process (cpu_clock, reset)
begin
if reset = '1' then
nmi_enable <= '0';
int_enable <= '0';
led_on <= '0';
else
if rising_edge(cpu_clock) then
if io1_cs ='1' then
if cpu_addr(3 downto 0) = "1100" then nmi_enable <= '1'; end if; -- 4c
if cpu_addr(3 downto 0) = "1101" then nmi_enable <= '0'; end if; -- 4d
if cpu_addr(3 downto 0) = "1111" and cpu_wr_n = '0' then int_enable <= cpu_do(0); end if; -- 4f
end if;
if io2_cs ='1' then
if cpu_addr(2 downto 0) = "110" then led_on <= '0'; end if; -- 66
if cpu_addr(2 downto 0) = "111" then led_on <= '1'; end if; -- 67
end if;
end if;
end if;
end process;
process (clock_10, cpu_iorq_n, cpu_addr, reset)
begin
if reset = '1' then
cpu_int_n <= '1';
cpu_nmi_n <= '1';
else
if rising_edge(clock_10) then
vcnt_r <= vcnt;
vcnt_int_r <= vcnt_int;
if nmi_enable = '1' then
if vcnt_r(4) = '0' and vcnt(4) = '1' then cpu_nmi_n <= '0';end if;
if hcnt_r(0) = '0' and hcnt(0) = '1' then cpu_nmi_n <= '1';end if;
else
cpu_nmi_n <= '1';
end if;
end if;
if rising_edge(clock_10) then
if cpu_iorq_n ='0' then
-- m1_n avoid clear interrupt during vector reading
if cpu_addr(7 downto 0) = X"4e" and cpu_m1_n = '1' then cpu_int_n <= '1'; end if;
end if;
if int_enable = '1' then
if vcnt_int_r = '0' and vcnt_int = '1' then cpu_int_n <= '0';end if;
end if;
end if;
end if;
end process;
------------------------------------
-- mux cpu data mem read and io read
------------------------------------
-- memory mux
with cpu_addr(15 downto 11) select
cpu_di_mem <=
prog1_do when "00000", -- 0000-07ff 16k 00
prog1_do when "00001", -- 0800-0fff 16k 00
prog1_do when "00010", -- 1000-17ff 16k 01
prog1_do when "00011", -- 1800-1fff 16k 01
prog1_do when "00100", -- 2000-27ff 16k 01
prog1_do when "00101", -- 2800-2fff 16k 10
prog1_do when "00110", -- 3000-37ff 16k 11
prog1_do when "00111", -- 3800-3fff 16k 11
vram_do when "01000", -- 4000-47ff
vram_do when "01001", -- 4800-4fff
vram_do when "01010", -- 5000-57ff
vram_do when "01011", -- 5800-5fff
vram_do when "01100", -- 6000-67ff
vram_do when "01101", -- 6800-6fff
vram_do when "01110", -- 7000-77ff
vram_do when "01111", -- 7800-7fff
cram_do when "10000", -- 8000-87ff 10000 00000000000
prog2_do when "11000", -- c000-c7ff 4k 11000 00000000000
prog2_do when "11001", -- c800-cfff 4k 11001 00000000000
mosram_do when "11111", -- f800-fbff 11111 00000000000
x"FF" when others;
-- I/O-2 mux
with cpu_addr(2 downto 0) select
cpu_di_io <=
X"00" when "000", -- 60 (F3)
X"F8" when "001", -- 61 (F2)
X"FF" when "010", -- 62 (F6)
X"FF" when "011", -- 63 (F5)
X"FF" when "100", -- 64 (F4)
X"00" when "101", -- 65 (SW2)
X"00" when "110", -- 66 (led on )
X"00" when "111", -- 67 (led off)
X"00" when others;
------------------
-- player controls
------------------
player1 <= not(fire1 & fire2 & fire3 & dail);--todo dail
player2 <= not(fire1 & fire2 & fire3 & dail);--todo dail
--system <= not(coin1 & "000" & hyperflip & '0' & start2 & start1);
system <= not(coin1 & "00000" & start2 & start1);
-- I/O-1 and final mux 00011111
-- pull up on ZPU board
cpu_di <= "111111" & cpu_int_n & '0' when cpu_iorq_n = '0' and cpu_m1_n = '0' -- interrupt vector
else '0'&not(speech_busy)&"000000" when io1_cs = '1' and cpu_addr(3 downto 0) = X"4" -- speech board
else player1 when io1_cs = '1' and cpu_addr(3 downto 0) = X"8" -- P1
else system when io1_cs = '1' and cpu_addr(3 downto 0) = X"9" -- sys
else player2 when io1_cs = '1' and cpu_addr(3 downto 0) = X"a" -- P2
else intercept_latch & "111111" & vcnt(8) when io1_cs = '1' and cpu_addr(3 downto 0) = X"e"
else cpu_di_io when io2_cs = '1'
else cpu_di_mem;
-- video memory computation
process(clock_10, reset)
begin
if reset = '1' then
shifter_flopper_alu_cmd <= (others => '0');
else
if rising_edge(clock_10) then
if cpu_clock = '0' and ena_pixel = '1' then
vram_do_latch <= vram_do;
end if;
if vram_we = '1' and cpu_addr(13) = '1' then
if ena_pixel = '1' then
last_data_written <= cpu_do(6 downto 0);
if (vram_do_latch and flopper_do) /= X"00" then
intercept_latch <= '1';
end if;
end if;
end if;
if io1_cs = '1' then
if cpu_addr(3 downto 0) = "1011" then -- 4b
shifter_flopper_alu_cmd <= cpu_do;
last_data_written <= (others => '0');
intercept_latch <= '0';
end if;
end if;
end if;
end if;
end process;
-- shifter - flopper
with shifter_flopper_alu_cmd(2 downto 0) select
shifter_do <= cpu_do(7 downto 0) when "000",
last_data_written( 0) & cpu_do(7 downto 1) when "001",
last_data_written(1 downto 0) & cpu_do(7 downto 2) when "010",
last_data_written(2 downto 0) & cpu_do(7 downto 3) when "011",
last_data_written(3 downto 0) & cpu_do(7 downto 4) when "100",
last_data_written(4 downto 0) & cpu_do(7 downto 5) when "101",
last_data_written(5 downto 0) & cpu_do(7 downto 6) when "110",
last_data_written(6 downto 0) & cpu_do(7 ) when others;
with shifter_flopper_alu_cmd(3) select
flopper_do <= shifter_do when '0',
shifter_do(0)&shifter_do(1)&shifter_do(2)&shifter_do(3)&
shifter_do(4)&shifter_do(5)&shifter_do(6)&shifter_do(7) when others;
-- 74181 - alu (logical computation only)
with not(shifter_flopper_alu_cmd(7 downto 4)) select
alu_do <= not flopper_do when "0000",
not(flopper_do or vram_do_latch) when "0001",
not(flopper_do) and vram_do_latch when "0010",
X"00" when "0011",
not(flopper_do and vram_do_latch) when "0100",
not(vram_do_latch) when "0101",
flopper_do xor vram_do_latch when "0110",
flopper_do and not(vram_do_latch) when "0111",
not(flopper_do) or vram_do_latch when "1000",
not(flopper_do xor vram_do_latch) when "1001",
vram_do_latch when "1010",
flopper_do and vram_do_latch when "1011",
X"FF" when "1100",
flopper_do or not(vram_do_latch) when "1101",
flopper_do or vram_do_latch when "1110",
flopper_do when others;
------------------------------------------------------
-- video & color ram address/data mux
------------------------------------------------------
with cpu_addr(13) select
vram_di <= cpu_do when '0',
alu_do when others;
vram_addr <= cpu_addr(12 downto 0) when cpu_clock = '0'
else vcnt(7 downto 0) & hcnt(7 downto 3);
cram_addr <= cpu_addr(10 downto 0) when cpu_clock = '0'
else vcnt(7 downto 2) & hcnt(7 downto 3);
-------------------------------------------------------
-- video & color ram read
-------------------------------------------------------
process(clock_10)
begin
if rising_edge(clock_10) then
if hcnt(2 downto 0) = "111" and ena_pixel = '1' then
graphx <= vram_do;
colors <= cram_do;
end if;
end if;
end process;
-- Sync and video counters
video_gen : entity work.video_gen
port map (
clock => clock_10,
reset => reset,
ena_pixel => ena_pixel,
hsync => hsync,
vsync => vsync,
csync => csync,
hblank => video_hb,
vblank => video_vb,
hcnt_o => hcnt,
vcnt_o => vcnt
);
video_s <= video;
video_hs <= hsync;
video_vs <= vsync;
video_r <= video_s(0);
video_g <= video_s(1);
video_b <= video_s(2);
video_hi <= video_s(3);
video_clk <= clock_10;
video_csync <= csync;
-- Z80
Z80 : entity work.T80se
generic map(Mode => 0, T2Write => 1, IOWait => 1)
port map(
RESET_n => reset_n,
CLK_n => cpu_clock,
CLKEN => '1',
WAIT_n => '1',
INT_n => cpu_int_n,
NMI_n => cpu_nmi_n,
BUSRQ_n => '1',
M1_n => cpu_m1_n,
MREQ_n => cpu_mreq_n,
IORQ_n => cpu_iorq_n,
RD_n => open,
WR_n => cpu_wr_n,
RFSH_n => open,
HALT_n => open,
BUSAK_n => open,
A => cpu_addr,
DI => cpu_di,
DO => cpu_do
);
-- program roms
program1 : entity work.MoonWar_program1
port map (
addr => cpu_addr(13 downto 0),
clk => clock_10n,
data => prog1_do
);
prog2_rom_addr <= cpu_addr-X"c000";
program2 : entity work.MoonWar_program2
port map (
addr => cpu_addr(11 downto 0),
clk => clock_10n,
data => prog2_do
);
-- working ram - 0800-0bff
mosram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 10)
port map(
clk => clock_10n,
we => mosram_we,
addr => cpu_addr( 9 downto 0),
d => cpu_do,
q => mosram_do
);
-- video/working ram - 4000-5fff mirrored 6000-7fff
vram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 13)
port map(
clk => clock_10n,
we => vram_we,
addr => vram_addr,
d => vram_di,
q => vram_do
);
-- color ram - 8000-87ff
cram : entity work.gen_ram
generic map( dWidth => 8, aWidth => 11)
port map(
clk => clock_10n,
we => cram_we,
addr => cram_addr,
d => cpu_do,
q => cram_do
);
-- sound effects
berzerk_sound_fx : entity work.berzerk_sound_fx
port map(
clock => cpu_clock,
reset => reset,
cs => io1_cs,
addr => cpu_addr(4 downto 0),
di => cpu_do,
sample => sound_out
);
-- speech synthesis (s14001a)
berzerk_speech : entity work.berzerk_speech
port map(
sw => sw,
clock => cpu_clock,
reset => reset,
cs => io1_cs,
wr_n => cpu_wr_n,
addr => cpu_addr(4 downto 0),
di => cpu_do,
busy => speech_busy,
sample => speech_out
);
------------------------------------------
end architecture;

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---------------------------------------------------------------------------------
-- Berzerk sound effects - Dar - July 2018
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity berzerk_sound_fx is
port (
clock : in std_logic;
reset : in std_logic;
cs : in std_logic;
addr : in std_logic_vector(4 downto 0);
di : in std_logic_vector(7 downto 0);
sample : out std_logic_vector(11 downto 0)
);
end berzerk_sound_fx;
architecture struct of berzerk_sound_fx is
signal hdiv : std_logic_vector(1 downto 0);
signal ena_internal_clock : std_logic;
signal ptm6840_msb_buffer : std_logic_vector(7 downto 0);
signal ptm6840_max1 : std_logic_vector(15 downto 0);
signal ptm6840_max2 : std_logic_vector(15 downto 0);
signal ptm6840_max3 : std_logic_vector(15 downto 0);
signal ptm6840_cnt1 : std_logic_vector(15 downto 0);
signal ptm6840_cnt2 : std_logic_vector(15 downto 0);
signal ptm6840_cnt3 : std_logic_vector(15 downto 0);
signal ptm6840_ctrl1 : std_logic_vector(7 downto 0);
signal ptm6840_ctrl2 : std_logic_vector(7 downto 0);
signal ptm6840_ctrl3 : std_logic_vector(7 downto 0);
signal ptm6840_q1 : std_logic;
signal ptm6840_q2 : std_logic;
signal ptm6840_q3 : std_logic;
signal ctrl_noise_and_ch1 : std_logic_vector(1 downto 0);
signal ctrl_vol_ch1 : std_logic_vector(2 downto 0);
signal ctrl_vol_ch2 : std_logic_vector(2 downto 0);
signal ctrl_vol_ch3 : std_logic_vector(2 downto 0);
type vol_type is array(0 to 7) of unsigned(7 downto 0);
constant vol : vol_type := (X"01", X"02", X"04", X"08", X"10", X"20", X"40", X"80");
signal snd1 : signed(8 downto 0);
signal snd2 : signed(8 downto 0);
signal snd3 : signed(8 downto 0);
--signal snd : std_logic_vector(11 downto 0);
signal ptm6840_q1_r : std_logic;
signal ena_q1_clock : std_logic;
signal noise_xor, noise_xor_r : std_logic;
signal noise_shift_reg : std_logic_vector(127 downto 0) := (others => '1');
signal noise_shift_reg_95_r : std_logic;
signal ena_external_clock : std_logic;
begin
sample <= std_logic_vector(snd1+snd2+snd3) + X"7FF";
-- make enable signal to replace misc clocks
process(clock)
begin
if rising_edge(clock) then
-- ptm_6840 E input pin (internal clock)
-- board input clock divide by 4
if hdiv = "11" then
hdiv <= "00";
ena_internal_clock <= '1';
else
hdiv <= std_logic_vector(unsigned(hdiv) + 1);
ena_internal_clock <= '0';
end if;
-- ptm6840_q1 is used for alternate noise generator clock
ptm6840_q1_r <= ptm6840_q1;
if ptm6840_q1_r = '0' and ptm6840_q1 = '1' then
ena_q1_clock <= '1';
else
ena_q1_clock <= '0';
end if;
-- noise generator ouput is use for ptm6840 external clocks (C1, C2, C3)
noise_shift_reg_95_r <= noise_shift_reg(95);
if noise_shift_reg_95_r = '0' and noise_shift_reg(95) = '1' then
ena_external_clock <= '1';
else
ena_external_clock <= '0';
end if;
end if;
end process;
--control/registers interface with cpu addr/data
ctrl_regs : process(clock, reset)
begin
if reset = '1' then
ptm6840_ctrl1 <= X"01";
ptm6840_ctrl2 <= (others => '0');
ptm6840_ctrl3 <= (others => '0');
ctrl_noise_and_ch1 <= (others => '0');
ctrl_vol_ch1 <= (others => '0');
ctrl_vol_ch2 <= (others => '0');
ctrl_vol_ch3 <= (others => '0');
else
if rising_edge(clock) then
if cs = '1' and addr(4 downto 3) = "00" then
case addr(2 downto 0) is
when "000" =>
if ptm6840_ctrl2(0) = '1' then
ptm6840_ctrl1 <= di;
else
ptm6840_ctrl3 <= di;
end if;
when "001" =>
ptm6840_ctrl2 <= di;
when "011" =>
ptm6840_max1 <= ptm6840_msb_buffer & di;
when "101" =>
ptm6840_max2 <= ptm6840_msb_buffer & di;
when "111" =>
ptm6840_max3 <= ptm6840_msb_buffer & di;
when "110" =>
-- ptm6840_msb_buffer <= di;
case di(7 downto 6) is
when "00" =>
ctrl_noise_and_ch1 <= di(1 downto 0);
when "01" =>
ctrl_vol_ch1 <= di(2 downto 0);
when "10" =>
ctrl_vol_ch2 <= di(2 downto 0);
when others =>
ctrl_vol_ch3 <= di(2 downto 0);
end case;
when others =>
ptm6840_msb_buffer <= di;
end case;
end if;
end if;
end if;
end process;
-- simplified ptm6840 (only useful part for berzerk)
-- only synthesis mode
-- 16 bits count mode only (no dual 8 bits mode)
-- count on internal or external clock
-- no status
-- no IRQ
-- no gates input
counters : process(clock, reset, ptm6840_max1, ptm6840_max2, ptm6840_max3)
begin
if reset = '1' then
ptm6840_cnt1 <= ptm6840_max1;
ptm6840_cnt2 <= ptm6840_max2;
ptm6840_cnt3 <= ptm6840_max3;
ptm6840_q1 <= '0';
ptm6840_q2 <= '0';
ptm6840_q3 <= '0';
else
if rising_edge(clock) then
if ptm6840_ctrl1(0) = '0' then
-- counter #1
if (ptm6840_ctrl1(1) = '1' and ena_internal_clock = '1') or
(ptm6840_ctrl1(1) = '0' and ena_external_clock = '1') then
if ptm6840_cnt1 = X"0000" then
ptm6840_cnt1 <= ptm6840_max1;
ptm6840_q1 <= not ptm6840_q1;
else
ptm6840_cnt1 <= ptm6840_cnt1 - '1';
end if;
end if;
-- counter #2
if (ptm6840_ctrl2(1) = '1' and ena_internal_clock = '1') or
(ptm6840_ctrl2(1) = '0' and ena_external_clock = '1') then
if ptm6840_cnt2 = X"0000" then
ptm6840_cnt2 <= ptm6840_max2;
ptm6840_q2 <= not ptm6840_q2;
else
ptm6840_cnt2 <= ptm6840_cnt2 - '1';
end if;
end if;
-- counter #3
if (ptm6840_ctrl3(1) = '1' and ena_internal_clock = '1') or
(ptm6840_ctrl3(1) = '0' and ena_external_clock = '1') then
if ptm6840_cnt3 = X"0000" then
ptm6840_cnt3 <= ptm6840_max3;
ptm6840_q3 <= not ptm6840_q3;
else
ptm6840_cnt3 <= ptm6840_cnt3 - '1';
end if;
end if;
else
ptm6840_cnt1 <= ptm6840_max1;
ptm6840_cnt2 <= ptm6840_max2;
ptm6840_cnt3 <= ptm6840_max3;
end if;
-- fx channel #1 enable and volume
-- channel #1 output is OFF when q1 drive noise generator clock
snd1 <= (others=>'0');
if ptm6840_ctrl1(7) = '1' then
if ptm6840_q1 = '1' and ctrl_noise_and_ch1(1) = '0' then
snd1 <= signed('0'&vol(to_integer(unsigned(ctrl_vol_ch1))));
else
snd1 <= -signed('0'&vol(to_integer(unsigned(ctrl_vol_ch1))));
end if;
end if;
-- fx channel #2 enable and volume
snd2 <= (others=>'0');
if ptm6840_ctrl2(7) = '1' then
if ptm6840_q2 = '1' then
snd2 <= signed('0'&vol(to_integer(unsigned(ctrl_vol_ch2))));
else
snd2 <= -signed('0'&vol(to_integer(unsigned(ctrl_vol_ch2))));
end if;
end if;
-- fx channel #2 enable and volume
snd3 <= (others=>'0');
if ptm6840_ctrl3(7) = '1' then
if ptm6840_q3 = '1' then
snd3 <= signed('0'&vol(to_integer(unsigned(ctrl_vol_ch3))));
else
snd3 <= -signed('0'&vol(to_integer(unsigned(ctrl_vol_ch3))));
end if;
end if;
end if;
end if;
end process;
-- noise generator
noise_xor <= noise_shift_reg(127) xor noise_shift_reg(95);
noise: process(clock, reset)
begin
if reset = '1' then
noise_shift_reg <= (others => '1');
else
if rising_edge(clock) then
-- noise clock is either same as internal clock or q1 output
if (ctrl_noise_and_ch1(0) = '0' and ena_internal_clock = '1') or
(ctrl_noise_and_ch1(0) = '1' and ena_q1_clock = '1') then
noise_shift_reg <= noise_shift_reg(126 downto 0) & (noise_xor_r xor noise_xor);
noise_xor_r <= noise_xor;
end if;
end if;
end if;
end process;
end architecture;

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---------------------------------------------------------------------------------
-- Berzerk speech by Dar - July 2018
---------------------------------------------------------------------------------
-- s14001a speech synthesis based on Mame source code : TSI S14001A emulator v1.32
--
-- By Jonathan Gevaryahu ("Lord Nightmare") with help from Kevin Horton ("kevtris")
-- MAME conversion and integration by R. Belmont
-- Clock Frequency control updated by Zsolt Vasvari
-- Other fixes by AtariAce
--
-- Copyright (C) 2006-2013 Jonathan Gevaryahu aka Lord Nightmare
--
--
-- VHDL conversion by Dar
--
---------------------------------------------------------------------------------
-- S14001a principle
--
-- Command + start select a word to be played
-- One word is a list of first phoneme address called syllables
-- Each phoneme is composed of an LPC data first bloc address and a phoneme parameter
-- Phoneme parameter gives the mode (mirror/not mirror), silent, last_phoneme,
-- repeat and length of begining counters values.
--
-- Sound is LPC data encoded by bloc of 32 samples (8 bytes and 4 delta value/byte)
--
-- In non mirror mode blocs of LPC data are read consecutively from first to
-- first+N. with N = (8-repeat) * (16-length)
--
-- In mirror mode blocs of LPC data are read once forward and once backward
-- repeatedly (8-repeat) times then next bloc is read. Change to next syllable
-- after (16-length)/2 blocs have been read.
--
-- Output is set to silent (value 7) under some circumstances (third and fourth
-- quarter in mirror mode or for one sample after changing read direction).
--
-- Silence can modify output value (in the loop) or not (silence modify
-- output_sil but not output)
--
--
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity berzerk_speech is
port (
sw : in std_logic_vector(9 downto 0);
clock : in std_logic;
reset : in std_logic;
cs : in std_logic;
wr_n : in std_logic;
addr : in std_logic_vector(4 downto 0);
di : in std_logic_vector(7 downto 0);
busy : out std_logic;
sample : out std_logic_vector(11 downto 0)
);
end berzerk_speech;
architecture struct of berzerk_speech is
signal hdiv1 : std_logic_vector(3 downto 0);
signal hdiv2 : std_logic_vector(3 downto 0);
signal ena_hdiv2 : std_logic;
signal ctrl_hdiv1 : std_logic_vector(2 downto 0);
signal ctrl_volume : std_logic_vector(2 downto 0);
signal ctrl_s14001_cmd : std_logic_vector(5 downto 0);
signal busy_in : std_logic;
type vol_type is array(0 to 7) of integer range 0 to 255 ;
constant vol : vol_type := (0, 32, 46, 64, 89, 126, 180, 255); -- resistor ladder
signal rom_addr : std_logic_vector(11 downto 0);
signal rom_do : std_logic_vector( 7 downto 0);
type state_t is (waiting_start, reading, next_syllable);
signal state : state_t;
signal syllable_addr : std_logic_vector(11 downto 0);
signal phoneme_addr : std_logic_vector(11 downto 0);
signal phoneme_offset : std_logic_vector(11 downto 0);
signal phoneme_param : std_logic_vector( 7 downto 0);
alias last_phoneme : std_logic is phoneme_param(7);
alias mirror : std_logic is phoneme_param(6);
alias silence : std_logic is phoneme_param(5);
signal phoneme_length : std_logic_vector(3 downto 0);
signal phoneme_repeat : std_logic_vector(2 downto 0);
signal length_counter : std_logic_vector(4 downto 0);
signal repeat_counter : std_logic_vector(3 downto 0);
signal output_counter : std_logic_vector(2 downto 0);
signal phoneme_start : std_logic;
signal read_direction : std_logic;
signal last_offset : std_logic;
signal output : signed(4 downto 0); -- actually unsigned between 0 and F, silence = 7
signal output_sil : signed(4 downto 0); -- actually unsigned between 0 and F, silence = 7
signal start_speech : std_logic;
signal old_delta : std_logic_vector (1 downto 0);
signal cur_delta : std_logic_vector (1 downto 0);
type delta_table_row_t is array(0 to 3,0 to 3) of signed(2 downto 0);
constant delta_table : delta_table_row_t := (
("101", "101", "111", "111"),
("111", "111", "000", "000"),
("000", "000", "001", "001"),
("001", "001", "011", "011"));
begin
-- busy output
busy <= busy_in;
-- conversion from 0-F ouput and volume scale to 0-F*256, silence at 7*256.
sample <= std_logic_vector(to_unsigned(
((to_integer(output_sil) -7) * vol(to_integer(unsigned(ctrl_volume)))) + 7*256, 12));
-- clock divider
counter : process(clock, reset)
begin
if reset = '1' then
hdiv1 <= (others => '0');
hdiv2 <= (others => '0');
else
if rising_edge(clock) then
-- divide between 9 and 16 upon ctrl
if hdiv1 = "1111" then
hdiv1 <= "0"&ctrl_hdiv1;
ena_hdiv2 <= '1';
else
hdiv1 <= hdiv1 + '1';
ena_hdiv2 <= '0';
end if;
-- divide by 16 is ok because : IC A5 divide by 8 and s14001a divide by 2 internally
if ena_hdiv2 = '1' then
if hdiv2 = "1111" then
hdiv2 <= (others => '0');
else
hdiv2 <= hdiv2 + '1';
end if;
end if;
end if;
end if;
end process;
--control/registers interface with cpu addr/data
ctrl_regs : process(clock, reset)
begin
if reset = '1' then
ctrl_s14001_cmd <= (others => '0');
ctrl_hdiv1 <= (others => '0');
ctrl_volume <= (others => '0');
start_speech <= '0';
else
if rising_edge(clock) then
if busy_in = '1' then
start_speech <= '0';
end if;
if (cs = '1') and (wr_n = '0') and (addr = "00100") then -- 0x44
if (di(7 downto 6) = "00") and (busy_in = '0') and (start_speech = '0') then
ctrl_s14001_cmd <= di(5 downto 0);
start_speech <= '1';
end if;
if di(7 downto 6) = "01" then
ctrl_hdiv1 <= di(2 downto 0);
ctrl_volume <= di(5 downto 3);
end if;
end if;
end if;
end if;
end process;
-- s14001a
phoneme_length <= phoneme_param(4 downto 2)&'0';
phoneme_repeat <= phoneme_param(1 downto 0)&'0';
s14001a: process(clock, reset)
begin
if reset = '1' then
state <= waiting_start;
else
if rising_edge(clock) then
if ena_hdiv2 = '1' then
-- using hdiv2 as a sub-state counter
-- computation are done during sub-state 0-14
-- new sample is ready on sub-state 15
-- next state is set on sub-state transition from 15 to 0
case state is
when waiting_start =>
output <= "00111";
case hdiv2 is
-- wait for start, set busy when done
when X"0" =>
busy_in <= '0';
if start_speech = '1' then
busy_in <= '1';
end if;
-- compute syllable addr from word cmd
when X"1" =>
rom_addr <= "00000"&ctrl_s14001_cmd&'0';
when X"2" =>
syllable_addr(11 downto 4) <= rom_do;
rom_addr <= "00000"&ctrl_s14001_cmd&'1';
when X"3" =>
syllable_addr(3 downto 0) <= rom_do(7 downto 4);
-- init playing speech
when X"F" =>
if busy_in = '1' then
state <= reading;
phoneme_start <= '1';
phoneme_offset <= (others =>'0');
end if;
when others => null;
end case;
when reading =>
case hdiv2 is
-- get phoneme addr and parameter
when X"0" =>
rom_addr <= syllable_addr;
when X"1" =>
phoneme_addr <= rom_do&"0000";
rom_addr <= syllable_addr + '1';
when X"2" =>
phoneme_param <= rom_do;
rom_addr <= phoneme_addr + phoneme_offset(11 downto 2);
when X"3" =>
-- start with a new phoneme
if phoneme_start = '1' then
length_counter <= '0'&phoneme_length;
repeat_counter <= '0'&phoneme_repeat;
read_direction <= '1';
old_delta <= "10";
output_counter <= (others =>'0');
phoneme_start <= '0';
phoneme_offset <= (others =>'0');
output <= "00111";
end if;
-- get LPC data
case phoneme_offset(1 downto 0) is
when "00" => cur_delta <= rom_do(7 downto 6);
when "01" => cur_delta <= rom_do(5 downto 4);
when "10" => cur_delta <= rom_do(3 downto 2);
when others => cur_delta <= rom_do(1 downto 0);
end case;
-- compute new ouput from previous value and new LPC data
when X"4" =>
if read_direction = '1' then
if ((mirror = '1') and (output_counter(1) = '1')) or (silence = '1') then
output <= "00111" + delta_table(to_integer(unsigned(cur_delta)), 2);
else
output <= output + delta_table(to_integer(unsigned(cur_delta)),to_integer(unsigned(old_delta)));
end if;
else
if phoneme_offset(4 downto 0) = "11111" then
if (output_counter(1) = '1') or (silence = '1') then
output <= "00111";
else
-- keep last value
end if;
else
if (output_counter(1) = '1') or (silence = '1') then
output <= "00111" - delta_table(2, to_integer(unsigned(cur_delta)));
else
output <= output - delta_table(to_integer(unsigned(old_delta)),to_integer(unsigned(cur_delta)));
end if;
end if;
end if;
old_delta <= cur_delta;
-- increase or decrease phoneme_offset (one offset = one sample)
-- last offset when 32 samples have been read either forward or backward
last_offset <= '0';
if read_direction = '1' then
if phoneme_offset(4 downto 0) = "11111" then
last_offset <= '1';
if mirror = '0' then
phoneme_offset <= phoneme_offset + '1';
end if;
else
phoneme_offset <= phoneme_offset + '1';
end if;
else
if phoneme_offset(4 downto 0) = "00000" then
last_offset <= '1';
else
phoneme_offset <= phoneme_offset - '1';
end if;
end if;
-- increase repeat counter every 32 samples
when X"5" =>
if last_offset = '1' then
repeat_counter <= repeat_counter + '1';
output_counter <= output_counter + '1';
last_offset <= '0';
end if;
-- limit ouput to 0 - F
if output > "01111" then output <= "01111"; end if;
if output < "00000" then output <= "00000"; end if;
-- manage read_direction and phoneme advance (+8bytes = next 32 samples)
-- upon mirror condition
when X"6" =>
if mirror = '1' then
if repeat_counter = 8 then
repeat_counter <= '0'&phoneme_repeat;
if length_counter(0) = '1' then
phoneme_offset <= phoneme_offset + "100000";
end if;
if length_counter = 15 then
-- will be 16 after on next state
else
if output_counter(0) = '1' then
read_direction <= '0';
else
read_direction <= '1';
end if;
end if;
length_counter <= length_counter + 1;
else
if output_counter(0) = '1' then
read_direction <= '0';
else
read_direction <= '1';
end if;
end if;
else -- not in mirror mode
if repeat_counter = 8 then
repeat_counter <= '0'&phoneme_repeat;
if length_counter = 15 then
-- will be 16 after this state
end if;
length_counter <= length_counter + 1;
end if;
end if;
-- goto next syllable when length counter reach 16
when X"F" =>
if length_counter = 16 then
state <= next_syllable;
end if;
when others => null;
end case;
when next_syllable =>
case hdiv2 is
-- prepare for next syllable
when X"0" =>
syllable_addr <= syllable_addr + 2;
phoneme_offset <= (others =>'0');
phoneme_start <= '1';
-- one silent sample during syllable change
when X"4" =>
output <= "00111";
-- terminate if last phoneme reached
when X"F" =>
if last_phoneme = '1' then
state <= waiting_start;
else
state <= reading;
end if;
when others => null;
end case;
when others => null;
end case; -- case state
-- set silent final output during 2 last quarter when in mirror mode
if hdiv2 = X"6" then
if ((mirror = '1') and (output_counter(1) = '1')) or (silence = '1') then
output_sil <= "00111";
else
output_sil <= output;
end if;
end if;
end if;
end if;
end if;
end process;
-- program roms
speech_rom : entity work.MoonWar_speech_rom
port map (
addr => rom_addr(11 downto 0),
clk => clock,
data => rom_do
);
end architecture;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

84
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/gen_ram.vhd Normal file
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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- gen_rwram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity gen_ram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk : in std_logic;
we : in std_logic;
addr : in std_logic_vector((aWidth-1) downto 0);
d : in std_logic_vector((dWidth-1) downto 0);
q : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of gen_ram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal rAddrReg : std_logic_vector((aWidth-1) downto 0);
signal qReg : std_logic_vector((dWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
-- Signals to entity interface
-- -----------------------------------------------------------------------
-- q <= qReg;
-- -----------------------------------------------------------------------
-- Memory write
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= d;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Memory read
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
-- qReg <= ram(to_integer(unsigned(rAddrReg)));
-- rAddrReg <= addr;
---- qReg <= ram(to_integer(unsigned(addr)));
q <= ram(to_integer(unsigned(addr)));
end if;
end process;
--q <= ram(to_integer(unsigned(addr)));
end architecture;

100
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/joy2quad.sv Normal file
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//============================================================================
// joy2quad
//
// Take in digital joystick buttons, and try to estimate a quadrature encoder
//
//
// This makes an offset wave pattern for each keyboard stroke. It might
// be a good extension to change the size of the wave based on how long the joystick
// is held down.
//
// Copyright (c) 2019 Alan Steremberg - alanswx
//
//
//============================================================================
// digital joystick button to quadrature encoder
module joy2quad
(
input CLK,
input [31:0] clkdiv,
input cright,
input cleft,
output reg [4:0] steer
);
reg [3:0] state = 0;
always @(posedge CLK) begin
reg [31:0] count = 0;
if (count >0)
begin
count=count-1;
end
else
begin
count=clkdiv;
casex(state)
4'b0000:
begin
steer=5'b00000;
if (cleft==1)
begin
state=4'b0001;
end
if (cright==1)
begin
state=4'b0101;
end
end
4'b0001:
begin
steer=5'b00000;
state=4'b0010;
end
4'b0010:
begin
steer=5'b10001;
state=3'b0011;
end
4'b0011:
begin
steer=5'b11011;
state=4'b0100;
end
4'b0100:
begin
steer=5'b01010;
state=4'b000;
end
4'b0101:
begin
steer=5'b00000;
state=4'b0110;
end
4'b0110:
begin
steer=5'b01010;
state=4'b0111;
end
4'b0111:
begin
steer=5'b11011;
state=4'b1000;
end
4'b1000:
begin
steer=5'b00001;
state=4'b0000;
end
endcase
end
end
endmodule

59
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/ls161.vhd Normal file
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--============================================================================
--
-- VHDL implementation of the 74LS161 synchonous presettable 4-bit counter
-- Copyright (C) 2018, 2019 Ace
--
-- Permission is hereby granted, free of charge, to any person obtaining a
-- copy of this software and associated documentation files (the "Software"),
-- to deal in the Software without restriction, including without limitation
-- the rights to use, copy, modify, merge, publish, distribute, sublicense,
-- and/or sell copies of the Software, and to permit persons to whom the
-- Software is furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--
--============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ls161 is
port
(
n_clr : in std_logic;
clk : in std_logic;
din : in std_logic_vector(3 downto 0);
enp, ent : in std_logic;
n_load : in std_logic;
q : out std_logic_vector(3 downto 0);
rco : out std_logic
);
end ls161;
architecture arch of ls161 is
signal data : std_logic_vector(3 downto 0) := "0000";
begin
process(clk, n_clr, enp, ent, data) begin
if(n_clr = '0') then
data <= "0000";
elsif(clk'event and clk = '1') then
if(n_load = '0') then
data <= din;
elsif(enp = '1' and ent = '1') then
data <= data + '1';
end if;
end if;
end process;
q <= data;
rco <= data(0) and data(1) and data(2) and data(3) and ent;
end arch;

4
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

348
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/pll.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 10,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 27,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 20,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "27"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "20.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "20"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "20.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "20"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

1046
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/rom/MoonWar_program1.vhd Normal file
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278
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/rom/MoonWar_program2.vhd Normal file
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@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity MoonWar_program2 is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of MoonWar_program2 is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
X"2A",X"AE",X"F8",X"7C",X"B5",X"C0",X"EB",X"22",X"AE",X"F8",X"C9",X"D5",X"CD",X"7C",X"2E",X"D1",
X"07",X"07",X"EE",X"09",X"E6",X"0F",X"90",X"FA",X"1C",X"C0",X"18",X"FA",X"80",X"28",X"0C",X"47",
X"7E",X"CB",X"7F",X"20",X"03",X"23",X"18",X"F8",X"23",X"10",X"F5",X"7E",X"47",X"E6",X"7F",X"12",
X"13",X"CB",X"78",X"23",X"28",X"F5",X"C9",X"2A",X"AE",X"F8",X"7C",X"B5",X"C0",X"21",X"B1",X"F8",
X"35",X"C0",X"CD",X"7C",X"2E",X"07",X"07",X"07",X"07",X"E6",X"0F",X"C6",X"01",X"77",X"21",X"2E",
X"F9",X"CD",X"7C",X"2E",X"E6",X"07",X"F6",X"78",X"77",X"23",X"36",X"21",X"EB",X"21",X"72",X"C0",
X"06",X"0B",X"CD",X"0B",X"C0",X"EB",X"36",X"47",X"23",X"36",X"FF",X"21",X"2E",X"F9",X"22",X"AE",
X"F8",X"C9",X"01",X"02",X"0B",X"8C",X"00",X"21",X"01",X"0F",X"98",X"03",X"84",X"15",X"22",X"03",
X"84",X"05",X"A3",X"05",X"02",X"08",X"87",X"0D",X"0E",X"0F",X"90",X"01",X"02",X"86",X"05",X"02",
X"86",X"00",X"00",X"1A",X"92",X"0E",X"02",X"89",X"45",X"FF",X"7C",X"11",X"12",X"13",X"14",X"45",
X"FF",X"7C",X"01",X"02",X"06",X"45",X"FF",X"7C",X"05",X"02",X"06",X"45",X"FF",X"7C",X"03",X"02",
X"09",X"45",X"FF",X"7C",X"03",X"02",X"0A",X"45",X"FF",X"7C",X"08",X"07",X"17",X"21",X"15",X"45",
X"FF",X"7C",X"07",X"04",X"21",X"00",X"24",X"24",X"24",X"45",X"FF",X"7C",X"1A",X"1B",X"1C",X"20",
X"45",X"FF",X"7C",X"1A",X"1B",X"1D",X"20",X"45",X"FF",X"7C",X"1A",X"1B",X"1E",X"20",X"45",X"FF",
X"7C",X"1A",X"1B",X"1F",X"20",X"45",X"FF",X"7C",X"00",X"00",X"21",X"03",X"02",X"19",X"45",X"FF",
X"7C",X"15",X"22",X"0F",X"08",X"07",X"16",X"17",X"45",X"FF",X"7C",X"15",X"22",X"0F",X"06",X"16",
X"04",X"45",X"FF",X"3A",X"E1",X"43",X"B7",X"C0",X"3A",X"EC",X"43",X"B7",X"28",X"04",X"DB",X"4A",
X"18",X"02",X"DB",X"48",X"08",X"DB",X"60",X"0E",X"1F",X"CB",X"5F",X"28",X"02",X"CB",X"A1",X"CB",
X"5F",X"3E",X"0F",X"28",X"02",X"A9",X"4F",X"08",X"A9",X"47",X"E6",X"0F",X"21",X"EF",X"43",X"4E",
X"77",X"91",X"F2",X"38",X"C1",X"2F",X"C6",X"01",X"FE",X"08",X"DA",X"42",X"C1",X"F6",X"F0",X"2F",
X"C6",X"01",X"21",X"EE",X"43",X"4F",X"CB",X"29",X"81",X"CB",X"60",X"20",X"04",X"86",X"77",X"18",
X"04",X"47",X"7E",X"90",X"77",X"C9",X"7B",X"BD",X"38",X"01",X"EB",X"42",X"4B",X"E5",X"2E",X"00",
X"60",X"E3",X"FD",X"E1",X"E5",X"2E",X"00",X"61",X"E3",X"7C",X"90",X"16",X"00",X"30",X"01",X"15",
X"5F",X"7D",X"91",X"06",X"00",X"30",X"01",X"05",X"4F",X"E1",X"7B",X"B1",X"3E",X"01",X"28",X"21",
X"3E",X"FF",X"08",X"7B",X"AA",X"17",X"38",X"0F",X"79",X"A8",X"17",X"38",X"0A",X"CB",X"23",X"CB",
X"21",X"08",X"CB",X"3F",X"C3",X"82",X"C1",X"08",X"3C",X"C5",X"01",X"80",X"00",X"09",X"FD",X"09",
X"C1",X"08",X"7C",X"FD",X"E5",X"D9",X"E1",X"6F",X"06",X"10",X"CD",X"68",X"2F",X"36",X"80",X"D9",
X"08",X"09",X"FD",X"19",X"3D",X"C2",X"A1",X"C1",X"C9",X"EC",X"2A",X"AE",X"F8",X"7C",X"B5",X"C0",
X"EB",X"22",X"AE",X"F8",X"C9",X"01",X"D8",X"01",X"F8",X"DE",X"F8",X"DE",X"D8",X"01",X"D8",X"FE",
X"02",X"DB",X"44",X"DB",X"FE",X"02",X"DC",X"44",X"DC",X"FE",X"02",X"DD",X"44",X"DD",X"FE",X"02",
X"DE",X"44",X"DE",X"FE",X"02",X"DF",X"44",X"DF",X"FE",X"02",X"E0",X"44",X"E0",X"FE",X"02",X"E3",
X"44",X"E3",X"FE",X"02",X"E4",X"44",X"E4",X"FE",X"02",X"E5",X"44",X"E5",X"FE",X"02",X"E6",X"44",
X"E6",X"FE",X"02",X"E7",X"44",X"E7",X"FE",X"02",X"E8",X"44",X"E8",X"FE",X"03",X"F8",X"03",X"EE",
X"44",X"EE",X"44",X"F8",X"FF",X"01",X"23",X"1C",X"12",X"1E",X"10",X"10",X"10",X"00",X"0C",X"12",
X"12",X"12",X"12",X"0C",X"00",X"11",X"11",X"11",X"15",X"15",X"0E",X"00",X"1E",X"10",X"18",X"10",
X"10",X"1E",X"00",X"1C",X"12",X"1E",X"18",X"14",X"12",X"00",X"01",X"23",X"0E",X"09",X"0E",X"0E",
X"09",X"0E",X"00",X"06",X"09",X"09",X"09",X"09",X"06",X"00",X"09",X"0D",X"0D",X"0B",X"0B",X"09",
X"00",X"09",X"09",X"09",X"09",X"09",X"06",X"00",X"07",X"08",X"06",X"01",X"01",X"0E",X"00",X"01",
X"23",X"06",X"09",X"0F",X"09",X"09",X"09",X"00",X"09",X"0D",X"0D",X"0B",X"0B",X"09",X"00",X"07",
X"08",X"08",X"0B",X"09",X"06",X"00",X"08",X"08",X"08",X"08",X"08",X"0F",X"00",X"0F",X"08",X"0C",
X"08",X"08",X"0F",X"00",X"02",X"05",X"08",X"BA",X"0D",X"93",X"0A",X"92",X"08",X"92",X"08",X"BA",
X"02",X"05",X"5C",X"60",X"50",X"80",X"DC",X"40",X"50",X"20",X"5C",X"C0",X"02",X"04",X"0F",X"1E",
X"0F",X"1E",X"0F",X"1E",X"0F",X"1E",X"02",X"04",X"3C",X"78",X"3C",X"78",X"3C",X"78",X"3C",X"78",
X"02",X"05",X"0E",X"7A",X"09",X"4A",X"0E",X"4A",X"09",X"4A",X"0E",X"7B",X"02",X"05",X"3E",X"60",
X"08",X"80",X"08",X"40",X"08",X"20",X"C8",X"C0",X"02",X"05",X"07",X"0C",X"04",X"92",X"07",X"1E",
X"05",X"12",X"04",X"92",X"02",X"05",X"32",X"40",X"42",X"80",X"43",X"00",X"42",X"80",X"32",X"40",
X"02",X"05",X"04",X"1E",X"04",X"10",X"04",X"18",X"04",X"10",X"07",X"9E",X"02",X"05",X"79",X"C0",
X"40",X"80",X"60",X"80",X"40",X"80",X"40",X"80",X"02",X"05",X"1C",X"E6",X"21",X"09",X"19",X"09",
X"05",X"09",X"38",X"E6",X"02",X"05",X"73",X"9C",X"4A",X"20",X"73",X"18",X"52",X"04",X"4B",X"B8",
X"01",X"3B",X"00",X"16",X"F0",X"3E",X"AA",X"E6",X"0F",X"5F",X"3E",X"08",X"CD",X"B9",X"CC",X"01",
X"3B",X"01",X"16",X"F0",X"3E",X"BB",X"E6",X"0F",X"5F",X"3E",X"06",X"CD",X"B9",X"CC",X"01",X"FB",
X"01",X"16",X"F0",X"3E",X"99",X"E6",X"0F",X"5F",X"3E",X"02",X"CD",X"B9",X"CC",X"01",X"3C",X"00",
X"16",X"F0",X"3E",X"AA",X"E6",X"0F",X"5F",X"3E",X"0C",X"CD",X"B9",X"CC",X"01",X"BC",X"01",X"16",
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X"3E",X"99",X"E6",X"0F",X"5F",X"3E",X"01",X"CD",X"B9",X"CC",X"01",X"3E",X"00",X"16",X"F0",X"3E",
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X"48",X"11",X"15",X"C2",X"CD",X"E0",X"C6",X"01",X"5B",X"02",X"16",X"F0",X"3E",X"22",X"E6",X"0F",
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

278
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/rom/MoonWar_speech_rom.vhd Normal file
View File

@@ -0,0 +1,278 @@
library ieee;
use ieee.std_logic_1164.all,ieee.numeric_std.all;
entity MoonWar_speech_rom is
port (
clk : in std_logic;
addr : in std_logic_vector(11 downto 0);
data : out std_logic_vector(7 downto 0)
);
end entity;
architecture prom of MoonWar_speech_rom is
type rom is array(0 to 4095) of std_logic_vector(7 downto 0);
signal rom_data: rom := (
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begin
process(clk)
begin
if rising_edge(clk) then
data <= rom_data(to_integer(unsigned(addr)));
end if;
end process;
end architecture;

134
Arcade_MiST/Berzerk Hardware/MoonWar_MiST/rtl/video_gen.vhd Normal file
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---------------------------------------------------------------------------------
-- Berzerk Video generator - Dar - Juin 2018
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity video_gen is
port(
clock : in std_logic;
reset : in std_logic;
ena_pixel : in std_logic;
hsync : out std_logic;
vsync : out std_logic;
csync : out std_logic;
hblank : out std_logic;
vblank : out std_logic;
hcnt_o : out std_logic_vector(8 downto 0);
vcnt_o : out std_logic_vector(8 downto 0)
);
end video_gen;
architecture struct of video_gen is
signal hcnt : std_logic_vector(8 downto 0);
signal vcnt : std_logic_vector(8 downto 0);
signal hsync0 : std_logic;
signal hsync1 : std_logic;
signal hsync2 : std_logic;
begin
hcnt_o <= hcnt;
vcnt_o <= vcnt;
hsync <= hsync0;
-- Compteur horizontal
-- 1C0..1FF-000..0FF : 64+256 = 320 pixels
-- 448..511-000..255
-- Compteur vertical
-- 1DA..1FF-020..0FF : 38+224 = 262 lignes
-- 474..511-032..255
-- Synchro horizontale : hcnt=[] (xx pixels)
-- Synchro verticale : vcnt=[] ( x lignes)
process(clock,reset)
begin
if reset = '1' then
hcnt <= (others=>'0');
vcnt <= (others=>'0');
else
if rising_edge(clock) then
if ena_pixel = '1' then
if hcnt = std_logic_vector(to_unsigned(511,9)) then -- 511
hcnt <= (others=>'0');
else
if hcnt = std_logic_vector(to_unsigned(255,9)) then -- 255
hcnt <= std_logic_vector(to_unsigned(448,9)); -- 448
else
hcnt <= hcnt + '1';
end if;
end if;
if hcnt = std_logic_vector(to_unsigned(255,9)) then
if vcnt = std_logic_vector(to_unsigned(511,9)) then
vcnt <= std_logic_vector(to_unsigned(32,9));
else
if vcnt = 255 then
vcnt <= std_logic_vector(to_unsigned(474,9));
else
vcnt <= vcnt + '1';
end if;
end if;
end if;
if hcnt = std_logic_vector(to_unsigned(448+16,9)) then
-- vblank_r <= vblank;
end if;
if hcnt = (466+ 0) then hsync0 <= '0';
elsif hcnt = (466+24) then hsync0 <= '1';
end if;
if hcnt = (466+ 0) then hsync1 <= '0';
elsif hcnt = (466+11) then hsync1 <= '1';
elsif hcnt = (466 +160-512) then hsync1 <= '0';
elsif hcnt = (466+11+160-512) then hsync1 <= '1';
end if;
if hcnt = (466) then hsync2 <= '0';
elsif hcnt = (466-10) then hsync2 <= '1';
end if;
if vcnt = (490-7) then csync <= hsync1;
elsif vcnt = (491-7) then csync <= hsync1;
elsif vcnt = (492-7) then csync <= hsync1;
elsif vcnt = (493-7) then csync <= hsync2;
elsif vcnt = (494-7) then csync <= hsync2;
elsif vcnt = (495-7) then csync <= hsync2;
elsif vcnt = (496-7) then csync <= hsync1;
elsif vcnt = (497-7) then csync <= hsync1;
elsif vcnt = (498-7) then csync <= hsync1;
else csync <= hsync0;
end if;
if vcnt = (490) then vsync <= '0';
elsif vcnt = (498) then vsync <= '1';
end if;
if hcnt = (448+8) then hblank <= '1';
elsif hcnt = (8) then hblank <= '0';
end if;
if vcnt = (474) then vblank <= '1';
elsif vcnt = (032) then vblank <= '0';
end if;
end if;
end if;
end if;
end process;
end architecture;

30
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/GunFight.qpf Normal file
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@@ -0,0 +1,30 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 21:27:39 November 20, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.1"
DATE = "21:27:39 November 20, 2017"
# Revisions
PROJECT_REVISION = "GunFight"

178
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/GunFight.qsf Normal file
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@@ -0,0 +1,178 @@
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 22:12:52 July 17, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# GunFight_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:27:39 NOVEMBER 20, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_mist.sv
set_global_assignment -name VHDL_FILE rtl/invaders.vhd
set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/GunFight_memory.sv
set_global_assignment -name VHDL_FILE rtl/GunFight_overlay.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Reg.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_Pack.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_MCode.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80_ALU.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T80.vhd
set_global_assignment -name VHDL_FILE rtl/pll.vhd
set_global_assignment -name QIP_FILE ../../../../common/mist/mist.qip
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY GunFight_mist
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# start EDA_TOOL_SETTINGS(eda_simulation)
# ---------------------------------------
# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------
# ---------------------------
# start ENTITY(GunFight_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(GunFight_mist)
# -------------------------
# --------------------------------
# start ENTITY(spaceinvaders_mist)
# end ENTITY(spaceinvaders_mist)
# ------------------------------
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

126
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/GunFight.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] 1.000 [get_ports {VGA_*}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

29
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/README.txt Normal file
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---------------------------------------------------------------------------------
--
-- Arcade: Gun Fight port to MiST by Gehstock
-- 17 July 2019
--
---------------------------------------------------------------------------------
--
-- Midway 8080 Hardware
-- Audio based on work by Paul Walsh.
-- Audio and scan converter by MikeJ.
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- ESC : Start
-- Joystick 1 / 2 : Movement
-- Q : Player 1 Gun Up
-- Y : Player 1 Gun Down
-- Arrow Up : Player 2 Gun Up
-- ArrowDown : Player 2 Gun Down
-- Joystick only
--
--
---------------------------------------------------------------------------------
ToDo: Sound
Controls

BIN
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/Release/GunFight.rbf Normal file
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Binary file not shown.

15
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/clean.bat Normal file
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@echo off
del /s *.bak
del /s *.orig
del /s *.rej
rmdir /s /q db
rmdir /s /q incremental_db
rmdir /s /q output_files
rmdir /s /q simulation
rmdir /s /q greybox_tmp
del PLLJ_PLLSPE_INFO.txt
del *.qws
del *.ppf
del *.qip
del *.ddb
pause

129
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/GunFight_memory.sv Normal file
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module GunFight_memory(
input Clock,
input RW_n,
input [15:0]Addr,
input [15:0]Ram_Addr,
output [7:0]Ram_out,
input [7:0]Ram_in,
output [7:0]Rom_out
);
wire [7:0]rom_data_0;
wire [7:0]rom_data_1;
wire [7:0]rom_data_2;
wire [7:0]rom_data_3;
wire [7:0]rom_data_4;
wire [7:0]rom_data_5;
wire [7:0]rom_data_6;
wire [7:0]rom_data_7;
sprom #(
.init_file("./roms/gf-h.hex"),
.widthad_a(9),
.width_a(8))
u_rom_h (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_0)
);
sprom #(
.init_file("./roms/gf-g.hex"),
.widthad_a(9),
.width_a(8))
u_rom_g (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_1)
);
sprom #(
.init_file("./roms/gf-f.hex"),
.widthad_a(9),
.width_a(8))
u_rom_f (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_2)
);
sprom #(
.init_file("./roms/gf-e.hex"),
.widthad_a(9),
.width_a(8))
u_rom_e (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_3)
);
sprom #(
.init_file("./roms/gf-d.hex"),
.widthad_a(9),
.width_a(8))
u_rom_d (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_4)
);
sprom #(
.init_file("./roms/gf-c.hex"),
.widthad_a(9),
.width_a(8))
u_rom_c (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_5)
);
sprom #(
.init_file("./roms/gf-b.hex"),
.widthad_a(9),
.width_a(8))
u_rom_b (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_6)
);
sprom #(
.init_file("./roms/gf-a.hex"),
.widthad_a(9),
.width_a(8))
u_rom_a (
.clock(Clock),
.Address(Addr[8:0]),
.q(rom_data_7)
);
always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_data_5, rom_data_6, rom_data_7) begin
Rom_out = 8'b00000000;
case (Addr[12:9])
4'b0000 : Rom_out = rom_data_0;
4'b0001 : Rom_out = rom_data_1;
4'b0010 : Rom_out = rom_data_2;
4'b0011 : Rom_out = rom_data_3;
4'b0100 : Rom_out = rom_data_4;
4'b0101 : Rom_out = rom_data_5;
4'b0110 : Rom_out = rom_data_6;
4'b0111 : Rom_out = rom_data_7;
default : Rom_out = 8'b00000000;
endcase
end
spram #(
.addr_width_g(13),
.data_width_g(8))
u_ram0(
.address(Ram_Addr[12:0]),
.clken(1'b1),
.clock(Clock),
.data(Ram_in),
.wren(~RW_n),
.q(Ram_out)
);
endmodule

197
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/GunFight_mist.sv Normal file
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module GunFight_mist(
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27
);
`include "rtl\build_id.v"
localparam CONF_STR = {
"Gun Fight;;",
"O34,Scanlines,Off,25%,50%,75%;",
// "O5,Overlay, On, Off;",
"T6,Reset;",
"V,v1.20.",`BUILD_DATE
};
assign LED = 1;
assign AUDIO_R = AUDIO_L;
wire clk_sys;
wire pll_locked;
pll pll
(
.inclk0(CLOCK_27),
.areset(),
.c0(clk_sys)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] kbjoy;
wire [7:0] joystick_0,joystick_1;
wire scandoublerD;
wire ypbpr;
wire key_pressed;
wire [7:0] key_code;
wire key_strobe;
wire [7:0] audio;
wire hsync,vsync;
wire hs, vs;
wire r,g,b;
wire [15:0]RAB;
wire [15:0]AD;
wire [7:0]RDB;
wire [7:0]RWD;
wire [7:0]IB;
wire [5:0]SoundCtrl3;
wire [5:0]SoundCtrl5;
wire Rst_n_s;
wire RWE_n;
wire Video;
wire HSync;
wire VSync;
invaderst invaderst(
.Rst_n(~(status[0] | status[6] | buttons[1])),
.Clk(clk_sys),
.ENA(),
.Coin(btn_coin),
.Sel1Player(btn_one_player),
.Fire1(~joystick_0[4]),
.Fire2(~joystick_1[4]),
.GunUp1(gun1_up),
.GunDown1(gun1_dw),
.MoveLeft1(~joystick_0[1]),
.MoveRight1(~joystick_0[0]),
.MoveUp1(~joystick_0[3]),
.MoveDown1(~joystick_0[2]),
.GunUp2(gun2_up),
.GunDown2(gun2_dw),
.MoveLeft2(~joystick_1[1]),
.MoveRight2(~joystick_1[0]),
.MoveUp2(~joystick_1[3]),
.MoveDown2(~joystick_1[2]),
// .DIP(dip),
.RDB(RDB),
.IB(IB),
.RWD(RWD),
.RAB(RAB),
.AD(AD),
.SoundCtrl3(SoundCtrl3),
.SoundCtrl5(SoundCtrl5),
.Rst_n_s(Rst_n_s),
.RWE_n(RWE_n),
.Video(Video),
.HSync(hs),
.VSync(vs)
);
GunFight_memory GunFight_memory (
.Clock(clk_sys),
.RW_n(RWE_n),
.Addr(AD),
.Ram_Addr(RAB),
.Ram_out(RDB),
.Ram_in(RWD),
.Rom_out(IB)
);
invaders_audio invaders_audio (
.Clk(clk_sys),
.S1(SoundCtrl3),
.S2(SoundCtrl5),
.Aud(audio)
);
mist_video #(.COLOR_DEPTH(3)) mist_video(
.clk_sys(clk_sys),
.SPI_SCK(SPI_SCK),
.SPI_SS3(SPI_SS3),
.SPI_DI(SPI_DI),
.R({Video,Video,Video}),
.G({Video,Video,Video}),
.B(3'b000),
.HSync(hs),
.VSync(vs),
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_VS(VGA_VS),
.VGA_HS(VGA_HS),
.scandoubler_disable(scandoublerD),
.ce_divider(1),
.scanlines(status[4:3]),
.ypbpr(ypbpr)
);
user_io #(
.STRLEN(($size(CONF_STR)>>3)))
user_io(
.clk_sys (clk_sys ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(
.c_bits(7))
dac (
.clk_i(clk_sys),
.res_n_i(1),
.dac_i(audio),
.dac_o(AUDIO_L)
);
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_coin = 0;
reg gun1_up = 0;
reg gun1_dw = 0;
reg gun2_up = 0;
reg gun2_dw = 0;
always @(posedge clk_sys) begin
if(key_strobe) begin
case(key_code)
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
'h15: gun1_up <= key_pressed; // Q
'h35: gun1_dw <= key_pressed; // Y
'h75: gun2_up <= key_pressed; // Arrow up
'h72: gun2_dw <= key_pressed; // Arrow down
endcase
end
end
endmodule

127
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/GunFight_overlay.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity GunFight_overlay is
port(
Video : in std_logic;
Overlay : in std_logic;
CLK : in std_logic;
Rst_n_s : in std_logic;
HSync : in std_logic;
VSync : in std_logic;
O_VIDEO_R : out std_logic;
O_VIDEO_G : out std_logic;
O_VIDEO_B : out std_logic;
O_HSYNC : out std_logic;
O_VSYNC : out std_logic
);
end GunFight_overlay;
architecture rtl of GunFight_overlay is
signal HCnt : std_logic_vector(11 downto 0);
signal VCnt : std_logic_vector(11 downto 0);
signal HSync_t1 : std_logic;
signal Overlay_G1 : boolean;
signal Overlay_G2 : boolean;
signal Overlay_R1 : boolean;
signal Overlay_G1_VCnt : boolean;
signal VideoRGB : std_logic_vector(2 downto 0);
begin
process (Rst_n_s, Clk)
variable cnt : unsigned(3 downto 0);
begin
if Rst_n_s = '0' then
cnt := "0000";
elsif Clk'event and Clk = '1' then
if cnt = 9 then
cnt := "0000";
else
cnt := cnt + 1;
end if;
end if;
end process;
p_overlay : process(Rst_n_s, Clk)
variable HStart : boolean;
begin
if Rst_n_s = '0' then
HCnt <= (others => '0');
VCnt <= (others => '0');
HSync_t1 <= '0';
Overlay_G1_VCnt <= false;
Overlay_G1 <= false;
Overlay_G2 <= false;
Overlay_R1 <= false;
elsif Clk'event and Clk = '1' then
HSync_t1 <= HSync;
HStart := (HSync_t1 = '0') and (HSync = '1');
if HStart then
HCnt <= (others => '0');
else
HCnt <= HCnt + "1";
end if;
if (VSync = '0') then
VCnt <= (others => '0');
elsif HStart then
VCnt <= VCnt + "1";
end if;
if HStart then
if (Vcnt = x"1F") then
Overlay_G1_VCnt <= true;
elsif (Vcnt = x"95") then
Overlay_G1_VCnt <= false;
end if;
end if;
if (HCnt = x"027") and Overlay_G1_VCnt then
Overlay_G1 <= true;
elsif (HCnt = x"046") then
Overlay_G1 <= false;
end if;
if (HCnt = x"046") then
Overlay_G2 <= true;
elsif (HCnt = x"0B6") then
Overlay_G2 <= false;
end if;
if (HCnt = x"1A6") then
Overlay_R1 <= true;
elsif (HCnt = x"1E6") then
Overlay_R1 <= false;
end if;
end if;
end process;
p_video_out_comb : process(Video, Overlay_G1, Overlay_G2, Overlay_R1)
begin
if (Video = '0') then
VideoRGB <= "000";
else
if Overlay_G1 or Overlay_G2 then
VideoRGB <= "010";
elsif Overlay_R1 then
VideoRGB <= "100";
else
VideoRGB <= "111";
end if;
end if;
end process;
O_VIDEO_R <= VideoRGB(2) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_G <= VideoRGB(1) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_VIDEO_B <= VideoRGB(0) when (Overlay = '1') else VideoRGB(0) or VideoRGB(1) or VideoRGB(2);
O_HSYNC <= HSync;
O_VSYNC <= VSync;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- 8080 compatible microprocessor core, synchronous top level with clock enable
-- Different timing than the original 8080
-- Inputs needs to be synchronous and outputs may glitch
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
-- STACK status output not supported
--
-- File history :
--
-- 0237 : First version
--
-- 0238 : Updated for T80 interface change
--
-- 0240 : Updated for T80 interface change
--
-- 0242 : Updated for T80 interface change
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T8080se is
generic(
Mode : integer := 2; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
T2Write : integer := 0 -- 0 => WR_n active in T3, /=0 => WR_n active in T2
);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T8080se;
architecture rtl of T8080se is
signal IntCycle_n : std_logic;
signal NoRead : std_logic;
signal Write : std_logic;
signal IORQ : std_logic;
signal INT_n : std_logic;
signal HALT_n : std_logic;
signal BUSRQ_n : std_logic;
signal BUSAK_n : std_logic;
signal DO_i : std_logic_vector(7 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal TState : std_logic_vector(2 downto 0);
signal One : std_logic;
begin
INT_n <= not INT;
BUSRQ_n <= HOLD;
HLDA <= not BUSAK_n;
SYNC <= '1' when TState = "001" else '0';
VAIT <= '1' when TState = "010" else '0';
One <= '1';
DO(0) <= not IntCycle_n when TState = "001" else DO_i(0); -- INTA
DO(1) <= Write when TState = "001" else DO_i(1); -- WO_n
DO(2) <= DO_i(2); -- STACK not supported !!!!!!!!!!
DO(3) <= not HALT_n when TState = "001" else DO_i(3); -- HLTA
DO(4) <= IORQ and Write when TState = "001" else DO_i(4); -- OUT
DO(5) <= DO_i(5) when TState /= "001" else '1' when MCycle = "001" else '0'; -- M1
DO(6) <= IORQ and not Write when TState = "001" else DO_i(6); -- INP
DO(7) <= not IORQ and not Write and IntCycle_n when TState = "001" else DO_i(7); -- MEMR
u0 : T80
generic map(
Mode => Mode,
IOWait => 0)
port map(
CEN => CLKEN,
M1_n => open,
IORQ => IORQ,
NoRead => NoRead,
Write => Write,
RFSH_n => open,
HALT_n => HALT_n,
WAIT_n => READY,
INT_n => INT_n,
NMI_n => One,
RESET_n => RESET_n,
BUSRQ_n => One,
BUSAK_n => BUSAK_n,
CLK_n => CLK,
A => A,
DInst => DI,
DI => DI_Reg,
DO => DO_i,
MC => MCycle,
TS => TState,
IntCycle_n => IntCycle_n,
IntE => INTE);
process (RESET_n, CLK)
begin
if RESET_n = '0' then
DBIN <= '0';
WR_n <= '1';
DI_Reg <= "00000000";
elsif CLK'event and CLK = '1' then
if CLKEN = '1' then
DBIN <= '0';
WR_n <= '1';
if MCycle = "001" then
if TState = "001" or (TState = "010" and READY = '0') then
DBIN <= IntCycle_n;
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and NoRead = '0' and Write = '0' then
DBIN <= '1';
end if;
if T2Write = 0 then
if TState = "010" and Write = '1' then
WR_n <= '0';
end if;
else
if (TState = "001" or (TState = "010" and READY = '0')) and Write = '1' then
WR_n <= '0';
end if;
end if;
end if;
if TState = "010" and READY = '1' then
DI_Reg <= DI;
end if;
end if;
end if;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0238 : Fixed zero flag for 16 bit SBC and ADC
--
-- 0240 : Added GB operations
--
-- 0242 : Cleanup
--
-- 0247 : Cleanup
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_ALU is
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end T80_ALU;
architecture rtl of T80_ALU is
procedure AddSub(A : std_logic_vector;
B : std_logic_vector;
Sub : std_logic;
Carry_In : std_logic;
signal Res : out std_logic_vector;
signal Carry : out std_logic) is
variable B_i : unsigned(A'length - 1 downto 0);
variable Res_i : unsigned(A'length + 1 downto 0);
begin
if Sub = '1' then
B_i := not unsigned(B);
else
B_i := unsigned(B);
end if;
Res_i := unsigned("0" & A & Carry_In) + unsigned("0" & B_i & "1");
Carry <= Res_i(A'length + 1);
Res <= std_logic_vector(Res_i(A'length downto 1));
end;
-- AddSub variables (temporary signals)
signal UseCarry : std_logic;
signal Carry7_v : std_logic;
signal Overflow_v : std_logic;
signal HalfCarry_v : std_logic;
signal Carry_v : std_logic;
signal Q_v : std_logic_vector(7 downto 0);
signal BitMask : std_logic_vector(7 downto 0);
begin
with IR(5 downto 3) select BitMask <= "00000001" when "000",
"00000010" when "001",
"00000100" when "010",
"00001000" when "011",
"00010000" when "100",
"00100000" when "101",
"01000000" when "110",
"10000000" when others;
UseCarry <= not ALU_Op(2) and ALU_Op(0);
AddSub(BusA(3 downto 0), BusB(3 downto 0), ALU_Op(1), ALU_Op(1) xor (UseCarry and F_In(Flag_C)), Q_v(3 downto 0), HalfCarry_v);
AddSub(BusA(6 downto 4), BusB(6 downto 4), ALU_Op(1), HalfCarry_v, Q_v(6 downto 4), Carry7_v);
AddSub(BusA(7 downto 7), BusB(7 downto 7), ALU_Op(1), Carry7_v, Q_v(7 downto 7), Carry_v);
OverFlow_v <= Carry_v xor Carry7_v;
process (Arith16, ALU_OP, F_In, BusA, BusB, IR, Q_v, Carry_v, HalfCarry_v, OverFlow_v, BitMask, ISet, Z16)
variable Q_t : std_logic_vector(7 downto 0);
variable DAA_Q : unsigned(8 downto 0);
begin
Q_t := "--------";
F_Out <= F_In;
DAA_Q := "---------";
case ALU_Op is
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" | "0110" | "0111" =>
F_Out(Flag_N) <= '0';
F_Out(Flag_C) <= '0';
case ALU_OP(2 downto 0) is
when "000" | "001" => -- ADD, ADC
Q_t := Q_v;
F_Out(Flag_C) <= Carry_v;
F_Out(Flag_H) <= HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "010" | "011" | "111" => -- SUB, SBC, CP
Q_t := Q_v;
F_Out(Flag_N) <= '1';
F_Out(Flag_C) <= not Carry_v;
F_Out(Flag_H) <= not HalfCarry_v;
F_Out(Flag_P) <= OverFlow_v;
when "100" => -- AND
Q_t(7 downto 0) := BusA and BusB;
F_Out(Flag_H) <= '1';
when "101" => -- XOR
Q_t(7 downto 0) := BusA xor BusB;
F_Out(Flag_H) <= '0';
when others => -- OR "110"
Q_t(7 downto 0) := BusA or BusB;
F_Out(Flag_H) <= '0';
end case;
if ALU_Op(2 downto 0) = "111" then -- CP
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
else
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
end if;
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
if Z16 = '1' then
F_Out(Flag_Z) <= F_In(Flag_Z); -- 16 bit ADC,SBC
end if;
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
case ALU_Op(2 downto 0) is
when "000" | "001" | "010" | "011" | "111" => -- ADD, ADC, SUB, SBC, CP
when others =>
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
end case;
if Arith16 = '1' then
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
F_Out(Flag_P) <= F_In(Flag_P);
end if;
when "1100" =>
-- DAA
F_Out(Flag_H) <= F_In(Flag_H);
F_Out(Flag_C) <= F_In(Flag_C);
DAA_Q(7 downto 0) := unsigned(BusA);
DAA_Q(8) := '0';
if F_In(Flag_N) = '0' then
-- After addition
-- Alow > 9 or H = 1
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if (DAA_Q(3 downto 0) > 9) then
F_Out(Flag_H) <= '1';
else
F_Out(Flag_H) <= '0';
end if;
DAA_Q := DAA_Q + 6;
end if;
-- new Ahigh > 9 or C = 1
if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q + 96; -- 0x60
end if;
else
-- After subtraction
if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
if DAA_Q(3 downto 0) > 5 then
F_Out(Flag_H) <= '0';
end if;
DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
end if;
if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
DAA_Q := DAA_Q - 352; -- 0x160
end if;
end if;
F_Out(Flag_X) <= DAA_Q(3);
F_Out(Flag_Y) <= DAA_Q(5);
F_Out(Flag_C) <= F_In(Flag_C) or DAA_Q(8);
Q_t := std_logic_vector(DAA_Q(7 downto 0));
if DAA_Q(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= DAA_Q(7);
F_Out(Flag_P) <= not (DAA_Q(0) xor DAA_Q(1) xor DAA_Q(2) xor DAA_Q(3) xor
DAA_Q(4) xor DAA_Q(5) xor DAA_Q(6) xor DAA_Q(7));
when "1101" | "1110" =>
-- RLD, RRD
Q_t(7 downto 4) := BusA(7 downto 4);
if ALU_Op(0) = '1' then
Q_t(3 downto 0) := BusB(7 downto 4);
else
Q_t(3 downto 0) := BusB(3 downto 0);
end if;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_S) <= Q_t(7);
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
when "1001" =>
-- BIT
Q_t(7 downto 0) := BusB and BitMask;
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
F_Out(Flag_P) <= '1';
else
F_Out(Flag_Z) <= '0';
F_Out(Flag_P) <= '0';
end if;
F_Out(Flag_H) <= '1';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= '0';
F_Out(Flag_Y) <= '0';
if IR(2 downto 0) /= "110" then
F_Out(Flag_X) <= BusB(3);
F_Out(Flag_Y) <= BusB(5);
end if;
when "1010" =>
-- SET
Q_t(7 downto 0) := BusB or BitMask;
when "1011" =>
-- RES
Q_t(7 downto 0) := BusB and not BitMask;
when "1000" =>
-- ROT
case IR(5 downto 3) is
when "000" => -- RLC
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := BusA(7);
F_Out(Flag_C) <= BusA(7);
when "010" => -- RL
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(7);
when "001" => -- RRC
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(0);
F_Out(Flag_C) <= BusA(0);
when "011" => -- RR
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := F_In(Flag_C);
F_Out(Flag_C) <= BusA(0);
when "100" => -- SLA
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '0';
F_Out(Flag_C) <= BusA(7);
when "110" => -- SLL (Undocumented) / SWAP
if Mode = 3 then
Q_t(7 downto 4) := BusA(3 downto 0);
Q_t(3 downto 0) := BusA(7 downto 4);
F_Out(Flag_C) <= '0';
else
Q_t(7 downto 1) := BusA(6 downto 0);
Q_t(0) := '1';
F_Out(Flag_C) <= BusA(7);
end if;
when "101" => -- SRA
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := BusA(7);
F_Out(Flag_C) <= BusA(0);
when others => -- SRL
Q_t(6 downto 0) := BusA(7 downto 1);
Q_t(7) := '0';
F_Out(Flag_C) <= BusA(0);
end case;
F_Out(Flag_H) <= '0';
F_Out(Flag_N) <= '0';
F_Out(Flag_X) <= Q_t(3);
F_Out(Flag_Y) <= Q_t(5);
F_Out(Flag_S) <= Q_t(7);
if Q_t(7 downto 0) = "00000000" then
F_Out(Flag_Z) <= '1';
else
F_Out(Flag_Z) <= '0';
end if;
F_Out(Flag_P) <= not (Q_t(0) xor Q_t(1) xor Q_t(2) xor Q_t(3) xor
Q_t(4) xor Q_t(5) xor Q_t(6) xor Q_t(7));
if ISet = "00" then
F_Out(Flag_P) <= F_In(Flag_P);
F_Out(Flag_S) <= F_In(Flag_S);
F_Out(Flag_Z) <= F_In(Flag_Z);
end if;
when others =>
null;
end case;
Q <= Q_t;
end process;
end;

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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;

114
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-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- T80 Registers, technology independent
--
-- Version : 0244
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t51/
--
-- Limitations :
--
-- File history :
--
-- 0242 : Initial release
--
-- 0244 : Changed to single register file
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity T80_Reg is
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0)
);
end T80_Reg;
architecture rtl of T80_Reg is
type Register_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal RegsH : Register_Image(0 to 7);
signal RegsL : Register_Image(0 to 7);
begin
process (Clk)
begin
if Clk'event and Clk = '1' then
if CEN = '1' then
if WEH = '1' then
RegsH(to_integer(unsigned(AddrA))) <= DIH;
end if;
if WEL = '1' then
RegsL(to_integer(unsigned(AddrA))) <= DIL;
end if;
end if;
end if;
end process;
DOAH <= RegsH(to_integer(unsigned(AddrA)));
DOAL <= RegsL(to_integer(unsigned(AddrA)));
DOBH <= RegsH(to_integer(unsigned(AddrB)));
DOBL <= RegsL(to_integer(unsigned(AddrB)));
DOCH <= RegsH(to_integer(unsigned(AddrC)));
DOCL <= RegsL(to_integer(unsigned(AddrC)));
end;

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

48
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-------------------------------------------------------------------------------
--
-- Delta-Sigma DAC
--
-- Refer to Xilinx Application Note XAPP154.
--
-- This DAC requires an external RC low-pass filter:
--
-- dac_o 0---XXXXX---+---0 analog audio
-- 3k3 |
-- === 4n7
-- |
-- GND
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dac is
generic (
C_bits : integer := 8
);
port (
clk_i : in std_logic;
res_n_i : in std_logic;
dac_i : in std_logic_vector(C_bits-1 downto 0);
dac_o : out std_logic
);
end dac;
architecture rtl of dac is
signal sig_in: unsigned(C_bits downto 0);
begin
seq: process(clk_i, res_n_i)
begin
if res_n_i = '0' then
sig_in <= to_unsigned(2**C_bits, sig_in'length);
dac_o <= '0';
elsif rising_edge(clk_i) then
-- not dac_i(C_bits-1) effectively adds 0x8..0 to dac_i
--sig_in <= sig_in + unsigned(sig_in(C_bits) & (not dac_i(C_bits-1)) & dac_i(C_bits-2 downto 0));
sig_in <= sig_in + unsigned(sig_in(C_bits) & dac_i);
dac_o <= sig_in(C_bits);
end if;
end process seq;
end rtl;

287
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-- Space Invaders core logic
-- 9.984MHz clock
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.fpgaarcade.com
--
-- Limitations :
--
-- File history :
--
-- 0241 : First release
--
-- 0242 : Cleaned up reset logic
--
-- 0300 : MikeJ tidyup for audio release
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity invaderst is
port(
Rst_n : in std_logic;
Clk : in std_logic;
ENA : out std_logic;
Coin : in std_logic;
Sel1Player : in std_logic;
Sel2Player : in std_logic;
Fire1 : in std_logic;
Fire2 : in std_logic;
GunUp1 : in std_logic;
GunDown1 : in std_logic;
MoveLeft1 : in std_logic;
MoveRight1 : in std_logic;
MoveUp1 : in std_logic;
MoveDown1 : in std_logic;
GunUp2 : in std_logic;
GunDown2 : in std_logic;
MoveLeft2 : in std_logic;
MoveRight2 : in std_logic;
MoveUp2 : in std_logic;
MoveDown2 : in std_logic;
DIP : in std_logic_vector(8 downto 1);
RDB : in std_logic_vector(7 downto 0);
IB : in std_logic_vector(7 downto 0);
RWD : out std_logic_vector(7 downto 0);
RAB : out std_logic_vector(12 downto 0);
AD : out std_logic_vector(15 downto 0);
SoundCtrl3 : out std_logic_vector(5 downto 0);
SoundCtrl5 : out std_logic_vector(5 downto 0);
Rst_n_s : out std_logic;
RWE_n : out std_logic;
Video : out std_logic;
HSync : out std_logic;
VSync : out std_logic
);
end invaderst;
architecture rtl of invaderst is
component mw8080
port(
Rst_n : in std_logic;
Clk : in std_logic;
ENA : out std_logic;
RWE_n : out std_logic;
RDB : in std_logic_vector(7 downto 0);
RAB : out std_logic_vector(12 downto 0);
Sounds : out std_logic_vector(7 downto 0);
Ready : out std_logic;
GDB : in std_logic_vector(7 downto 0);
IB : in std_logic_vector(7 downto 0);
DB : out std_logic_vector(7 downto 0);
AD : out std_logic_vector(15 downto 0);
Status : out std_logic_vector(7 downto 0);
Systb : out std_logic;
Int : out std_logic;
Hold_n : in std_logic;
IntE : out std_logic;
DBin_n : out std_logic;
Vait : out std_logic;
HldA : out std_logic;
Sample : out std_logic;
Wr : out std_logic;
Video : out std_logic;
HSync : out std_logic;
VSync : out std_logic);
end component;
signal GDB0 : std_logic_vector(7 downto 0);
signal GDB1 : std_logic_vector(7 downto 0);
signal GDB2 : std_logic_vector(7 downto 0);
signal S : std_logic_vector(7 downto 0);
signal GDB : std_logic_vector(7 downto 0);
signal DB : std_logic_vector(7 downto 0);
signal Sounds : std_logic_vector(7 downto 0);
signal AD_i : std_logic_vector(15 downto 0);
signal PortWr : std_logic_vector(6 downto 2);
signal EA : std_logic_vector(2 downto 0);
signal D5 : std_logic_vector(15 downto 0);
signal WD_Cnt : unsigned(7 downto 0);
signal Sample : std_logic;
signal Rst_n_s_i : std_logic;
signal gun1 : std_logic_vector(2 downto 0);
signal gun2 : std_logic_vector(2 downto 0);
begin
Rst_n_s <= Rst_n_s_i;
RWD <= DB;
AD <= AD_i;
-- no Watchdog
process (Rst_n, Clk)
variable Rst_n_r : std_logic;
begin
if Rst_n = '0' then
Rst_n_r := '0';
Rst_n_s_i <= '0';
elsif Clk'event and Clk = '1' then
Rst_n_s_i <= Rst_n_r;
-- if WD_Cnt = 255 then
-- Rst_n_s_i <= '0';
-- end if;
Rst_n_r := '1';
end if;
end process;
process (Rst_n_s_i, Clk)
variable Old_S0 : std_logic;
begin
if Rst_n_s_i = '0' then
-- WD_Cnt <= (others => '0');
Old_S0 := '1';
elsif Clk'event and Clk = '1' then
-- if Sounds(0) = '1' and Old_S0 = '0' then
-- WD_Cnt <= WD_Cnt + 1;
-- end if;
-- if PortWr(6) = '1' then
-- WD_Cnt <= (others => '0');
-- end if;
Old_S0 := Sounds(0);
end if;
end process;
u_mw8080: mw8080
port map(
Rst_n => Rst_n_s_i,
Clk => Clk,
ENA => ENA,
RWE_n => RWE_n,
RDB => RDB,
IB => IB,
RAB => RAB,
Sounds => Sounds,
Ready => open,
GDB => GDB,
DB => DB,
AD => AD_i,
Status => open,
Systb => open,
Int => open,
Hold_n => '1',
IntE => open,
DBin_n => open,
Vait => open,
HldA => open,
Sample => Sample,
Wr => open,
Video => Video,
HSync => HSync,
VSync => VSync);
with AD_i(9 downto 8) select
GDB <= GDB0 when "00",
GDB1 when "01",
GDB2 when "10",
S when others;
--GDB <= GDB0 and GDB1 and GDB2 and S;--todo
GDB0(0) <= not MoveUp1;
GDB0(1) <= not MoveDown1;
GDB0(2) <= not MoveLeft1;
GDB0(3) <= not MoveRight1;
GDB0(4) <= not GunUp1;--Gun1(0);--todo
GDB0(5) <= '0';--not Gun1(1);--todo
GDB0(6) <= not GunDown1;--Gun1(2);--todo
GDB0(7) <= not Fire1;
GDB1(0) <= not MoveUp2;
GDB1(1) <= not MoveDown2;
GDB1(2) <= not MoveLeft2;
GDB1(3) <= not MoveRight2;
GDB1(4) <= not GunUp2;--Gun2(0);--todo
GDB1(5) <= '0';--not Gun2(1);--todo
GDB1(6) <= not GunDown2;--Gun2(2);--todo
GDB1(7) <= not Fire2;
GDB2(0) <= '0';--Coinage
GDB2(1) <= '0';--Coinage
GDB2(2) <= '0';--Coinage
GDB2(3) <= '0';--Coinage
GDB2(4) <= '0';--Game_Time
GDB2(5) <= '0';--Game_Time
GDB2(6) <= Coin;
GDB2(7) <= Sel1Player;
PortWr(2) <= '1' when AD_i(10 downto 8) = "010" and Sample = '1' else '0';
PortWr(3) <= '1' when AD_i(10 downto 8) = "011" and Sample = '1' else '0';
PortWr(4) <= '1' when AD_i(10 downto 8) = "100" and Sample = '1' else '0';
PortWr(5) <= '1' when AD_i(10 downto 8) = "101" and Sample = '1' else '0';
PortWr(6) <= '1' when AD_i(10 downto 8) = "110" and Sample = '1' else '0';
process (Rst_n_s_i, Clk)
variable OldSample : std_logic;
begin
if Rst_n_s_i = '0' then
D5 <= (others => '0');
EA <= (others => '0');
SoundCtrl3 <= (others => '0');
SoundCtrl5 <= (others => '0');
OldSample := '0';
elsif Clk'event and Clk = '1' then
if PortWr(2) = '1' then
EA <= DB(2 downto 0);
end if;
if PortWr(3) = '1' then
SoundCtrl3 <= DB(5 downto 0);
end if;
if PortWr(4) = '1' and OldSample = '0' then
D5(15 downto 8) <= DB;
D5(7 downto 0) <= D5(15 downto 8);
end if;
if PortWr(5) = '1' then
SoundCtrl5 <= DB(5 downto 0);
end if;
OldSample := Sample;
end if;
end process;
with EA select
S <= D5(15 downto 8) when "000",
D5(14 downto 7) when "001",
D5(13 downto 6) when "010",
D5(12 downto 5) when "011",
D5(11 downto 4) when "100",
D5(10 downto 3) when "101",
D5( 9 downto 2) when "110",
D5( 8 downto 1) when others;
end;

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-- Version : 0300
-- The latest version of this file can be found at:
-- http://www.fpgaarcade.com
-- minor tidy up by MikeJ
-------------------------------------------------------------------------------
-- Company:
-- Engineer: PaulWalsh
--
-- Create Date: 08:45:29 11/04/05
-- Design Name:
-- Module Name: Invaders Audio
-- Project Name: Space Invaders
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity invaders_audio is
Port (
Clk : in std_logic;
S1 : in std_logic_vector(5 downto 0);
S2 : in std_logic_vector(5 downto 0);
Aud : out std_logic_vector(7 downto 0)
);
end;
--* Port 3: (S1)
--* bit 0=UFO (repeats)
--* bit 1=Shot
--* bit 2=Base hit
--* bit 3=Invader hit
--* bit 4=Bonus base
--*
--* Port 5: (S2)
--* bit 0=Fleet movement 1
--* bit 1=Fleet movement 2
--* bit 2=Fleet movement 3
--* bit 3=Fleet movement 4
--* bit 4=UFO 2
architecture Behavioral of invaders_audio is
signal ClkDiv : unsigned(10 downto 0) := (others => '0');
signal ClkDiv2 : std_logic_vector(7 downto 0) := (others => '0');
signal Clk7680_ena : std_logic;
signal Clk480_ena : std_logic;
signal Clk240_ena : std_logic;
signal Clk60_ena : std_logic;
signal s1_t1 : std_logic_vector(5 downto 0);
signal s2_t1 : std_logic_vector(5 downto 0);
signal tempsum : std_logic_vector(7 downto 0);
signal vco_cnt : std_logic_vector(3 downto 0);
signal TriDir1 : std_logic;
signal Fnum : std_logic_vector(3 downto 0);
signal comp : std_logic;
signal SS : std_logic;
signal TrigSH : std_logic;
signal SHCnt : std_logic_vector(8 downto 0);
signal SH : std_logic_vector(7 downto 0);
signal SauHit : std_logic_vector(8 downto 0);
signal SHitTri : std_logic_vector(5 downto 0);
signal TrigIH : std_logic;
signal IHDir : std_logic;
signal IHDir1 : std_logic;
signal IHCnt : std_logic_vector(8 downto 0);
signal IH : std_logic_vector(7 downto 0);
signal InHit : std_logic_vector(8 downto 0);
signal IHitTri : std_logic_vector(5 downto 0);
signal TrigEx : std_logic;
signal Excnt : std_logic_vector(9 downto 0);
signal ExShift : std_logic_vector(15 downto 0);
signal Ex : std_logic_vector(2 downto 0);
signal Explo : std_logic;
signal TrigMis : std_logic;
signal MisShift : std_logic_vector(15 downto 0);
signal MisCnt : std_logic_vector(8 downto 0);
signal miscnt1 : unsigned(7 downto 0);
signal Mis : std_logic_vector(2 downto 0);
signal Missile : std_logic;
signal EnBG : std_logic;
signal BGFnum : std_logic_vector(7 downto 0);
signal BGCnum : std_logic_vector(7 downto 0);
signal bg_cnt : unsigned(7 downto 0);
signal BG : std_logic;
begin
-- do a crude addition of all sound samples
p_audio_mix : process
variable IHVol : std_logic_vector(6 downto 0);
variable SHVol : std_logic_vector(6 downto 0);
begin
wait until rising_edge(Clk);
IHVol(6 downto 0) := InHit(6 downto 0) and IH(6 downto 0);
SHVol(6 downto 0) := SauHit(6 downto 0) and SH(6 downto 0);
tempsum(7 downto 0) <= ('0' & IHVol) + ('0' & SHVol);
Aud(7) <= tempsum (7);
Aud(6) <= tempsum (6) xor (Mis(2) and Missile) xor (Ex(2) and Explo) xor BG;
Aud(5) <= tempsum (5) xor (Mis(1) and Missile) xor (Ex(1) and Explo) xor SS;
Aud(4) <= tempsum (4) xor (Mis(0) and Missile) xor (Ex(0) and Explo);
Aud(3 downto 0) <= tempsum (3 downto 0);
end process;
p_clkdiv : process
begin
wait until rising_edge(Clk);
Clk7680_ena <= '0';
if ClkDiv = 1277 then
Clk7680_ena <= '1';
ClkDiv <= (others => '0');
else
ClkDiv <= ClkDiv + 1;
end if;
end process;
p_clkdiv2 : process
begin
wait until rising_edge(Clk);
Clk480_ena <= '0';
Clk240_ena <= '0';
Clk60_ena <= '0';
if (Clk7680_ena = '1') then
ClkDiv2 <= ClkDiv2 + 1;
if (ClkDiv2(3 downto 0) = "0000") then
Clk480_ena <= '1';
end if;
if (ClkDiv2(4 downto 0) = "00000") then
Clk240_ena <= '1';
end if;
if (ClkDiv2(7 downto 0) = "00000000") then
Clk60_ena <= '1';
end if;
end if;
end process;
p_delay : process
begin
wait until rising_edge(Clk);
s1_t1 <= S1;
s2_t1 <= S2;
end process;
--*************************Saucer Sound***************************************
-- Implement a VCOscilator: frequency is set using counter end point(Fnum)
p_saucer_vco : process
variable term : std_logic_vector(3 downto 0);
begin
wait until rising_edge(Clk);
term := 8 + Fnum;
if (S1(0) = '1') and (Clk7680_ena = '1') then
if vco_cnt = term then
vco_cnt <= (others => '0');
SS <= not SS;
else
vco_cnt <= vco_cnt + 1;
end if;
end if;
end process;
-- Implement a 5.3Hz trianglular wave LFO control the Variable oscilator
-- this is 6Hz ?? 0123454321
p_saucer_lfo : process
begin
wait until rising_edge(Clk);
if (Clk60_ena = '1') then
if Fnum = 4 then -- 5 -1
Comp <= '1';
elsif Fnum = 1 then -- 0 +1
Comp <= '0';
end if;
if comp = '1' then
Fnum <= Fnum - 1 ;
else
Fnum <= Fnum + 1 ;
end if;
end if;
end process;
--**********************SAUCER HIT Sound**************************
-- Implement a 10Hz saw tooth LFO to control the Saucer Hit VCO
p_saucer_hit_vco : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if SHitTri = 48 then
SHitTri <= "000000";
else
SHitTri <= SHitTri+1;
end if;
end if;
end process;
-- Implement a trianglular wave VCO for Saucer Hit 200Hz to 1kHz approx
p_saucer_hit_lfo : process
begin
wait until rising_edge(Clk);
if (Clk7680_ena = '1') then
if TriDir1 = '1' then
if (SauHit +58 - SHitTri) < 190 + 256 then
SauHit <= SauHit +58 - SHitTri;
else
SauHit <= "110111110";
TriDir1 <= '0';
end if;
else
if (SauHit -58 + SHitTri) > 256 then
SauHit <= SauHit -58 + SHitTri;
else
SauHit <= "100000000";
TriDir1 <= '1';
end if;
end if;
end if;
end process;
-- Implement the ADSR for Saucer Hit Sound
p_saucer_adsr : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if (TrigSH = '1') then
SHCnt <= "100000000";
SH <= "11111111";
elsif (SHCnt(8) = '1') then
SHCnt <= SHCnt + "1";
if SHCnt(7 downto 0) = x"60" then -- 96
SH <= "01111111";
elsif SHCnt(7 downto 0) = x"90" then -- 144
SH <= "00111111";
elsif SHCnt(7 downto 0) = x"C0" then -- 192
SH <= "00000000";
end if;
end if;
end if;
end process;
-- Implement the trigger for The Saucer Hit Sound
p_saucer_hit : process
begin
wait until rising_edge(Clk);
if (S2(4) = '1') and (s2_t1(4) = '0') then -- rising_edge
TrigSH <= '1';
elsif (Clk480_ena = '1') then
TrigSH <= '0';
end if;
end process;
--***********************Invader Hit Sound*****************************
-- Implement a 5Hz Triangular Wave LFO to control the Invaders Hit VCO
p_invader_hit_lfo : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if IHitTri = 48-2 then
IHDir <= '0';
elsif IHitTri =0+2 then
IHDir <= '1';
end if;
if IHDir ='1' then
IHitTri <= IHitTri + 2;
else
IHitTri <= IHitTri - 2;
end if;
end if;
end process;
-- Implement a trianglular wave VCO for Invader Hit 700Hz to 3kHz approx
p_invader_hit_vco : process
begin
wait until rising_edge(Clk);
if (Clk7680_ena = '1') then
if IHDir1 = '1' then
if (InHit +10 + IHitTri) < 110 + 256 then
InHit <= InHit +10 + IHitTri;
else
InHit <= "101101110";
IHDir1 <= '0';
end if;
else
if (InHit -10 - IHitTri) > 256 then
InHit <= InHit -10 - IHitTri;
else
InHit <= "100000000";
IHDir1 <= '1';
end if;
end if;
end if;
end process;
-- Implement the ADSR for Invader Hit Sound
p_invader_adsr : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if (TrigIH = '1') then
IHCnt <= "100000000";
IH <= "11111111";
elsif (IHCnt(8) = '1') then
IHCnt <= IHCnt + "1";
if IHCnt(7 downto 0) = x"14" then -- 20
IH <= "01111111";
elsif IHCnt(7 downto 0) = x"1C" then -- 28
IH <= "11111111";
elsif IHCnt(7 downto 0) = x"30" then -- 48
IH <= "00000000";
end if;
end if;
end if;
end process;
-- Implement the trigger for The Invader Hit Sound
p_invader_hit : process
begin
wait until rising_edge(Clk);
if (S1(3) = '1') and (s1_t1(3) = '0') then -- rising_edge
TrigIH <= '1';
elsif (Clk480_ena = '1') then
TrigIH <= '0';
end if;
end process;
--***********************Explosion*****************************
-- Implement a Pseudo Random Noise Generator
p_explosion_pseudo : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if (ExShift = x"0000") then
ExShift <= "0000000010101001";
else
ExShift(0) <= Exshift(14) xor ExShift(15);
ExShift(15 downto 1) <= ExShift (14 downto 0);
end if;
end if;
end process;
Explo <= ExShift(0);
p_explosion_adsr : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if (TrigEx = '1') then
ExCnt <= "1000000000";
Ex <= "100";
elsif (ExCnt(9) = '1') then
ExCnt <= ExCnt + "1";
if ExCnt(8 downto 0) = '0' & x"64" then -- 100
Ex <= "010";
elsif ExCnt(8 downto 0) = '0' & x"c8" then -- 200
Ex <= "001";
elsif ExCnt(8 downto 0) = '1' & x"2c" then -- 300
Ex <= "000";
end if;
end if;
end if;
end process;
-- Implement the trigger for The Explosion Sound
p_explosion_trig : process
begin
wait until rising_edge(Clk);
if (S1(2) = '1') and (s1_t1(2) = '0') then -- rising_edge
TrigEx <= '1';
elsif (Clk480_ena = '1') then
TrigEx <= '0';
end if;
end process;
--***********************Missile*****************************
-- Implement a Pseudo Random Noise Generator
p_missile_pseudo : process
begin
wait until rising_edge(Clk);
if (Clk7680_ena = '1') then
if (MisShift = x"0000") then
MisShift <= "0000000010101001";
else
MisShift(0) <= MisShift(14) xor MisShift(15);
MisShift(15 downto 1) <= MisShift (14 downto 0);
end if;
miscnt1 <= miscnt1 + 20 + unsigned(MisShift(2 downto 0));
if miscnt1 > 60 then
miscnt1 <= "00000000";
Missile <= not Missile;
end if;
end if;
end process;
-- Implement the ADSR for The Missile Sound
p_missile_adsr : process
begin
wait until rising_edge(Clk);
if (Clk480_ena = '1') then
if (TrigMis = '1') then
MisCnt <= "100000000";
Mis <= "100";
elsif (MisCnt(8) = '1') then
MisCnt <= MisCnt + "1";
if MisCnt(7 downto 0) = x"4b" then -- 75
Mis <= "010";
elsif MisCnt(7 downto 0) = x"70" then -- 112
Mis <= "001";
elsif MisCnt(7 downto 0) = x"96" then -- 150
Mis <= "000";
end if;
end if;
end if;
end process;
-- Implement the trigger for The Missile Sound
p_missile_trig : process
begin
wait until rising_edge(Clk);
if (S1(1) = '1') and (s1_t1(1) = '0') then -- rising_edge
TrigMis <= '1';
elsif (Clk480_ena = '1') then
TrigMis <= '0';
end if;
end process;
-- ******************************** Background invader moving tones **************************
EnBG <= S2(0) or S2(1) or S2(2) or S2(3);
with S2(3 downto 0) select
BGFnum <= x"66" when "0001",
x"74" when "0010",
x"7C" when "0100",
x"87" when "1000",
x"87" when others;
with S2(3 downto 0) select
BGCnum <= x"33" when "0001",
x"3A" when "0010",
x"3E" when "0100",
x"43" when "1000",
x"43" when others;
-- Implement a Variable Oscilator: set frequency using counter mid(Cnum) and end points(Fnum)
p_background : process
begin
wait until rising_edge(Clk);
if (Clk7680_ena = '1') then
if EnBG = '0' then
bg_cnt <= x"00";
BG <= '0';
else
bg_cnt <= bg_cnt + 1;
if bg_cnt = unsigned(BGfnum) then
bg_cnt <= x"00";
BG <= '0';
elsif bg_cnt=unsigned(BGCnum) then
BG <='1';
end if;
end if;
end if;
end process;
end Behavioral;

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-- Midway 8080 main board
-- 9.984MHz Clock
--
-- Version : 0242
--
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.fpgaarcade.com
--
-- Limitations :
--
-- File history :
--
-- 0241 : First release
--
-- 0242 : Removed the ROM
--
-- 0300 : MikeJ tidyup for audio release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mw8080 is
port(
Rst_n : in std_logic;
Clk : in std_logic;
ENA : out std_logic;
RWE_n : out std_logic;
RDB : in std_logic_vector(7 downto 0);
RAB : out std_logic_vector(12 downto 0);
Sounds : out std_logic_vector(7 downto 0);
Ready : out std_logic;
GDB : in std_logic_vector(7 downto 0);
IB : in std_logic_vector(7 downto 0);
DB : out std_logic_vector(7 downto 0);
AD : out std_logic_vector(15 downto 0);
Status : out std_logic_vector(7 downto 0);
Systb : out std_logic;
Int : out std_logic;
Hold_n : in std_logic;
IntE : out std_logic;
DBin_n : out std_logic;
Vait : out std_logic;
HldA : out std_logic;
Sample : out std_logic;
Wr : out std_logic;
Video : out std_logic;
HSync : out std_logic;
VSync : out std_logic);
end mw8080;
architecture struct of mw8080 is
component T8080se
generic(
Mode : integer := 2;
T2Write : integer := 0);
port(
RESET_n : in std_logic;
CLK : in std_logic;
CLKEN : in std_logic;
READY : in std_logic;
HOLD : in std_logic;
INT : in std_logic;
INTE : out std_logic;
DBIN : out std_logic;
SYNC : out std_logic;
VAIT : out std_logic;
HLDA : out std_logic;
WR_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0));
end component;
signal Ready_i : std_logic;
signal Hold : std_logic;
signal IntTrig : std_logic;
signal IntTrigOld : std_logic;
signal Int_i : std_logic;
signal IntE_i : std_logic;
signal DBin : std_logic;
signal Sync : std_logic;
signal Wr_n, Rd_n : std_logic;
signal ClkEnCnt : unsigned(2 downto 0);
signal Status_i : std_logic_vector(7 downto 0);
signal A : std_logic_vector(15 downto 0);
signal ISel : std_logic_vector(1 downto 0);
signal DI : std_logic_vector(7 downto 0);
signal DO : std_logic_vector(7 downto 0);
signal RR : std_logic_vector(9 downto 0);
signal VidEn : std_logic;
signal CntD5 : unsigned(3 downto 0); -- Horizontal counter / 320
signal CntE5 : unsigned(4 downto 0); -- Horizontal counter 2
signal CntE6 : unsigned(3 downto 0); -- Vertical counter / 262
signal CntE7 : unsigned(4 downto 0); -- Vertical counter 2
signal Shift : std_logic_vector(7 downto 0);
begin
ENA <= ClkEnCnt(2);
Status <= Status_i;
Ready <= Ready_i;
DB <= DO;
Systb <= Sync;
Int <= Int_i;
Hold <= not Hold_n;
IntE <= IntE_i;
DBin_n <= not DBin;
Sample <= not Wr_n and Status_i(4);
Wr <= not Wr_n;
AD <= A;
Sounds(0) <= CntE7(3);
Sounds(1) <= CntE7(2);
Sounds(2) <= CntE7(1);
Sounds(3) <= CntE7(0);
Sounds(4) <= CntE6(3);
Sounds(5) <= CntE6(2);
Sounds(6) <= CntE6(1);
Sounds(7) <= CntE6(0);
IntTrig <= (not CntE7(2) nand CntE7(3)) nand not CntE7(4);
ISel(0) <= Status_i(0) nor (Status_i(6) nor A(13));
ISel(1) <= Status_i(0) nor Status_i(6);
with ISel select
DI <= "110" & CntE7(2) & not CntE7(2) & "111" when "00",
GDB when "01",
IB when "10",
RR(7 downto 0) when others;
RWE_n <= Wr_n or not (RR(8) xor RR(9)) or not CntD5(2);
RAB <= A(12 downto 0) when CntD5(2) = '1' else
std_logic_vector(CntE7(3 downto 0) & CntE6(3 downto 0) & CntE5(3 downto 0) & CntD5(3));
u_8080: T8080se
generic map (
Mode => 2,
T2Write => 1)
port map (
RESET_n => Rst_n,
CLK => Clk,
CLKEN => ClkEnCnt(2),
READY => Ready_i,
HOLD => Hold,
INT => Int_i,
INTE => IntE_i,
DBIN => DBin,
SYNC => Sync,
VAIT => Vait,
HLDA => HLDA,
WR_n => Wr_n,
A => A,
DI => DI,
DO => DO);
-- Clock enables
process (Rst_n, Clk)
begin
if Rst_n = '0' then
ClkEnCnt <= "000";
VidEn <= '0';
elsif Clk'event and Clk = '1' then
VidEn <= not VidEn;
if ClkEnCnt = 4 then
ClkEnCnt <= "000";
else
ClkEnCnt <= ClkEnCnt + 1;
end if;
end if;
end process;
-- Glue
process (Rst_n, Clk)
variable OldASEL : std_logic;
begin
if Rst_n = '0' then
Status_i <= (others => '0');
IntTrigOld <= '0';
Int_i <= '0';
OldASEL := '0';
Ready_i <= '0';
RR <= (others => '0');
elsif Clk'event and Clk = '1' then
-- E3
-- Interrupt
IntTrigOld <= IntTrig;
if Status_i(0) = '1' then
Int_i <= '0';
elsif IntTrigOld = '0' and IntTrig = '1' then
Int_i <= IntE_i;
end if;
-- D7
-- Status register
if Sync = '1' then
Status_i <= DO;
end if;
-- A3, C3, E3
-- RAM register/ready logic
if Sync = '1' and A(13) = '1' then
Ready_i <= '0';
elsif Ready_i = '1' then
Ready_i <= '1';
else
Ready_i <= RR(9);
end if;
if Sync = '1' and A(13) = '1' then
RR <= (others => '0');
elsif (CntD5(2) = '1' and OldASEL = '0') or -- ASEL pos edge
(CntD5(2) = '0' and OldASEL = '1' and RR(8) = '1') then -- ASEL neg edge
RR(7 downto 0) <= RDB;
RR(8) <= '1';
RR(9) <= RR(8);
end if;
OldASEL := CntD5(2);
end if;
end process;
-- Video counters
process (Rst_n, Clk)
begin
if Rst_n = '0' then
CntD5 <= (others => '0');
CntE5 <= (others => '0');
CntE6 <= (others => '0');
CntE7 <= (others => '0');
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
CntD5 <= CntD5 + 1;
if CntD5 = 15 then
CntE5 <= CntE5 + 1;
if CntE5(3 downto 0) = 15 then
if CntE5(4) = '0' then
CntE5 <= "11100";
CntE6 <= CntE6 + 1;
if CntE6 = 15 then
CntE7 <= CntE7 + 1;
if CntE7(3 downto 0) = 15 then
if CntE7(4) = '0' then
CntE6 <= "1010";
CntE7 <= "11101";
else
CntE7 <= "00010";
end if;
end if;
end if;
end if;
else
end if;
end if;
end if;
end if;
end process;
-- Video shift register
process (Rst_n, Clk)
begin
if Rst_n = '0' then
Shift <= (others => '0');
Video <= '0';
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
if CntE7(4) = '0' and CntE5(4) = '0' and CntD5(2 downto 0) = "011" then
Shift(7 downto 0) <= RDB(7 downto 0);
else
Shift(6 downto 0) <= Shift(7 downto 1);
Shift(7) <= '0';
end if;
Video <= Shift(0);
end if;
end if;
end process;
-- Sync
process (Rst_n, Clk)
begin
if Rst_n = '0' then
HSync <= '1';
VSync <= '1';
elsif Clk'event and Clk = '1' then
if VidEn = '1' then
if CntE5(4) = '1' and CntE5(1 downto 0) = "10" then
HSync <= '0';
else
HSync <= '1';
end if;
if CntE7(4) = '1' and CntE7(0) = '0' and CntE6(3 downto 2) = "11" then
VSync <= '0';
else
VSync <= '1';
end if;
end if;
end if;
end process;
end;

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<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
<global>
<pin name="inclk0" direction="input" scope="external" source="clock" />
<pin name="c0" direction="output" scope="external" source="clock" />
</global>
</pinplan>

4
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/pll.qip Normal file
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set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]

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Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/pll.vhd Normal file
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-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END pll;
ARCHITECTURE SYN OF pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 27,
clk0_duty_cycle => 50,
clk0_multiply_by => 10,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 37037,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-a.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
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:200180004040404040404040404040404000002547524C404649474851494C50454F51405C
:2001A000434D494C4040404040404040404040474551404F454144553A3A3A3A3A3A203A19
:2001C0003A3A3A3A3A4040444F41543B4040474D51404B453B484555404E414F444C454F86
:2001E0003B2E554D52404841534540434F454449513C00001A4E52504840425251514D4CAF
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-b.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:200000001F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F00C0CE
:200020007F00C01FC0801F7000073C800F0FF8FF03FCFF01CEFF00C61F00C61F00C61F0040
:20004000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F0088
:20006000C07F00C01F00801FC0000738800F0CF8FF0FFCFF03CE7F00C61F00C61F00C61F29
:2000800000C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C03F48
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:2000C0001F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700C028
:2000E0003F00C07F00C01F00801F00000700800F00F83F00FCFF01CEFF0FC61F7FC61F0016
:20010000C61F00C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01700E1
:20012000C03F00C07F00C01F00801F00000700800F00F83F00FCFF00CEFF01C6FF07C61FBC
:200140001EC61F70C61F00FA3F000315000500800D00800D00800F00C89F00F8FF00C01713
:2001600000C03F00C07F00C01F00801F00000700800F00F83F00FC7F00CEFF01C6FF03C61F
:200180001F17C61F0EC61F14FA3F20030CF03F00F03F00E03D00C07900C07100C0E100C08F
:2001A000E100E06000707000343400383800F0F000030CF03F00E03F00C01F00C01F00C0AB
:2001C0001F00C01F00001E00001C00000C00000D00000E00003C00030CF03F00F03F00E037
:2001E0001F00C00F00801F00003E00C07C00E07800703000343400383800F0F00003200421
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-c.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:200000007E3C181C1818181818183C3C3C7E66607C3E06067E7E3C7E6660387860667E3CF8
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:2000400060703038181C0C0C3C7E66663C7E66667E3C3C7E66667E7C60607C3C10383838A6
:2000600038383838387CC0C0C0C0C0C00000C0C00000000000000000C0C00000002040FF0D
:2000800040200000F0C0A09008040201000078FCCCE07030300030300000000000000000C1
:2000A0000000183C7E6666667E7E66663E7E66663E7E66667E3E3C7E6606060606667E3C50
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:2001200066667E3C3E7E66667E3E060606063E7E66667E3E766666663C7E66063E7C60664B
:200140007E3C7E7E181818181818181866666666666666667E3C66666666667E3C3C18181B
:20016000C3C3C3DBFFFFE7E7C3C366667E3C1818181818180116101818181858781B1A1E49
:200180001E9898783818181818181818021B000100038003C007C007601D00318007E01F53
:2001A000F03D383904418003C007E00FF81F3E2907E90001000900050005081F381B3829C6
:2001C000CC37FE5D0315000500800D00800D00800F00C89F00F8FF00C01780C03F50C07FB8
:2001E00060C01F30801F3800071C800F0EF8FF07FCFF03CEFF01C61F00C61F00C61F00C6BA
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-d.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:20000000CE0F3E07C3FB053A0820A7C8218208220020C921C52034C8352A00202B22002086
:20002000C90413010C610F0A24100F035A0001296D0F0026035A00010B990F143D052A203C
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:200100001E000109C50F0C2E030A072A20073D20000105A40F0E2E14099B080C05202A20B7
:2001200020FD0D0DC202030F000B2A20105F0E12032D00099B080E6010095D090E6050093E
:200140005D090E6090095D090E7810095D090E9010095D090E9050095D090E90900DB2025E
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:2001E00048094E0954095A09630900020000000000000000440000003C7E666666666666C7
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-e.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:20000000F21406471C7BE61FC20D06141404C20406C3FC05E5D521F809CA2406010A00097C
:200020003DC21F06EB0120003E0AF51A137709F13DC22A06D1E113F13DC2FB05C92A0020BE
:200040007E23220020320320C92A00207E23220020321520C9F3E10100001100003E1031DD
:200060000F40C513BAC26206AFD301310024FBE92A00205E2356232200201AE6BF1213AFA0
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:2000E000E3F5CD2D02F1E13DF2D5063A162047E680C2030778F68032162021220F3A052060
:20010000C3C5063A1620E640C0F6403216203E04D302AF21360FC3D506E5F52150207EE6C4
:2001200080C22D07EB0E0F21520FCD72033A1620F640321620F1E1C92A00205E235623226E
:2001400000201A3C2712CDA3052A00205E235623F33E801213137E2312131313131AC60867
:20016000124E234623220020131313EB71237023AF772377C92A00207ED301237E232200FB
:2001800020321420C92A00203A1D205E235623220020922E0267CD5903EBE54B70230DC244
:2001A0009C07E10E200915C29A07C921002111C40B1AA7C87723134F1A13477723C578064B
:2001C0000009472B1A13D5571E0006087A1F577B175F05C2CC0773D10DC2C307C178060088
:2001E000094705C2BD07C3B107213F20C3F207212C205E0104000956CD59031B151515219A
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-f.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:20000000220020C93A0920FE22F4A705C9AEC84F0601790FDA20044F7807471313C3120483
:2000200078AE77A0EB4E236669E91AE6700F0F0FA7C8321A2021E20E112A20C34F041AE675
:20004000700F0F0FA7C8321B2021F00E113D204F0600094E2346EB36C0110B00197123706B
:20006000C906FEC268040600212A2036C01105001970C90602C3630406FFC27F0406002113
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:2000C000C01112201AA7C0E5EB11A23E011020CDFA043EE2D301112C2001081A3A1A2021D6
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:20018000E630CA90054F78C6104779D610C285057832042021C62035210220AF772377232B
:2001A0002377C9AF3203200E04211E201102201A1F1F1F1FE60FC2BB053E10C63077231A2F
:2001C000E60FF63077062B79FE03C2D605062C1AA7C2D6053640132370230DC2AF053E08AD
:2001E000211E20110524C3FB052A00207E235E235623D55E235623220020E1F57E23D63030
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-g.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:200000002777C21802C314022115207EA7CA180235C2180221C52035DB0247DB02B8210602
:2000200020119E09CC0D04F1C1D1E1FBC97AB3C81A134F1A8032BC201A1347C5E51A13D3AC
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:2000C00023567723477AB3EBC9E5010F0009444D2F32BD203E60BA21AB20D2E00221B2202D
:2000E00071237023CD5903732372237123E37EEB210B0019EBE3732372EB1717DA14031769
:20010000DA3E032B562B5E0104003E8009732372E1AE77C9E13E50BDC8E53E2ABD214903AC
:20012000CA26032151033A0920E60C0F856FD23203245E2356E1E5010D00AFC30C03AF7782
:20014000237723772377E177C98B0DB10DD70DB10DC722ED221323ED227BE6074F0603AF0C
:200160007A1F577B1F5F05C25F03E521002419EBE1C9F37E2312130DC27303C9D55F160084
:200180001978462356E1865F232323237E8257C93E08210220060070233DC29703CD5506BA
:2001A000212108220020FB2A00203AC620A7CAB403219B085E23220020160021AE0919197F
:2001C0005E2356EB11A603D5E9CD1308DB0047DB00B8211720117E09CC0D04DB0147DB017C
:2001E000B8211820118E09CC0D04211C207EA7CA04043600075F160021D609195E2356EB88
:00000001FF

18
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/roms/gf-h.hex Normal file
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@@ -0,0 +1,18 @@
:020000040000FA
:200000000000310024C39003E5D5C5F5C3870077E5D5C5F521B9207E2F77A7FAEA00216F53
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:2000E000237023D1732372C318022163207EA7E5F25101237EA7237EFA0301FE70D2080172
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:20016000A7F283013EFF32C420CD5E027E17F67FA677F28301E501090009CD59037323721C
:200180002371E1011200093EABBDC25F012ABE207DB4C29801212A2022C020AF32BD207EC9
:2001A000A7F2B101CD5E023ABD20A7CCC90222BE20111300193E63BDC2BE01212A203AC0F1
:2001C00020BDC29F012114207EA7CAD40135C2D401AFD30121092035F20802362221042060
:2001E0007EA7CAF601C6992777C2F601EB21C42034C29D03EB342103207EA7CA0802C69922
:00000001FF

55
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/spram.vhd Normal file
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@@ -0,0 +1,55 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY spram IS
generic (
addr_width_g : integer := 8;
data_width_g : integer := 8
);
PORT
(
address : IN STD_LOGIC_VECTOR (addr_width_g-1 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (data_width_g-1 DOWNTO 0)
);
END spram;
ARCHITECTURE SYN OF spram IS
BEGIN
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_g,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => addr_width_g,
width_a => data_width_g,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => q
);
END SYN;

82
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/GunFight_MiST/rtl/sprom.vhd Normal file
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@@ -0,0 +1,82 @@
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sprom IS
GENERIC
(
init_file : string := "";
widthad_a : natural;
width_a : natural := 8;
outdata_reg_a : string := "UNREGISTERED"
);
PORT
(
address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END sprom;
ARCHITECTURE SYN OF sprom IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(width_a-1 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => init_file,
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 2**widthad_a,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => outdata_reg_a,
widthad_a => widthad_a,
width_a => width_a,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;

1
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/SpaceWalk_MiST/SpaceWalk.qsf
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@@ -49,7 +49,6 @@ set_global_assignment -name VHDL_FILE rtl/invaders.vhd
set_global_assignment -name VHDL_FILE rtl/mw8080.vhd
set_global_assignment -name VHDL_FILE rtl/invaders_audio.vhd
set_global_assignment -name SYSTEMVERILOG_FILE rtl/invaders_memory.sv
set_global_assignment -name VHDL_FILE rtl/dac.vhd
set_global_assignment -name VHDL_FILE rtl/sprom.vhd
set_global_assignment -name VHDL_FILE rtl/spram.vhd
set_global_assignment -name VHDL_FILE rtl/T80/T8080se.vhd

4
Arcade_MiST/Midway-Taito 8080 Hardware/Midway8080_MiST/SpaceWalk_MiST/rtl/invaders_memory.sv
View File

@@ -106,8 +106,8 @@ always @(Addr, rom_data_0, rom_data_1, rom_data_2, rom_data_3, rom_data_4, rom_d
Rom_out = 8'b00000000;
case (Addr[13:10])
4'b0000 : Rom_out = rom_data_0;
4'b0001 : Rom_out = rom_data_1;
4'b0010 : Rom_out = rom_data_2;
4'b0001 : Rom_out = rom_data_1;// 0100 0000 0000
4'b0010 : Rom_out = rom_data_2;// 1000 0000 0000
4'b0011 : Rom_out = rom_data_3;
4'b0100 : Rom_out = rom_data_4;