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mirror of https://github.com/Gehstock/Mist_FPGA.git synced 2026-01-18 09:02:08 +00:00

Some Changes

This commit is contained in:
Marcel 2019-07-07 15:14:15 +02:00
parent fe2817b3d2
commit e4838615e3
5 changed files with 46 additions and 53 deletions

View File

@ -45,7 +45,7 @@ wire pll_locked;
pll pll(
.inclk0(CLOCK_27),
.areset(0),
.c0(clk_sys)//11
.c0(clk_sys)
);
wire [31:0] status;
@ -57,12 +57,8 @@ wire scandoublerD;
wire ypbpr;
reg [11:0] audio;
wire hb1, hb2, vb;
<<<<<<< HEAD
wire blankn = ~(hb1 | hb2 | vb);
=======
wire blankn = ~((hb1 & hb2) | vb);
wire ce_pix;
>>>>>>> 446007a4fb619051d6e65af18a1c0b2ed9b4dae6
wire hs, vs;
wire [1:0] r,g,b;

View File

@ -5,29 +5,29 @@ entity col_h is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of col_h is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"04",X"06",X"04",X"04",X"04",X"04",
X"01",X"01",X"02",X"02",X"03",X"03",X"03",X"03",X"06",X"06",X"03",X"01",X"01",X"01",X"01",X"01",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"00",X"00",X"04",X"03",X"03",
X"02",X"05",X"05",X"04",X"04",X"03",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"05",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"04",X"06",X"03",X"03",X"03",X"03",
X"01",X"05",X"02",X"05",X"05",X"05",X"05",X"05",X"06",X"05",X"03",X"01",X"04",X"04",X"04",X"04",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"02",X"02",X"04",X"03",X"03",
X"02",X"05",X"05",X"01",X"01",X"03",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"05",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"02",X"02",X"05",X"05",X"05",X"05",
X"00",X"01",X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"02",X"03",X"05",X"02",X"02",X"02",X"02",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"00",X"00",X"01",X"03",X"03",
X"02",X"05",X"05",X"03",X"03",X"04",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"02",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"04",X"04",X"01",X"01",X"01",X"01",
X"01",X"06",X"02",X"05",X"06",X"06",X"06",X"06",X"06",X"03",X"03",X"01",X"07",X"07",X"07",X"07",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"01",X"01",X"01",X"03",X"03",
X"02",X"05",X"05",X"04",X"04",X"04",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"02",X"05",X"05");
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0100","0110","0100","0100","0100","0100",
"0001","0001","0010","0010","0011","0011","0011","0011","0110","0110","0011","0001","0001","0001","0001","0001",
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0000","0000","0100","0011","0011",
"0010","0101","0101","0100","0100","0011","0111","0111","0110","0111","0111","0101","0101","0101","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0100","0110","0011","0011","0011","0011",
"0001","0101","0010","0101","0101","0101","0101","0101","0110","0101","0011","0001","0100","0100","0100","0100",
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0010","0010","0100","0011","0011",
"0010","0101","0101","0001","0001","0011","0111","0111","0110","0111","0111","0111","0111","0101","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0010","0010","0101","0101","0101","0101",
"0000","0001","0010","0010","0000","0000","0000","0000","0000","0010","0011","0101","0010","0010","0010","0010",
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0000","0000","0001","0011","0011",
"0010","0101","0101","0011","0011","0100","0111","0111","0110","0111","0111","0111","0111","0010","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0100","0100","0001","0001","0001","0001",
"0001","0110","0010","0101","0110","0110","0110","0110","0110","0011","0011","0001","0111","0111","0111","0111",
"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0001","0001","0001","0011","0011",
"0010","0101","0101","0100","0100","0100","0111","0111","0110","0111","0111","0101","0101","0010","0101","0101");
begin
process(clk)
begin

View File

@ -5,29 +5,29 @@ entity col_l is
port (
clk : in std_logic;
addr : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0)
data : out std_logic_vector(3 downto 0)
);
end entity;
architecture prom of col_l is
type rom is array(0 to 255) of std_logic_vector(7 downto 0);
type rom is array(0 to 255) of std_logic_vector(3 downto 0);
signal rom_data: rom := (
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"05",X"06",X"04",X"04",X"04",X"04",
X"01",X"01",X"06",X"02",X"03",X"03",X"03",X"03",X"06",X"06",X"03",X"01",X"01",X"01",X"01",X"01",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"00",X"00",X"04",X"03",X"03",
X"06",X"05",X"05",X"04",X"04",X"03",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"05",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"05",X"06",X"03",X"03",X"03",X"03",
X"01",X"05",X"06",X"05",X"05",X"05",X"05",X"05",X"06",X"05",X"03",X"03",X"04",X"04",X"04",X"04",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"06",X"06",X"04",X"03",X"03",
X"06",X"05",X"05",X"01",X"01",X"03",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"05",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"02",X"02",X"05",X"05",X"05",X"05",
X"01",X"01",X"02",X"02",X"00",X"00",X"00",X"00",X"06",X"02",X"03",X"05",X"02",X"02",X"02",X"02",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"00",X"00",X"01",X"03",X"03",
X"06",X"05",X"05",X"03",X"03",X"04",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"02",X"05",X"05",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"05",X"07",X"01",X"01",X"01",X"01",
X"01",X"06",X"06",X"05",X"06",X"06",X"06",X"06",X"06",X"03",X"03",X"03",X"07",X"07",X"07",X"07",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"03",X"03",X"01",X"03",X"03",
X"06",X"05",X"05",X"04",X"04",X"04",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"02",X"05",X"05");
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0101","0110","0100","0100","0100","0100",
"0001","0001","0110","0010","0011","0011","0011","0011","0110","0110","0011","0001","0001","0001","0001","0001",
"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0000","0000","0100","0011","0011",
"0110","0101","0101","0100","0100","0011","0111","0111","0110","0111","0111","0101","0101","0101","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0101","0110","0011","0011","0011","0011",
"0001","0101","0110","0101","0101","0101","0101","0101","0110","0101","0011","0011","0100","0100","0100","0100",
"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0110","0110","0100","0011","0011",
"0110","0101","0101","0001","0001","0011","0111","0111","0110","0111","0111","0111","0111","0101","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0010","0010","0101","0101","0101","0101",
"0001","0001","0010","0010","0000","0000","0000","0000","0110","0010","0011","0101","0010","0010","0010","0010",
"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0000","0000","0001","0011","0011",
"0110","0101","0101","0011","0011","0100","0111","0111","0110","0111","0111","0111","0111","0010","0101","0101",
"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0101","0111","0001","0001","0001","0001",
"0001","0110","0110","0101","0110","0110","0110","0110","0110","0011","0011","0011","0111","0111","0111","0111",
"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0011","0011","0001","0011","0011",
"0110","0101","0101","0100","0100","0100","0111","0111","0110","0111","0111","0101","0101","0010","0101","0101");
begin
process(clk)
begin

View File

@ -106,11 +106,9 @@ architecture struct of phoenix is
signal fr_lin : std_logic_vector(2 downto 0);
signal bk_lin : std_logic_vector(2 downto 0);
signal color_set : std_logic;
signal color_set2 : std_logic;
signal color_set : std_logic_vector(1 downto 0);
signal color_id : std_logic_vector(5 downto 0);
signal rgb_0 : std_logic_vector(7 downto 0);
signal rgb_1 : std_logic_vector(7 downto 0);
signal rgb : std_logic_vector(7 downto 0);
signal player2 : std_logic := '0';
signal pl2_cocktail : std_logic := '0';
@ -228,8 +226,7 @@ begin
when "11000" => sound_b <= cpu_do;
when "11010" => sound_a <= cpu_do;
when "10100" => player2 <= cpu_do(0);
color_set <= cpu_do(1);
color_set2 <= cpu_do(2);
color_set <= cpu_do(2 downto 1);
A11 <= cpu_do(3);
when others => null;
end case;
@ -288,7 +285,7 @@ color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
-- address palette with pixel bits color and color set
palette_adr <= color_set2 & color_set & color_id;
palette_adr <= color_set & color_id;
-- output video to top level
process(clk) begin
@ -298,9 +295,9 @@ process(clk) begin
video_hblank_fg <= hblank_frgrd;
video_hblank_bg <= hblank_bkgrd;
if hcnt>=192 then
video_r <= rgb_1(0) & rgb_0(0);
video_g <= rgb_1(2) & rgb_0(2);
video_b <= rgb_1(1) & rgb_0(1);
video_r <= rgb(4) & rgb(0);
video_g <= rgb(6) & rgb(2);
video_b <= rgb(5) & rgb(1);
else
video_r <= "00";
video_g <= "00";
@ -342,14 +339,14 @@ col_l : entity work.col_l
port map(
clk => clk,
addr => palette_adr(7 downto 0),
data => rgb_0
data => rgb(7 downto 4)
);
col_h : entity work.col_h
port map(
clk => clk,
addr => palette_adr(7 downto 0),
data => rgb_1
data => rgb(3 downto 0)
);