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https://github.com/Gehstock/Mist_FPGA.git
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Some Changes
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@ -45,7 +45,7 @@ wire pll_locked;
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pll pll(
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.inclk0(CLOCK_27),
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.areset(0),
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.c0(clk_sys)//11
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.c0(clk_sys)
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);
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wire [31:0] status;
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@ -57,12 +57,8 @@ wire scandoublerD;
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wire ypbpr;
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reg [11:0] audio;
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wire hb1, hb2, vb;
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<<<<<<< HEAD
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wire blankn = ~(hb1 | hb2 | vb);
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=======
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wire blankn = ~((hb1 & hb2) | vb);
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wire ce_pix;
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>>>>>>> 446007a4fb619051d6e65af18a1c0b2ed9b4dae6
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wire hs, vs;
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wire [1:0] r,g,b;
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@ -5,29 +5,29 @@ entity col_h is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(7 downto 0);
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data : out std_logic_vector(7 downto 0)
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data : out std_logic_vector(3 downto 0)
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);
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end entity;
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architecture prom of col_h is
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type rom is array(0 to 255) of std_logic_vector(7 downto 0);
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type rom is array(0 to 255) of std_logic_vector(3 downto 0);
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signal rom_data: rom := (
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"04",X"06",X"04",X"04",X"04",X"04",
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X"01",X"01",X"02",X"02",X"03",X"03",X"03",X"03",X"06",X"06",X"03",X"01",X"01",X"01",X"01",X"01",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"00",X"00",X"04",X"03",X"03",
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X"02",X"05",X"05",X"04",X"04",X"03",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"05",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"04",X"06",X"03",X"03",X"03",X"03",
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X"01",X"05",X"02",X"05",X"05",X"05",X"05",X"05",X"06",X"05",X"03",X"01",X"04",X"04",X"04",X"04",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"02",X"02",X"04",X"03",X"03",
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X"02",X"05",X"05",X"01",X"01",X"03",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"05",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"02",X"02",X"05",X"05",X"05",X"05",
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X"00",X"01",X"02",X"02",X"00",X"00",X"00",X"00",X"00",X"02",X"03",X"05",X"02",X"02",X"02",X"02",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"00",X"00",X"01",X"03",X"03",
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X"02",X"05",X"05",X"03",X"03",X"04",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"02",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"04",X"04",X"01",X"01",X"01",X"01",
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X"01",X"06",X"02",X"05",X"06",X"06",X"06",X"06",X"06",X"03",X"03",X"01",X"07",X"07",X"07",X"07",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"04",X"01",X"01",X"01",X"01",X"01",X"03",X"03",
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X"02",X"05",X"05",X"04",X"04",X"04",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"02",X"05",X"05");
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0100","0110","0100","0100","0100","0100",
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"0001","0001","0010","0010","0011","0011","0011","0011","0110","0110","0011","0001","0001","0001","0001","0001",
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"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0000","0000","0100","0011","0011",
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"0010","0101","0101","0100","0100","0011","0111","0111","0110","0111","0111","0101","0101","0101","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0100","0110","0011","0011","0011","0011",
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"0001","0101","0010","0101","0101","0101","0101","0101","0110","0101","0011","0001","0100","0100","0100","0100",
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"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0010","0010","0100","0011","0011",
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"0010","0101","0101","0001","0001","0011","0111","0111","0110","0111","0111","0111","0111","0101","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0010","0010","0101","0101","0101","0101",
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"0000","0001","0010","0010","0000","0000","0000","0000","0000","0010","0011","0101","0010","0010","0010","0010",
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"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0000","0000","0001","0011","0011",
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"0010","0101","0101","0011","0011","0100","0111","0111","0110","0111","0111","0111","0111","0010","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0100","0100","0001","0001","0001","0001",
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"0001","0110","0010","0101","0110","0110","0110","0110","0110","0011","0011","0001","0111","0111","0111","0111",
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"0000","0000","0000","0000","0000","0000","0000","0000","0100","0001","0001","0001","0001","0001","0011","0011",
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"0010","0101","0101","0100","0100","0100","0111","0111","0110","0111","0111","0101","0101","0010","0101","0101");
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begin
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process(clk)
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begin
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@ -5,29 +5,29 @@ entity col_l is
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port (
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clk : in std_logic;
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addr : in std_logic_vector(7 downto 0);
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data : out std_logic_vector(7 downto 0)
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data : out std_logic_vector(3 downto 0)
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);
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end entity;
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architecture prom of col_l is
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type rom is array(0 to 255) of std_logic_vector(7 downto 0);
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type rom is array(0 to 255) of std_logic_vector(3 downto 0);
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signal rom_data: rom := (
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"05",X"06",X"04",X"04",X"04",X"04",
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X"01",X"01",X"06",X"02",X"03",X"03",X"03",X"03",X"06",X"06",X"03",X"01",X"01",X"01",X"01",X"01",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"00",X"00",X"04",X"03",X"03",
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X"06",X"05",X"05",X"04",X"04",X"03",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"05",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"05",X"06",X"03",X"03",X"03",X"03",
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X"01",X"05",X"06",X"05",X"05",X"05",X"05",X"05",X"06",X"05",X"03",X"03",X"04",X"04",X"04",X"04",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"06",X"06",X"04",X"03",X"03",
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X"06",X"05",X"05",X"01",X"01",X"03",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"05",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"02",X"02",X"02",X"05",X"05",X"05",X"05",
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X"01",X"01",X"02",X"02",X"00",X"00",X"00",X"00",X"06",X"02",X"03",X"05",X"02",X"02",X"02",X"02",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"00",X"00",X"01",X"03",X"03",
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X"06",X"05",X"05",X"03",X"03",X"04",X"07",X"07",X"06",X"07",X"07",X"07",X"07",X"02",X"05",X"05",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"02",X"04",X"05",X"07",X"01",X"01",X"01",X"01",
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X"01",X"06",X"06",X"05",X"06",X"06",X"06",X"06",X"06",X"03",X"03",X"03",X"07",X"07",X"07",X"07",
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X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"06",X"01",X"01",X"03",X"03",X"01",X"03",X"03",
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X"06",X"05",X"05",X"04",X"04",X"04",X"07",X"07",X"06",X"07",X"07",X"05",X"05",X"02",X"05",X"05");
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0101","0110","0100","0100","0100","0100",
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"0001","0001","0110","0010","0011","0011","0011","0011","0110","0110","0011","0001","0001","0001","0001","0001",
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"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0000","0000","0100","0011","0011",
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"0110","0101","0101","0100","0100","0011","0111","0111","0110","0111","0111","0101","0101","0101","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0101","0110","0011","0011","0011","0011",
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"0001","0101","0110","0101","0101","0101","0101","0101","0110","0101","0011","0011","0100","0100","0100","0100",
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"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0110","0110","0100","0011","0011",
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"0110","0101","0101","0001","0001","0011","0111","0111","0110","0111","0111","0111","0111","0101","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0010","0010","0010","0101","0101","0101","0101",
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"0001","0001","0010","0010","0000","0000","0000","0000","0110","0010","0011","0101","0010","0010","0010","0010",
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"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0000","0000","0001","0011","0011",
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"0110","0101","0101","0011","0011","0100","0111","0111","0110","0111","0111","0111","0111","0010","0101","0101",
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"0000","0000","0000","0000","0000","0000","0000","0000","0010","0100","0101","0111","0001","0001","0001","0001",
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"0001","0110","0110","0101","0110","0110","0110","0110","0110","0011","0011","0011","0111","0111","0111","0111",
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"0000","0000","0000","0000","0000","0000","0000","0000","0110","0001","0001","0011","0011","0001","0011","0011",
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"0110","0101","0101","0100","0100","0100","0111","0111","0110","0111","0111","0101","0101","0010","0101","0101");
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begin
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process(clk)
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begin
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@ -106,11 +106,9 @@ architecture struct of phoenix is
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signal fr_lin : std_logic_vector(2 downto 0);
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signal bk_lin : std_logic_vector(2 downto 0);
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signal color_set : std_logic;
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signal color_set2 : std_logic;
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signal color_set : std_logic_vector(1 downto 0);
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signal color_id : std_logic_vector(5 downto 0);
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signal rgb_0 : std_logic_vector(7 downto 0);
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signal rgb_1 : std_logic_vector(7 downto 0);
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signal rgb : std_logic_vector(7 downto 0);
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signal player2 : std_logic := '0';
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signal pl2_cocktail : std_logic := '0';
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@ -228,8 +226,7 @@ begin
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when "11000" => sound_b <= cpu_do;
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when "11010" => sound_a <= cpu_do;
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when "10100" => player2 <= cpu_do(0);
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color_set <= cpu_do(1);
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color_set2 <= cpu_do(2);
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color_set <= cpu_do(2 downto 1);
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A11 <= cpu_do(3);
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when others => null;
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end case;
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@ -288,7 +285,7 @@ color_id <= (fr_bit0 or fr_bit1) & fr_bit1 & fr_bit0 & fr_lin when (fr_bit0 o
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(fr_bit0 or fr_bit1) & bk_bit1 & bk_bit0 & bk_lin;
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-- address palette with pixel bits color and color set
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palette_adr <= color_set2 & color_set & color_id;
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palette_adr <= color_set & color_id;
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-- output video to top level
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process(clk) begin
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@ -298,9 +295,9 @@ process(clk) begin
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video_hblank_fg <= hblank_frgrd;
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video_hblank_bg <= hblank_bkgrd;
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if hcnt>=192 then
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video_r <= rgb_1(0) & rgb_0(0);
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video_g <= rgb_1(2) & rgb_0(2);
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video_b <= rgb_1(1) & rgb_0(1);
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video_r <= rgb(4) & rgb(0);
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video_g <= rgb(6) & rgb(2);
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video_b <= rgb(5) & rgb(1);
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else
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video_r <= "00";
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video_g <= "00";
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@ -342,14 +339,14 @@ col_l : entity work.col_l
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port map(
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clk => clk,
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addr => palette_adr(7 downto 0),
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data => rgb_0
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data => rgb(7 downto 4)
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);
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col_h : entity work.col_h
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port map(
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clk => clk,
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addr => palette_adr(7 downto 0),
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data => rgb_1
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data => rgb(3 downto 0)
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);
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