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Update bram.vhd

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Marcel 2021-12-12 21:33:46 +01:00 committed by GitHub
parent 745ff6a00d
commit e7975451a1
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@ -38,7 +38,7 @@ BEGIN
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME="&mem_name,
lpm_type => "altsyncram",
numwords_a => 2**addr_width,
@ -159,7 +159,7 @@ BEGIN
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone V",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 2**addr_width_a,
numwords_b => 2**addr_width_b,