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https://github.com/Gehstock/Mist_FPGA.git
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Robotron HW: the .ARC files also generated from the MRA
This commit is contained in:
Gyorgy Szombathelyi
parent
ab5003701b
commit
f1330a1f80
@ -10,8 +10,8 @@ Sinistar has some graphics issues, and the speech chip is not implemented.
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Usage:
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------
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- Create ROM and ARC files from MAME ROM zip files using the mra utility and the MRA files.
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- Copy the RBF and the ARC files to the same folder.
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- Create ROM files from MAME ROM zip files using the mra utility and the MRA files.
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- Example: mra -z /path/to/mame/roms scramble.mra
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- Copy the ROM files to the root of the SD Card.
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=5
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=3
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=1
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=0
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=6
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=2
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@ -1,3 +0,0 @@
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[ARC]
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RBF=ROBOTRON
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MOD=4
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Alien Arena</name>
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<mameversion>0209</mameversion>
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<rbf>Robotron</rbf>
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<setname>alienar</setname>
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<rom index="1"><part>5</part></rom>
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<rom index="0" zip="alienar.zip" md5="342b7d5d91dc2cd81f7f193b076555d2" type="merged">
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<part name="aarom01"/>
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<part name="aarom02"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Bubbles</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>bubbles</setname>
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<rom index="1"><part>3</part></rom>
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<rom index="0" zip="bubbles.zip" md5="6b23d478539f579c4ffe30cae83c28d8" type="merged">
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<part name="bubbles.1b"/>
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<part name="bubbles.2b"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Joust</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>joust</setname>
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<rom index="1"><part>1</part></rom>
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<rom index="0" zip="joust.zip" md5="190c1b26e2103232a58405f8ebdd752c" type="merged">
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<part name="3006-13.1b"/>
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<part name="3006-14.2b"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Robotron 2084</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>robotron</setname>
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<rom index="1"><part>0</part></rom>
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<rom index="0" zip="robotron.zip" md5="1d2f8e7d602ec2f848bad17f3cf928e2" type="merged">
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<part name="robotron.sb1"/>
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<part name="robotron.sb2"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Sinistar</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>sinistar</setname>
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<rom index="1"><part>6</part></rom>
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<rom index="0" zip="sinistar.zip" md5="60b465866ccf143727ff2ce9027e0886" type="merged">
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<part name="sinistar.01"/>
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<part name="sinistar.02"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Splat</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>splat</setname>
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<rom index="1"><part>2</part></rom>
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<rom index="0" zip="splat.zip" md5="401f6ca6baac2701f84a0edc6bea69ab" type="merged">
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<part name="splat.01"/>
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<part name="splat.02"/>
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@ -1,6 +1,9 @@
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<misterromdescription>
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<name>Stargate</name>
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<mameversion>0209</mameversion>
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<rbf>robotron</rbf>
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<setname>stargate</setname>
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<rom index="1"><part>4</part></rom>
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<rom index="0" zip="stargate.zip" md5="764a1192d52ef54eead60849d11dfcaa" type="merged">
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<part name="01"/>
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<part name="02"/>
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@ -38,8 +38,10 @@ module RobotronFPGA_MiST(
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`include "rtl/build_id.v"
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`define CORE_NAME "ROBOTRON"
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localparam CONF_STR = {
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";ROM;",
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`CORE_NAME,";ROM;",
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"O2,Rotate Controls,Off,On;",
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"O34,Scanlines,Off,25%,50%,75%;",
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"O5,Blend,Off,On;",
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@ -64,7 +66,6 @@ reg [3:0] BTN;
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reg blitter_sc2, sinistar;
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wire [6:0] core_mod;
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reg [8*8-1:0] core_name;
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reg [1:0] orientation; // [left/right, landscape/portrait]
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// advance button
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@ -85,59 +86,51 @@ always @(*) begin
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JA = 8'hFF;
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JB = 8'hFF;
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BTN = 4'hF;
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core_name = "ROBOTRON";
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blitter_sc2 = 0;
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sinistar = 0;
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case (core_mod)
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7'h0:
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7'h0: // ROBOTRON
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begin
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core_name = "ROBOTRON";
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BTN = { m_one_player, m_two_players, m_coin1 | m_coin2, reset };
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// Fire Up/Down/Left/Right maps to joystick 1/2/3/4 and keyboard R/F/D/G (MAME style)
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JA = ~{ m_fireD|m_right2, m_fireC|m_left2, m_fireB|m_down2, m_fireA|m_up2, m_right, m_left, m_down, m_up };
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JB = ~{ m_fireD|m_right2, m_fireC|m_left2, m_fireB|m_down2, m_fireA|m_up2, m_right, m_left, m_down, m_up };
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end
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7'h1:
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7'h1: // JOUST
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begin
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core_name = "JOUST ";
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BTN = { m_two_players, m_one_player, m_coin1 | m_coin2, reset };
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JA = ~{ 5'b00000, m_fireA, m_right, m_left };
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JB = ~{ 5'b00000, m_fire2A, m_right2, m_left2 };
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end
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7'h2:
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7'h2: // SPLAT
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begin
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core_name = "SPLAT ";
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blitter_sc2 = 1;
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BTN = { m_one_player, m_two_players, m_coin1 | m_coin2, reset };
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// Fire Up/Down/Left/Right maps to joystick 1/2/3/4 and keyboard R/F/D/G (MAME style)
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JA = ~{ m_fireD|m_right2, m_fireC|m_left2, m_fireB|m_down2, m_fireA|m_up2, m_right, m_left, m_down, m_up };
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JB = ~{ m_fireD|m_right2, m_fireC|m_left2, m_fireB|m_down2, m_fireA|m_up2, m_right, m_left, m_down, m_up };
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end
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7'h3:
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7'h3: // BUBBLES
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begin
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core_name = "BUBBLES ";
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BTN = { m_two_players, m_one_player, m_coin1 | m_coin2, reset };
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JA = ~{ 4'b0000, m_right, m_left, m_down, m_up };
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JB = ~{ 4'b0000, m_right2, m_left2, m_down2, m_up2 };
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end
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7'h4:
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7'h4: // STARGATE
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begin
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core_name = "STARGATE";
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BTN = { m_two_players, m_one_player, m_coin1 | m_coin2, reset };
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JA = ~{ m_fireE, m_up, m_down, m_left | m_right, m_fireD, m_fireC, m_fireB, m_fireA };
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JB = ~{ m_fire2E, m_up2, m_down2, m_left2 | m_right2, m_fire2D, m_fire2C, m_fire2B, m_fire2A };
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end
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7'h5:
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7'h5: // ALIENAR
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begin
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core_name = "ALIENAR ";
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BTN = { m_one_player, m_two_players, m_coin1 | m_coin2, reset };
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JA = ~{ 1'b0, 1'b0, m_fireB, m_fireA, m_right, m_left, m_down, m_up };
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JB = ~{ 1'b0, 1'b0, m_fire2B, m_fire2A, m_right2, m_left2, m_down2, m_up2 };
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end
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7'h6:
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7'h6: // SINISTAR
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begin
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core_name = "SINISTAR";
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sinistar = 1;
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orientation = 2'b01;
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BTN = { m_two_players, m_one_player, m_coin1 | m_coin2, reset };
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@ -181,10 +174,10 @@ wire [7:0] key_code;
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wire key_strobe;
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user_io #(
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.STRLEN(8+($size(CONF_STR)>>3)))
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.STRLEN($size(CONF_STR)>>3))
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user_io(
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.clk_sys ( clk_sys ),
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.conf_str ( {core_name, CONF_STR} ),
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.conf_str ( CONF_STR ),
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.SPI_CLK ( SPI_SCK ),
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.SPI_SS_IO ( CONF_DATA0 ),
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.SPI_MISO ( SPI_DO ),
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@ -274,7 +267,7 @@ wire [17:1] sdram_addr = ~romcs ? {1'b0, mem_addr[16], ~mem_addr[16] & mem_addr[
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// IOCTL address to SDRAM address:
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// D000-D3FF -> 1CC00-1CFFF (CMOS), otherwise direct mapping
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wire [22:0] downl_addr = (ioctl_addr[22:10] == { 7'h0, 4'hD, 2'b00 }) ? { 1'b1, 4'hC, 2'b11, ioctl_addr[9:0] } : ioctl_addr;
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wire [22:0] downl_addr = (ioctl_addr[22:10] == { 7'h0, 4'hD, 2'b00 }) ? { 1'b1, 4'hC, 2'b11, ioctl_addr[9:0] } : ioctl_addr[22:0];
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always @(posedge clk_mem) begin
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reg ioctl_wr_last = 0;
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