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MappyHardware: port works

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1 core for all: Mappy, Motos, Tower Of Druaga, Dig Dug II
This commit is contained in:
Gyorgy Szombathelyi 2019-12-18 23:24:25 +01:00
parent cd088fa8f5
commit f47f302c20
26 changed files with 7213 additions and 0 deletions
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Arcade_MiST/Mappy Hardware/DigDugII_MiST/Release/DIGDUG2.ROM
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Arcade_MiST/Mappy Hardware/Mappy_MiST/Release/MAPPY.ROM
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Arcade_MiST/Mappy Hardware/Motos_MiST/Release/MOTOS.ROM
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Arcade_MiST/Mappy Hardware/README.txt Normal file
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The Tower of Druaga/Mappy/Motos/DigDug II to Mist FPGA by Slingshot
Appropriate ROMs are required at the root of the SD Card:
DRUAGA.ROM
MAPPY.ROM
MOTOS.ROM
DIGDUG2.ROM
---------------------------------------------------------------------------------
--
-- Arcade: The Tower of Druaga port to MiSTer by MiSTer-X
-- 25 September 2019
--
---------------------------------------------------------------------------------
-- FPGA Druaga for XILINX Spartan-3
--------------------------------------
-- Copyright (c) 2007 MiSTer-X
---------------------------------------------------------------------------------
-- Cycle-Accurate 6809 Core
-- Revision 1.0 - 13th August 2016
---------------------------------------------------
-- Copyright (c) 2016, Greg Miller
---------------------------------------------------------------------------------
--
--
-- Keyboard inputs :
--
-- F2 : Coin + Start 2 players
-- F1 : Coin + Start 1 player
-- UP,DOWN,LEFT,RIGHT arrows : Movements
-- SPACE : Trig1
-- CTRL : Trig2
--
-- MAME/IPAC/JPAC Style Keyboard inputs:
-- 5 : Coin 1
-- 6 : Coin 2
-- 1 : Start 1 Player
-- 2 : Start 2 Players
-- R,F,D,G : Player 2 Movements
-- A : Player 2 Trig1
-- S : Player 2 Trig2
--
-- Joystick support.
--
--
-- FIXED: Video timing.
--
---------------------------------------------------------------------------------
*** Attention ***
ROM is not included. In order to use this arcade, you need to provide a correct ROM file.
Find this zip file somewhere. You need to find the file exactly as required.
Do not rename other zip files even if they also represent the same game - they are not compatible!
The name of zip is taken from M.A.M.E. project, so you can get more info about
hashes and contained files there.
To generate the ROM using Windows:
1) Copy the zip into "releases" directory
2) Execute bat file - it will show the name of zip file containing required files.
3) Put required zip into the same directory and execute the bat again.
4) If everything will go without errors or warnings, then you will get the a.*.rom file.
5) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using Linux/MacOS:
1) Copy the zip into "releases" directory
2) Execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file
To generate the ROM using MiSTer:
1) scp "releases" directory along with the zip file onto MiSTer:/media/fat/
2) Using OSD execute build_rom.sh
3) Copy generated a.*.rom into root of SD card along with the Arcade-*.rbf file

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Arcade_MiST/Mappy Hardware/TheTowerofDruaga.qpf Normal file
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DATE = "19:48:06 May 24, 2017"
QUARTUS_VERSION = "16.0.2"
# Revisions
PROJECT_REVISION = "TheTowerofDruaga"

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Arcade_MiST/Mappy Hardware/TheTowerofDruaga.qsf Normal file
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2014 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
# Date created = 19:13:36 October 04, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# TheTowerofDruaga_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.0.2
set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:48:06 MAY 24,2017"
set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:rtl/build_id.tcl"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
# Pin & Location Assignments
# ==========================
set_location_assignment PIN_7 -to LED
set_location_assignment PIN_54 -to CLOCK_27
set_location_assignment PIN_144 -to VGA_R[5]
set_location_assignment PIN_143 -to VGA_R[4]
set_location_assignment PIN_142 -to VGA_R[3]
set_location_assignment PIN_141 -to VGA_R[2]
set_location_assignment PIN_137 -to VGA_R[1]
set_location_assignment PIN_135 -to VGA_R[0]
set_location_assignment PIN_133 -to VGA_B[5]
set_location_assignment PIN_132 -to VGA_B[4]
set_location_assignment PIN_125 -to VGA_B[3]
set_location_assignment PIN_121 -to VGA_B[2]
set_location_assignment PIN_120 -to VGA_B[1]
set_location_assignment PIN_115 -to VGA_B[0]
set_location_assignment PIN_114 -to VGA_G[5]
set_location_assignment PIN_113 -to VGA_G[4]
set_location_assignment PIN_112 -to VGA_G[3]
set_location_assignment PIN_111 -to VGA_G[2]
set_location_assignment PIN_110 -to VGA_G[1]
set_location_assignment PIN_106 -to VGA_G[0]
set_location_assignment PIN_136 -to VGA_VS
set_location_assignment PIN_119 -to VGA_HS
set_location_assignment PIN_65 -to AUDIO_L
set_location_assignment PIN_80 -to AUDIO_R
set_location_assignment PIN_105 -to SPI_DO
set_location_assignment PIN_88 -to SPI_DI
set_location_assignment PIN_126 -to SPI_SCK
set_location_assignment PIN_127 -to SPI_SS2
set_location_assignment PIN_91 -to SPI_SS3
set_location_assignment PIN_90 -to SPI_SS4
set_location_assignment PIN_13 -to CONF_DATA0
set_location_assignment PIN_49 -to SDRAM_A[0]
set_location_assignment PIN_44 -to SDRAM_A[1]
set_location_assignment PIN_42 -to SDRAM_A[2]
set_location_assignment PIN_39 -to SDRAM_A[3]
set_location_assignment PIN_4 -to SDRAM_A[4]
set_location_assignment PIN_6 -to SDRAM_A[5]
set_location_assignment PIN_8 -to SDRAM_A[6]
set_location_assignment PIN_10 -to SDRAM_A[7]
set_location_assignment PIN_11 -to SDRAM_A[8]
set_location_assignment PIN_28 -to SDRAM_A[9]
set_location_assignment PIN_50 -to SDRAM_A[10]
set_location_assignment PIN_30 -to SDRAM_A[11]
set_location_assignment PIN_32 -to SDRAM_A[12]
set_location_assignment PIN_83 -to SDRAM_DQ[0]
set_location_assignment PIN_79 -to SDRAM_DQ[1]
set_location_assignment PIN_77 -to SDRAM_DQ[2]
set_location_assignment PIN_76 -to SDRAM_DQ[3]
set_location_assignment PIN_72 -to SDRAM_DQ[4]
set_location_assignment PIN_71 -to SDRAM_DQ[5]
set_location_assignment PIN_69 -to SDRAM_DQ[6]
set_location_assignment PIN_68 -to SDRAM_DQ[7]
set_location_assignment PIN_86 -to SDRAM_DQ[8]
set_location_assignment PIN_87 -to SDRAM_DQ[9]
set_location_assignment PIN_98 -to SDRAM_DQ[10]
set_location_assignment PIN_99 -to SDRAM_DQ[11]
set_location_assignment PIN_100 -to SDRAM_DQ[12]
set_location_assignment PIN_101 -to SDRAM_DQ[13]
set_location_assignment PIN_103 -to SDRAM_DQ[14]
set_location_assignment PIN_104 -to SDRAM_DQ[15]
set_location_assignment PIN_58 -to SDRAM_BA[0]
set_location_assignment PIN_51 -to SDRAM_BA[1]
set_location_assignment PIN_85 -to SDRAM_DQMH
set_location_assignment PIN_67 -to SDRAM_DQML
set_location_assignment PIN_60 -to SDRAM_nRAS
set_location_assignment PIN_64 -to SDRAM_nCAS
set_location_assignment PIN_66 -to SDRAM_nWE
set_location_assignment PIN_59 -to SDRAM_nCS
set_location_assignment PIN_33 -to SDRAM_CKE
set_location_assignment PIN_43 -to SDRAM_CLK
set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[*]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_HS
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
# Classic Timing Assignments
# ==========================
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name TOP_LEVEL_ENTITY TheTowerofDruaga_mist
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
# Assembler Assignments
# =====================
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
set_global_assignment -name GENERATE_RBF_FILE ON
# SignalTap II Assignments
# ========================
set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/druaga.stp
# Power Estimation Assignments
# ============================
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
# Advanced I/O Timing Assignments
# ===============================
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
# -----------------------------------
# start ENTITY(TheTowerofDruaga_mist)
# start DESIGN_PARTITION(Top)
# ---------------------------
# Incremental Compilation Assignments
# ===================================
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
# end DESIGN_PARTITION(Top)
# -------------------------
# end ENTITY(TheTowerofDruaga_mist)
# ---------------------------------
set_global_assignment -name SYSTEMVERILOG_FILE rtl/TheTowerofDruaga_mist.sv
set_global_assignment -name VERILOG_FILE rtl/fpga_druaga.v
set_global_assignment -name VERILOG_FILE rtl/druaga_video.v
set_global_assignment -name VERILOG_FILE rtl/druaga_sprite.v
set_global_assignment -name VERILOG_FILE rtl/wsg.v
set_global_assignment -name VERILOG_FILE rtl/ioctrl.v
set_global_assignment -name VERILOG_FILE rtl/hvgen.v
set_global_assignment -name VHDL_FILE rtl/dpram.vhd
set_global_assignment -name VERILOG_FILE rtl/mc6809/mc6809i.v
set_global_assignment -name VERILOG_FILE rtl/mc6809/mc6809.v
set_global_assignment -name VERILOG_FILE rtl/pll.v
set_global_assignment -name SYSTEMVERILOG_FILE rtl/sdram.sv
set_global_assignment -name QIP_FILE ../../common/mist/mist.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

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Arcade_MiST/Mappy Hardware/TheTowerofDruaga.sdc Normal file
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## Generated SDC file "vectrex_MiST.out.sdc"
## Copyright (C) 1991-2013 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 13.1.0 Build 162 10/23/2013 SJ Web Edition"
## DATE "Sun Jun 24 12:53:00 2018"
##
## DEVICE "EP3C25E144C8"
##
# Clock constraints
# Automatically constrain PLL and other generated clocks
derive_pll_clocks -create_base_clocks
# Automatically calculate clock uncertainty to jitter and other effects.
derive_clock_uncertainty
# tsu/th constraints
# tco constraints
# tpd constraints
#**************************************************************
# Time Information
#**************************************************************
set_time_format -unit ns -decimal_places 3
#**************************************************************
# Create Clock
#**************************************************************
create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
set sys_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
set sdram_clk "pll|altpll_component|auto_generated|pll1|clk[0]"
#**************************************************************
# Create Generated Clock
#**************************************************************
#**************************************************************
# Set Clock Latency
#**************************************************************
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
#**************************************************************
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock_fall -clock [get_clocks {CLOCK_27}] 1.000 [get_ports {CLOCK_27}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {CONF_DATA0}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DI}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SCK}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS2}]
set_input_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_SS3}]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 6.6 [get_ports SDRAM_DQ[*]]
set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min 3.5 [get_ports SDRAM_DQ[*]]
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock_fall -clock [get_clocks {SPI_SCK}] 1.000 [get_ports {SPI_DO}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_L}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {AUDIO_R}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {LED}]
set_output_delay -add_delay -clock_fall -clock [get_clocks $sys_clk] 1.000 [get_ports {VGA_*}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
#**************************************************************
# Set Clock Groups
#**************************************************************
set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
#**************************************************************
# Set False Path
#**************************************************************
#**************************************************************
# Set Multicycle Path
#**************************************************************
set_multicycle_path -to {VGA_*[*]} -setup 2
set_multicycle_path -to {VGA_*[*]} -hold 1
#**************************************************************
# Set Maximum Delay
#**************************************************************
#**************************************************************
# Set Minimum Delay
#**************************************************************
#**************************************************************
# Set Input Transition
#**************************************************************

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Arcade_MiST/Mappy Hardware/TheTowerofDruaga_MiST/Release/DRUAGA.ROM
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Arcade_MiST/Mappy Hardware/rtl/TheTowerofDruaga_mist.sv Normal file
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module TheTowerofDruaga_mist (
output LED,
output [5:0] VGA_R,
output [5:0] VGA_G,
output [5:0] VGA_B,
output VGA_HS,
output VGA_VS,
output AUDIO_L,
output AUDIO_R,
input SPI_SCK,
output SPI_DO,
input SPI_DI,
input SPI_SS2,
input SPI_SS3,
input CONF_DATA0,
input CLOCK_27,
output [12:0] SDRAM_A,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nWE,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nCS,
output [1:0] SDRAM_BA,
output SDRAM_CLK,
output SDRAM_CKE
);
// Uncomment one of these to load the default ROM:
`define CORE_NAME "DRUAGA"
//`define CORE_NAME "MAPPY"
//`define CORE_NAME "MOTOS"
//`define CORE_NAME "DIGDUG2"
`include "rtl\build_id.v"
localparam CONF_STR = {
`CORE_NAME,";ROM;",
"O2,Rotate Controls,Off,On;",
"O34,Scanlines,Off,25%,50%,75%;",
"O5,Blend,Off,On;",
"T0,Reset;",
"V,v1.00.",`BUILD_DATE
};
assign LED = ~ioctl_downl;
assign AUDIO_R = AUDIO_L;
assign SDRAM_CLK = clock_48;
assign SDRAM_CKE = 1;
wire clock_48, clock_6, pll_locked;
pll pll(
.inclk0(CLOCK_27),
.c0(clock_48),//49.147727
.c1(clock_6),
.locked(pll_locked)
);
wire [31:0] status;
wire [1:0] buttons;
wire [1:0] switches;
wire [7:0] joystick_0;
wire [7:0] joystick_1;
wire scandoublerD;
wire ypbpr;
wire [7:0] audio;
wire hs, vs;
wire hb, vb;
wire blankn = ~(hb | vb);
wire [2:0] r, g;
wire [1:0] b;
wire [14:0] rom_addr;
wire [15:0] rom_do;
wire [12:0] snd_addr;
wire [15:0] snd_do;
wire ioctl_downl;
wire [7:0] ioctl_index;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_dout;
wire key_strobe;
wire key_pressed;
wire [7:0] key_code;
/*
ROM map
00000-07FFF cpu0 32k 3.1d+1.1b (+2.1c in Mappy)
08000-0BFFF spchip0 16k 6.3m
0C000-0FFFF spchip1 16k 7.3m
10000-11FFF cpu1 8k 4.1k
12000-12FFF bgchip 4k 5.3b
13000-133FF spclut 1k 7.5k
13400-134FF bgclut 256b 6.4c
13500-135FF wave 256b 3.3m
13600-1361F palet 32b 5.5b
*/
data_io data_io(
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS2 ( SPI_SS2 ),
.SPI_DI ( SPI_DI ),
.ioctl_download( ioctl_downl ),
.ioctl_index ( ioctl_index ),
.ioctl_wr ( ioctl_wr ),
.ioctl_addr ( ioctl_addr ),
.ioctl_dout ( ioctl_dout )
);
reg port1_req, port2_req;
sdram sdram(
.*,
.init_n ( pll_locked ),
.clk ( clock_48 ),
// port1 used for main CPU
.port1_req ( port1_req ),
.port1_ack ( ),
.port1_a ( ioctl_addr[23:1] ),
.port1_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port1_we ( ioctl_downl ),
.port1_d ( {ioctl_dout, ioctl_dout} ),
.port1_q ( ),
.cpu1_addr ( ioctl_downl ? 15'h7fff : {1'b0, rom_addr[14:1]} ),
.cpu1_q ( rom_do ),
// port2 for sound CPU
.port2_req ( port2_req ),
.port2_ack ( ),
.port2_a ( ioctl_addr[23:1] - 16'h8000 ),
.port2_ds ( {ioctl_addr[0], ~ioctl_addr[0]} ),
.port2_we ( ioctl_downl ),
.port2_d ( {ioctl_dout, ioctl_dout} ),
.port2_q ( ),
.snd_addr ( ioctl_downl ? 15'h7fff : {3'b000, snd_addr[12:1]} ),
.snd_q ( snd_do )
);
always @(posedge clock_48) begin
reg ioctl_wr_last = 0;
ioctl_wr_last <= ioctl_wr;
if (ioctl_downl) begin
if (~ioctl_wr_last && ioctl_wr) begin
port1_req <= ~port1_req;
port2_req <= ~port2_req;
end
end
end
reg reset = 1;
reg rom_loaded = 0;
always @(posedge clock_48) begin
reg ioctl_downlD;
ioctl_downlD <= ioctl_downl;
if (ioctl_downlD & ~ioctl_downl) rom_loaded <= 1;
reset <= status[0] | buttons[1] | ioctl_downl | ~rom_loaded;
end
wire [7:0] DSW0 = 0;//{2'h0,status[7:6],4'h0};
wire [7:0] DSW1 = 0;
wire [7:0] DSW2 = 0;//{4'h0,status[8],3'h0};
wire [5:0] INP0 = { m_bomb, m_fire, m_left, m_down, m_right, m_up};
wire [5:0] INP1 = { m_bomb, m_fire, m_left, m_down, m_right, m_up};
wire [2:0] INP2 = { btn_coin, btn_two_players, btn_one_player };
wire PCLK, PCLK_EN;
wire [8:0] HPOS,VPOS;
fpga_druaga fpga_druaga(
.MCLK(clock_48),
.CLKCPUx2(clock_6),
.RESET(reset),
.SOUT(audio),
.rom_addr(rom_addr),
.rom_data(rom_addr[0] ? rom_do[15:8] : rom_do[7:0]),
.snd_addr(snd_addr),
.snd_data(snd_addr[0] ? snd_do[15:8] : snd_do[7:0]),
.PH(HPOS),
.PV(VPOS),
.PCLK(PCLK),
.PCLK_EN(PCLK_EN),
.POUT({b,g,r}),
.INP0(INP0),
.INP1(INP1),
.INP2(INP2),
.DSW0(DSW0),
.DSW1(DSW1),
.DSW2(DSW2),
.ROMAD(ioctl_addr[16:0]),
.ROMDT(ioctl_dout),
.ROMEN(ioctl_wr)
);
hvgen hvgen(
.MCLK(clock_48),
.HPOS(HPOS),
.VPOS(VPOS),
.PCLK(PCLK),
.PCLK_EN(PCLK_EN),
.HBLK(hb),
.VBLK(vb),
.HSYN(hs),
.VSYN(vs)
);
mist_video #(.COLOR_DEPTH(3), .SD_HCNT_WIDTH(10)) mist_video(
.clk_sys ( clock_48 ),
.SPI_SCK ( SPI_SCK ),
.SPI_SS3 ( SPI_SS3 ),
.SPI_DI ( SPI_DI ),
.R ( blankn ? r : 0 ),
.G ( blankn ? g : 0 ),
.B ( blankn ? {b,b[1]} : 0 ),
.HSync ( hs ),
.VSync ( vs ),
.VGA_R ( VGA_R ),
.VGA_G ( VGA_G ),
.VGA_B ( VGA_B ),
.VGA_VS ( VGA_VS ),
.VGA_HS ( VGA_HS ),
.rotate ( {1'b1,status[2]} ),
.scandoubler_disable( scandoublerD ),
.scanlines ( status[4:3] ),
.blend ( status[5] ),
.ypbpr ( ypbpr )
);
user_io #(.STRLEN(($size(CONF_STR)>>3)))user_io(
.clk_sys (clock_48 ),
.conf_str (CONF_STR ),
.SPI_CLK (SPI_SCK ),
.SPI_SS_IO (CONF_DATA0 ),
.SPI_MISO (SPI_DO ),
.SPI_MOSI (SPI_DI ),
.buttons (buttons ),
.switches (switches ),
.scandoubler_disable (scandoublerD ),
.ypbpr (ypbpr ),
.key_strobe (key_strobe ),
.key_pressed (key_pressed ),
.key_code (key_code ),
.joystick_0 (joystick_0 ),
.joystick_1 (joystick_1 ),
.status (status )
);
dac #(.C_bits(16))dac(
.clk_i(clock_48),
.res_n_i(1),
.dac_i({audio,audio}),
.dac_o(AUDIO_L)
);
// Rotated Normal
wire m_up = ~status[2] ? btn_left | joystick_0[1] | joystick_1[1] : btn_up | joystick_0[3] | joystick_1[3];
wire m_down = ~status[2] ? btn_right | joystick_0[0] | joystick_1[0] : btn_down | joystick_0[2] | joystick_1[2];
wire m_left = ~status[2] ? btn_down | joystick_0[2] | joystick_1[2] : btn_left | joystick_0[1] | joystick_1[1];
wire m_right = ~status[2] ? btn_up | joystick_0[3] | joystick_1[3] : btn_right | joystick_0[0] | joystick_1[0];
wire m_fire = btn_fire1 | joystick_0[4] | joystick_1[4];
wire m_bomb = btn_fire2 | joystick_0[5] | joystick_1[5];
reg btn_one_player = 0;
reg btn_two_players = 0;
reg btn_left = 0;
reg btn_right = 0;
reg btn_down = 0;
reg btn_up = 0;
reg btn_fire1 = 0;
reg btn_fire2 = 0;
//reg btn_fire3 = 0;
reg btn_coin = 0;
always @(posedge clock_48) begin
if(key_strobe) begin
case(key_code)
'h75: btn_up <= key_pressed; // up
'h72: btn_down <= key_pressed; // down
'h6B: btn_left <= key_pressed; // left
'h74: btn_right <= key_pressed; // right
'h76: btn_coin <= key_pressed; // ESC
'h05: btn_one_player <= key_pressed; // F1
'h06: btn_two_players <= key_pressed; // F2
// 'h14: btn_fire3 <= key_pressed; // ctrl
'h11: btn_fire2 <= key_pressed; // alt
'h29: btn_fire1 <= key_pressed; // Space
endcase
end
end
endmodule

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# ================================================================================
#
# Build ID Verilog Module Script
# Jeff Wiencrot - 8/1/2011
#
# Generates a Verilog module that contains a timestamp,
# from the current build. These values are available from the build_date, build_time,
# physical_address, and host_name output ports of the build_id module in the build_id.v
# Verilog source file.
#
# ================================================================================
proc generateBuildID_Verilog {} {
# Get the timestamp (see: http://www.altera.com/support/examples/tcl/tcl-date-time-stamp.html)
set buildDate [ clock format [ clock seconds ] -format %y%m%d ]
set buildTime [ clock format [ clock seconds ] -format %H%M%S ]
# Create a Verilog file for output
set outputFileName "rtl/build_id.v"
set outputFile [open $outputFileName "w"]
# Output the Verilog source
puts $outputFile "`define BUILD_DATE \"$buildDate\""
puts $outputFile "`define BUILD_TIME \"$buildTime\""
close $outputFile
# Send confirmation message to the Messages window
post_message "Generated build identification Verilog module: [pwd]/$outputFileName"
post_message "Date: $buildDate"
post_message "Time: $buildTime"
}
# Comment out this line to prevent the process from automatically executing when the file is sourced:
generateBuildID_Verilog

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-- -----------------------------------------------------------------------
--
-- Syntiac's generic VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
-- http://www.syntiac.com/fpga64.html
--
-- Modified April 2016 by Dar (darfpga@aol.fr)
-- http://darfpga.blogspot.fr
-- Remove address register when writing
--
-- -----------------------------------------------------------------------
--
-- dpram.vhd
--
-- -----------------------------------------------------------------------
--
-- generic ram.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity dpram is
generic (
dWidth : integer := 8;
aWidth : integer := 10
);
port (
clk_a : in std_logic;
we_a : in std_logic := '0';
addr_a : in std_logic_vector((aWidth-1) downto 0);
d_a : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_a : out std_logic_vector((dWidth-1) downto 0);
clk_b : in std_logic;
we_b : in std_logic := '0';
addr_b : in std_logic_vector((aWidth-1) downto 0);
d_b : in std_logic_vector((dWidth-1) downto 0) := (others => '0');
q_b : out std_logic_vector((dWidth-1) downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of dpram is
subtype addressRange is integer range 0 to ((2**aWidth)-1);
type ramDef is array(addressRange) of std_logic_vector((dWidth-1) downto 0);
signal ram: ramDef;
signal addr_a_reg: std_logic_vector((aWidth-1) downto 0);
signal addr_b_reg: std_logic_vector((aWidth-1) downto 0);
begin
-- -----------------------------------------------------------------------
process(clk_a)
begin
if rising_edge(clk_a) then
if we_a = '1' then
ram(to_integer(unsigned(addr_a))) <= d_a;
end if;
q_a <= ram(to_integer(unsigned(addr_a)));
end if;
end process;
process(clk_b)
begin
if rising_edge(clk_b) then
if we_b = '1' then
ram(to_integer(unsigned(addr_b))) <= d_b;
end if;
q_b <= ram(to_integer(unsigned(addr_b)));
end if;
end process;
end architecture;

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/***********************************
FPGA Druaga ( Sprite Part )
Copyright (c) 2007 MiSTer-X
************************************/
module DRUAGA_SPRITE
(
input VCLKx8,
input VCLK_EN,
input [8:0] HPOS,
input [8:0] VPOS,
input oHB,
output [6:0] SPRA_A,
input [23:0] SPRA_D,
output [4:0] SPCOL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire [9:0] CLT1_A;
wire [3:0] CLT1_D;
dpram #(4,10) clut1(.clk_a(VCLKx8), .addr_a(CLT1_A), .q_a(CLT1_D),
.clk_b(VCLKx8), .addr_b(ROMAD[9:0]), .we_b(ROMEN & (ROMAD[16:10]=={1'b1,4'h3,2'b00})), .d_b(ROMDT[3:0]));
wire [13:0] SPCH_A;
wire [15:0] SPCH_D;
dpram #(8,14) spch0(.clk_a(VCLKx8), .addr_a(SPCH_A), .q_a(SPCH_D[15:8]),
.clk_b(VCLKx8), .addr_b(ROMAD[13:0]), .we_b(ROMEN & (ROMAD[16:14]==3'b010)), .d_b(ROMDT));
dpram #(8,14) spch1(.clk_a(VCLKx8), .addr_a(SPCH_A), .q_a(SPCH_D[7:0]),
.clk_b(VCLKx8), .addr_b(ROMAD[13:0]), .we_b(ROMEN & (ROMAD[16:14]==3'b011)), .d_b(ROMDT));
reg lbufr = 1'b0; // 0/1
reg [5:0] loop = 6'h0; // 0~32
reg [4:0] lpcn = 5'h0; // 0~31
reg [4:0] xf, yf; // 0~31
reg [8:0] sx; // 0~511
reg [4:0] sy; // 0~31
reg [5:0] pn; // 0x00~0x3F
reg [8:0] vposl; // 0~511
reg [6:0] nProc = 7'h0; // 0~64
// sprite registers access
reg bLoad = 1'b0; // 0/1
wire [7:0] spriteram = SPRA_D[7:0];
wire [7:0] spriteram_2 = SPRA_D[15:8];
wire [7:0] spriteram_3 = SPRA_D[23:16];
assign SPRA_A = {nProc[5:0],bLoad};
// laster hit check
wire [8:0] y = spriteram_2 + 8'h10 + vposl;
wire [8:0] m = { 1'b1, ( 8'hF0 ^ { 3'b000, spriteram_3[3], 4'b0000 } )};
wire bHit = ( ( y & m ) == { 1'b0, m[7:0] } );
reg _sizx;
wire sizx = spriteram_3[2];
wire sizy = spriteram_3[3];
wire [4:0] mskx = { sizx, 4'b1111 };
wire [4:0] msky = { sizy, 4'b1111 };
reg [4:0] _msky = 5'b01111;
reg bKick = 1'b0;
reg [7:0] cno;
wire [4:0] ox = { lpcn ^ xf };
assign SPCH_A = { cno[7:2], (cno[1]|sy[4]), (cno[0]|ox[4]), sy[3], ox[3:2], sy[2:0] };
wire [15:0] SPCO = SPCH_D;
assign CLT1_A = (ox[1:0]==2'b00) ? { pn, SPCO[15], SPCO[11], SPCO[7], SPCO[3] } :
(ox[1:0]==2'b01) ? { pn, SPCO[14], SPCO[10], SPCO[6], SPCO[2] } :
(ox[1:0]==2'b10) ? { pn, SPCO[13], SPCO[ 9], SPCO[5], SPCO[1] } :
{ pn, SPCO[12], SPCO[ 8], SPCO[4], SPCO[0] } ;
wire [3:0] SPCL;
assign SPCOL = {1'b0,SPCL};
LINEBUF_DOUBLE linebuf( VCLKx8, ~oHB & VCLK_EN, lbufr, ~VCLKx8 & VCLK_EN, (loop!=0), sx, CLT1_D, HPOS, SPCL );
always @( posedge VCLKx8 ) begin
if (VCLK_EN) begin
if (~oHB) begin // Horizontal display time
bKick <= 1'b1;
if (loop!=0) begin // rend sprite scanline
sx <= sx+1'd1;
lpcn <= lpcn+1'd1;
loop <= loop-1'd1;
end
else begin // rend sprite scanline init.
if (~nProc[6]) begin
if (~bLoad) begin
if (bHit) begin
cno <= spriteram & { 6'b111111, ~sizy, ~sizx };
xf <= spriteram_3[0] ? mskx : 5'h0;
yf <= spriteram_3[1] ? msky : 5'h0;
sy <= ( 9'h10 + vposl + { 1'b0, spriteram_2 } );
_msky <= msky;
_sizx <= sizx;
bLoad <= 1'b1;
end
else begin
nProc <= nProc+1;
bLoad <= 1'b0;
end
end
else begin
pn <= spriteram[5:0];
sx <= { spriteram_3[0], spriteram_2[7:0] } - 9'h38;
sy <= ( sy & _msky ) ^ yf;
loop <= spriteram_3[1] ? 6'h0 : { _sizx, ~_sizx, 4'h0 };
lpcn <= 6'h0;
nProc <= nProc+1;
bLoad <= 1'b0;
end
end
end
end
else begin // Horizontal blanking time
if (bKick) begin
lbufr <= ~VPOS[0];
vposl <= VPOS+1;
nProc <= 0;
bKick <= 1'b0;
end
end
end
end
endmodule
//----------------------------------------
// Line Buffer ( for Sprite )
//----------------------------------------
module LINEBUF_DOUBLE( CLK, EN, SIDE1, CLK2, WEN, ADRSW, IN, ADRSR, OUT );
input CLK;
input EN;
input SIDE1;
input CLK2;
input WEN;
input [8:0] ADRSW;
input [3:0] IN;
input [8:0] ADRSR;
output [3:0] OUT;
wire [3:0] OUT0, OUT1;
wire SIDE0 = ~SIDE1;
wire OPAQUE = ~( IN[0] & IN[1] & IN[2] & IN[3] );
assign OUT = SIDE1 ? OUT1 : OUT0;
LBUF512 buf0( CLK, SIDE0 ? EN : ( EN & WEN & OPAQUE ), SIDE0 ? ADRSR : ADRSW, SIDE0 ? 4'b1111 : IN, CLK2, EN & SIDE0, ADRSR, OUT0 );
LBUF512 buf1( CLK, SIDE1 ? EN : ( EN & WEN & OPAQUE ), SIDE1 ? ADRSR : ADRSW, SIDE1 ? 4'b1111 : IN, CLK2, EN & SIDE1, ADRSR, OUT1 );
endmodule
module LBUF512
(
input CLKW,
input WEN,
input [8:0] ADRSW,
input [3:0] IN,
input CLKR,
input REN,
input [8:0] ADRSR,
output [3:0] OUT
);
dpram #(4,9) lbuf(.clk_a(CLKW), .we_a(WEN), .addr_a(ADRSW), .d_a(IN),
.clk_b(CLKR), .addr_b(ADRSR), .q_b(OUT));
endmodule

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/***********************************
FPGA Druaga ( Video Part )
Copyright (c) 2007 MiSTer-X
************************************/
module DRUAGA_VIDEO
(
input VCLKx8,
input VCLK,
input VCLK_EN,
input [8:0] PH,
input [8:0] PV,
output PCLK,
output PCLK_EN,
output [7:0] POUT,
output VB,
output [10:0] VRAM_A,
input [15:0] VRAM_D,
output [6:0] SPRA_A,
input [23:0] SPRA_D,
input [8:0] SCROLL,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire [8:0] HPOS = PH-8'd16;
wire [8:0] VPOS = PV;
wire oHB = (PH>=290) & (PH<492);
assign VB = (PV==224);
reg [4:0] PALT_A;
wire [7:0] PALT_D;
wire [7:0] CLT0_A;
wire [3:0] CLT0_D;
wire [11:0] BGCH_A;
wire [7:0] BGCH_D;
//
// BG scroll registers
//
reg [8:0] BGVSCR;
wire [8:0] BGVPOS = BGVSCR + VPOS;
always @(posedge VCLKx8) if (PH == 290) BGVSCR <= SCROLL;
//----------------------------------------
// BG scanline generator
//----------------------------------------
reg [7:0] BGPN;
reg BGH;
wire [5:0] COL = HPOS[8:3];
wire [5:0] ROW = VPOS[8:3];
wire [5:0] ROW2 = ROW + 6'h02;
wire [7:0] CHRC = VRAM_D[7:0];
wire [5:0] BGPL = VRAM_D[13:8];
wire [8:0] HP = HPOS;
wire [8:0] VP = COL[5] ? VPOS : BGVPOS;
wire [11:0] CHRA = { CHRC, ~HP[2], VP[2:0] };
wire [7:0] CHRO = BGCH_D;
always @ ( posedge VCLKx8 ) begin
if (VCLK_EN)
case ( HP[1:0] )
2'b00: begin BGPN <= { BGPL, CHRO[7], CHRO[3] }; BGH <= VRAM_D[14]; end
2'b01: begin BGPN <= { BGPL, CHRO[6], CHRO[2] }; BGH <= VRAM_D[14]; end
2'b10: begin BGPN <= { BGPL, CHRO[5], CHRO[1] }; BGH <= VRAM_D[14]; end
2'b11: begin BGPN <= { BGPL, CHRO[4], CHRO[0] }; BGH <= VRAM_D[14]; end
endcase
end
wire [10:0] VRAMADRS = COL[5] ? { 4'b1111, COL[1:0], ROW[4], ROW2[3:0] } : { VP[8:3], HP[7:3] };
assign CLT0_A = BGPN;
assign BGCH_A = CHRA;
assign VRAM_A = VRAMADRS;
wire BGHI = BGH & (CLT0_D!=4'd15);
wire [4:0] BGCOL = { 1'b1, CLT0_D };
//----------------------------------------
// Sprite scanline generator
//----------------------------------------
wire [4:0] SPCOL;
DRUAGA_SPRITE spr
(
VCLKx8, VCLK_EN,
HPOS, VPOS, oHB,
SPRA_A, SPRA_D,
SPCOL,
ROMAD,ROMDT,ROMEN
);
//----------------------------------------
// Color mixer & Final output
//----------------------------------------
always @(posedge VCLKx8) if (VCLK_EN) PALT_A <= BGHI ? BGCOL : ((SPCOL[3:0]==4'd15) ? BGCOL : SPCOL );
assign POUT = oHB ? 8'd0 : PALT_D;
assign PCLK = VCLK;
assign PCLK_EN = VCLK_EN;
//----------------------------------------
// ROMs
//----------------------------------------
dpram #(8,12) bgchr(.clk_a(VCLKx8), .addr_a(BGCH_A), .q_a(BGCH_D),
.clk_b(VCLKx8), .addr_b(ROMAD[11:0]), .we_b(ROMEN & (ROMAD[16:12]=={1'b1,4'h2})), .d_b(ROMDT));
dpram #(4,8) clut0(.clk_a(VCLKx8), .addr_a(CLT0_A^8'h03), .q_a(CLT0_D),
.clk_b(VCLKx8), .addr_b(ROMAD[7:0]), .we_b(ROMEN & (ROMAD[16:8]=={1'b1,8'h34})), .d_b(ROMDT[3:0]));
dpram #(8,5) pelet(.clk_a(VCLKx8), .addr_a(PALT_A), .q_a(PALT_D),
.clk_b(VCLKx8), .addr_b(ROMAD[4:0]), .we_b(ROMEN & (ROMAD[16:5]=={1'b1,8'h36,3'b000})), .d_b(ROMDT));
endmodule

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/***********************************
FPGA Druaga ( Top module )
Copyright (c) 2007 MiSTer-X
Conversion to clock-enable:
(c) 2019 Slingshot
************************************/
module fpga_druaga
(
input RESET, // RESET
input MCLK, // MasterClock: 49.125MHz
input CLKCPUx2, // CPU clock x 2: MCLK/8
input [8:0] PH, // Screen H
input [8:0] PV, // Screen V
output PCLK, // Pixel Clock
output PCLK_EN,
output [7:0] POUT, // Pixel Color
output [7:0] SOUT, // Sound Out
output [14:0] rom_addr,
input [7:0] rom_data,
output [12:0] snd_addr,
input [7:0] snd_data,
input [5:0] INP0, // 1P {B2,B1,L,D,R,U}
input [5:0] INP1, // 2P {B2,B1,L,D,R,U}
input [2:0] INP2, // {Coin,Start2P,Start1P}
input [7:0] DSW0, // DIPSWs (Active Logic)
input [7:0] DSW1,
input [7:0] DSW2,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
// Clock Generator
reg [4:0] CLKS;
wire VCLK_x8 = MCLK;
wire VCLK_x1 = CLKS[2];
wire VCLK_EN = CLKS[2:0] == 3'b011;
always @( posedge MCLK ) CLKS <= CLKS+1'd1;
// Main-CPU Interface
wire MCPU_CLK = CLKCPUx2;
wire [15:0] MCPU_ADRS;
wire MCPU_VMA;
wire MCPU_RW;
wire MCPU_WE = ( ~MCPU_RW );
//wire MCPU_RE = ( MCPU_RW );
wire [7:0] MCPU_DO;
wire [7:0] MCPU_DI;
// Sub-CPU Interface
wire SCPU_CLK = CLKCPUx2;
wire [15:0] SCPU_ADRS;
wire SCPU_VMA;
wire SCPU_RW;
wire SCPU_WE = ( ~SCPU_RW );
//wire SCPU_RE = ( SCPU_RW );
wire [7:0] SCPU_DO;
wire [7:0] SCPU_DI;
// I/O Interface
wire MCPU_CS_IO, SCPU_WE_WSG;
wire [7:0] IO_O;
wire [10:0] vram_a;
wire [15:0] vram_d;
wire [6:0] spra_a;
wire [23:0] spra_d;
MEMS mems
(
MCLK,
CLKCPUx2,
rom_addr, rom_data,
snd_addr, snd_data,
MCPU_ADRS, MCPU_VMA, MCPU_WE, MCPU_DO, MCPU_DI, MCPU_CS_IO, IO_O,
SCPU_ADRS, SCPU_VMA, SCPU_WE, SCPU_DO, SCPU_DI, SCPU_WE_WSG,
vram_a,vram_d,
spra_a,spra_d,
ROMAD,ROMDT,ROMEN
);
// Control Registers
wire oVB;
wire [7:0] SCROLL;
wire MCPU_IRQ, MCPU_IRQEN;
wire SCPU_IRQ, SCPU_IRQEN;
wire SCPU_RESET, IO_RESET;
wire PSG_ENABLE;
REGS regs
(
CLKCPUx2, RESET, oVB,
MCPU_ADRS, MCPU_VMA, MCPU_WE,
SCPU_ADRS, SCPU_VMA, SCPU_WE,
SCROLL,
MCPU_IRQ, MCPU_IRQEN,
SCPU_IRQ, SCPU_IRQEN,
SCPU_RESET, IO_RESET,
PSG_ENABLE
);
// I/O Controler
wire IsMOTOS;
IOCTRL ioctrl(
CLKCPUx2, oVB, IO_RESET, MCPU_CS_IO, MCPU_WE, MCPU_ADRS[5:0],
MCPU_DO,
IO_O,
{INP1,INP0},INP2,
{DSW2,DSW1,DSW0},
IsMOTOS
);
// Video Core
wire [7:0] oPOUT;
DRUAGA_VIDEO video
(
.VCLKx8(VCLK_x8),.VCLK(VCLK_x1),
.VCLK_EN(VCLK_EN),
.PH(PH),.PV(PV),
.PCLK(PCLK),.PCLK_EN(PCLK_EN),.POUT(oPOUT),.VB(oVB),
.VRAM_A(vram_a), .VRAM_D(vram_d),
.SPRA_A(spra_a), .SPRA_D(spra_d),
.SCROLL({1'b0,SCROLL}),
.ROMAD(ROMAD),.ROMDT(ROMDT),.ROMEN(ROMEN)
);
assign POUT = (IsMOTOS & (PV==0)) ? 8'h0 : oPOUT;
// MainCPU
cpucore main_cpu
(
.clk(MCPU_CLK),
.rst(RESET),
.rw(MCPU_RW),
.vma(MCPU_VMA),
.address(MCPU_ADRS),
.data_in(MCPU_DI),
.data_out(MCPU_DO),
.halt(1'b0),
.hold(1'b0),
.irq(MCPU_IRQ),
.firq(1'b0),
.nmi(1'b0)
);
// SubCPU
cpucore sub_cpu
(
.clk(SCPU_CLK),
.rst(SCPU_RESET),
.rw(SCPU_RW),
.vma(SCPU_VMA),
.address(SCPU_ADRS),
.data_in(SCPU_DI),
.data_out(SCPU_DO),
.halt(1'b0),
.hold(1'b0),
.irq(SCPU_IRQ),
.firq(1'b0),
.nmi(1'b0)
);
// SOUND
wire WAVE_CLK;
wire [7:0] WAVE_AD;
wire [3:0] WAVE_DT;
dpram #(4,8) wsgwv(.clk_a(MCLK), .addr_a(WAVE_AD), .q_a(WAVE_DT),
.clk_b(MCLK), .addr_b(ROMAD[7:0]), .we_b(ROMEN & (ROMAD[16:8]=={1'b1,8'h35})), .d_b(ROMDT[3:0]));
WSG_8CH wsg(
.MCLK(MCLK),
.ADDR(SCPU_ADRS[5:0]),
.DATA(SCPU_DO),
.WE(SCPU_WE_WSG),
.SND_ENABLE(PSG_ENABLE),
.WAVE_CLK(WAVE_CLK),
.WAVE_AD(WAVE_AD),
.WAVE_DT(WAVE_DT),
.SOUT(SOUT)
);
endmodule
module MEMS
(
input MCLK,
input CPUCLKx2,
output [14:0] rom_addr,
input [7:0] rom_data,
output [12:0] snd_addr,
input [7:0] snd_data,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [7:0] MCPU_DO,
output [7:0] MCPU_DI,
output IO_CS,
input [7:0] IO_O,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
input [7:0] SCPU_DO,
output [7:0] SCPU_DI,
output SCPU_WSG_WE,
input [10:0] vram_a,
output [15:0] vram_d,
input [6:0] spra_a,
output [23:0] spra_d,
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
wire [7:0] mrom_d, srom_d;
//DLROM #(15,8) mcpui( CPUCLKx2, MCPU_ADRS[14:0], mrom_d, ROMCL,ROMAD[14:0],ROMDT,ROMEN & (ROMAD[16:15]==2'b0_0));
assign rom_addr = MCPU_ADRS[14:0];
assign mrom_d = rom_data;
assign snd_addr = SCPU_ADRS[12:0];
assign srom_d = snd_data;
//dpram #(8,13) scpui(.clk_a(CPUCLKx2), .addr_a(SCPU_ADRS[12:0]), .q_a(srom_d),
// .clk_b(MCLK), .addr_b(ROMAD[12:0]), .we_b(ROMEN & (ROMAD[16:13]==4'b1_000)), .d_b(ROMDT));
wire mram_cs0 = ( MCPU_ADRS[15:11] == 5'b00000 ) & MCPU_VMA; // $0000-$07FF
wire mram_cs1 = ( MCPU_ADRS[15:11] == 5'b00001 ) & MCPU_VMA; // $0800-$0FFF
wire mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00010 ) & MCPU_VMA; // $1000-$17FF
wire mram_cs3 = ( MCPU_ADRS[15:11] == 5'b00011 ) & MCPU_VMA; // $1800-$1FFF
wire mram_cs4 = ( MCPU_ADRS[15:11] == 5'b00100 ) & MCPU_VMA; // $2000-$27FF
wire mram_cs5 = ( MCPU_ADRS[15:10] == 6'b010000 ) & MCPU_VMA; // $4000-$43FF
assign IO_CS = ( MCPU_ADRS[15:11] == 5'b01001 ) & MCPU_VMA; // $4800-$4FFF
wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF
wire mram_w0 = ( mram_cs0 & MCPU_WE );
wire mram_w1 = ( mram_cs1 & MCPU_WE );
wire mram_w2 = ( mram_cs2 & MCPU_WE );
wire mram_w3 = ( mram_cs3 & MCPU_WE );
wire mram_w4 = ( mram_cs4 & MCPU_WE );
wire mram_w5 = ( mram_cs5 & MCPU_WE );
wire [7:0] mram_o0, mram_o1, mram_o2, mram_o3, mram_o4, mram_o5;
assign MCPU_DI = mram_cs0 ? mram_o0 :
mram_cs1 ? mram_o1 :
mram_cs2 ? mram_o2 :
mram_cs3 ? mram_o3 :
mram_cs4 ? mram_o4 :
mram_cs5 ? mram_o5 :
mrom_cs ? mrom_d :
IO_CS ? IO_O :
8'h0;
wire [10:0] mram_ad = MCPU_ADRS[10:0];
dpram #(8,11) main_ram0( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o0), .we_a(mram_w0), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[ 7:0]));
dpram #(8,11) main_ram1( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o1), .we_a(mram_w1), .clk_b(MCLK), .addr_b(vram_a), .q_b(vram_d[15:8]));
dpram #(8,11) main_ram2( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o2), .we_a(mram_w2), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[ 7: 0]));
dpram #(8,11) main_ram3( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o3), .we_a(mram_w3), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[15: 8]));
dpram #(8,11) main_ram4( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o4), .we_a(mram_w4), .clk_b(MCLK), .addr_b({ 4'b1111, spra_a }), .q_b(spra_d[23:16]));
// (SCPU ADRS)
wire SCPU_CS_SREG = ( ( SCPU_ADRS[15:13] == 3'b000 ) & ( SCPU_ADRS[9:6] == 4'b0000 ) ) & SCPU_VMA;
wire srom_cs = ( SCPU_ADRS[15:13] == 3'b111 ) & SCPU_VMA; // $E000-$FFFF
wire sram_cs0 = (~SCPU_CS_SREG) & (~srom_cs) & SCPU_VMA; // $0000-$03FF
wire [7:0] sram_o0;
assign SCPU_DI = sram_cs0 ? sram_o0 :
srom_cs ? srom_d :
8'h0;
assign SCPU_WSG_WE = SCPU_CS_SREG & SCPU_WE;
dpram #(8,11) share_ram( .clk_a(CPUCLKx2), .addr_a(mram_ad), .d_a(MCPU_DO), .q_a(mram_o5), .we_a(mram_w5),
.clk_b(CPUCLKx2), .addr_b(SCPU_ADRS[9:0]), .d_b(SCPU_DO), .q_b(sram_o0), .we_b(sram_cs0 & SCPU_WE) );
endmodule
module REGS
(
input MCPU_CLK,
input RESET,
input VBLANK,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
output reg [7:0] SCROLL,
output MCPU_IRQ,
output reg MCPU_IRQEN,
output SCPU_IRQ,
output reg SCPU_IRQEN,
output SCPU_RESET,
output IO_RESET,
output reg PSG_ENABLE
);
// BG Scroll Register
wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE );
always @ ( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) SCROLL <= 8'h0;
else if ( MCPU_SCRWE ) SCROLL <= MCPU_ADRS[10:3];
end
// MainCPU IRQ Generator
wire MCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000001 ) & MCPU_VMA & MCPU_WE );
//wire MCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000001 ) & SCPU_VMA & SCPU_WE );
assign MCPU_IRQ = MCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
MCPU_IRQEN <= 1'b0;
end
else begin
if ( MCPU_IRQWE ) MCPU_IRQEN <= MCPU_ADRS[0];
// if ( MCPU_IRQWES ) MCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU IRQ Generator
wire SCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000000 ) & MCPU_VMA & MCPU_WE );
wire SCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000000 ) & SCPU_VMA & SCPU_WE );
assign SCPU_IRQ = SCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_IRQEN <= 1'b0;
end
else begin
if ( SCPU_IRQWE ) SCPU_IRQEN <= MCPU_ADRS[0];
if ( SCPU_IRQWES ) SCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU RESET Control
reg SCPU_RSTf = 1'b0;
wire SCPU_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000101 ) & MCPU_VMA & MCPU_WE );
wire SCPU_RSTWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000101 ) & SCPU_VMA & SCPU_WE );
assign SCPU_RESET = ~SCPU_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_RSTf <= 1'b0;
end
else begin
if ( SCPU_RSTWE ) SCPU_RSTf <= MCPU_ADRS[0];
if ( SCPU_RSTWES ) SCPU_RSTf <= SCPU_ADRS[0];
end
end
// I/O CHIP RESET Control
reg IOCHIP_RSTf = 1'b0;
wire IOCHIP_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000100 ) & MCPU_VMA & MCPU_WE );
assign IO_RESET = ~IOCHIP_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
IOCHIP_RSTf <= 1'b0;
end
else begin
if ( IOCHIP_RSTWE ) IOCHIP_RSTf <= MCPU_ADRS[0];
end
end
// Sound Enable Control
wire PSG_ENAWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000011 ) & MCPU_VMA & MCPU_WE );
wire PSG_ENAWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000011 ) & SCPU_VMA & SCPU_WE );
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
PSG_ENABLE <= 1'b0;
end
else begin
if ( PSG_ENAWE ) PSG_ENABLE <= MCPU_ADRS[0];
if ( PSG_ENAWES ) PSG_ENABLE <= SCPU_ADRS[0];
end
end
endmodule
module cpucore
(
input clk,
input rst,
output rw,
output vma,
output [15:0] address,
input [7:0] data_in,
output [7:0] data_out,
input halt,
input hold,
input irq,
input firq,
input nmi
);
mc6809 cpu
(
.D(data_in),
.DOut(data_out),
.ADDR(address),
.RnW(rw),
// .E(vma),
.nIRQ(~irq),
.nFIRQ(~firq),
.nNMI(~nmi),
.EXTAL(clk),
.nHALT(~halt),
.nRESET(~rst),
.XTAL(1'b0),
.MRDY(1'b1),
.nDMABREQ(1'b1)
);
assign vma = 1;
endmodule

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module hvgen
(
input MCLK,
output [8:0] HPOS,
output [8:0] VPOS,
input PCLK,
input PCLK_EN,
output reg HBLK = 1,
output reg VBLK = 1,
output reg HSYN = 1,
output reg VSYN = 1
);
reg [8:0] hcnt = 0;
reg [8:0] vcnt = 0;
assign HPOS = hcnt;
assign VPOS = vcnt;
always @(posedge MCLK) begin
if (PCLK_EN)
case (hcnt)
1: begin HBLK <= 0; hcnt <= hcnt+1'd1; end
290: begin HBLK <= 1; hcnt <= hcnt+1'd1; end
311: begin HSYN <= 0; hcnt <= hcnt+1'd1; end
342: begin HSYN <= 1; hcnt <= 9'd470; end
511: begin hcnt <= 0;
case (vcnt)
223: begin VBLK <= 1; vcnt <= vcnt+1'd1; end
226: begin VSYN <= 0; vcnt <= vcnt+1'd1; end
233: begin VSYN <= 1; vcnt <= 9'd483; end
511: begin VBLK <= 0; vcnt <= 0; end
default: vcnt <= vcnt+1'd1;
endcase
end
default: hcnt <= hcnt+1'd1;
endcase
end
endmodule

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/****************************************************
FPGA Druaga ( Custom I/O chip emulation part )
Copyright (c) 2007 MiSTer-X
*****************************************************/
module IOCTRL( CLK, UPDATE, RESET, ENABLE, WR, ADRS, IN, OUT, STKTRG12, CSTART12, DIPSW, IsMOTOS );
input CLK;
input UPDATE;
input RESET;
input ENABLE;
input WR;
input [5:0] ADRS;
input [7:0] IN;
output [7:0] OUT;
input [11:0] STKTRG12; // { STKTRG2[5:0], STKSTG1[5:0] }
input [2:0] CSTART12; // { COIN, START2P, START1P }
input [23:0] DIPSW; // { DSW5[3:0] DSW4[3:0] DSW3[3:0], DSW2[3:0], DSW1[3:0], DSW0[3:0] }
output IsMOTOS;
reg [3:0] mema[0:15];
reg [3:0] memb[0:15];
reg [3:0] memc[0:31];
reg [3:0] outr;
reg [7:0] credits;
reg [7:0] credit_add, credit_sub;
reg [9:0] pSTKTRG12;
reg [2:0] pCSTART12;
reg bUpdate;
reg bIOMode = 0;
assign OUT = { 4'b1111, outr };
assign IsMOTOS = bIOMode;
wire [11:0] iSTKTRG12 = ( STKTRG12 ^ pSTKTRG12 ) & STKTRG12;
wire [2:0] iCSTART12 = ( CSTART12 ^ pCSTART12 ) & CSTART12;
wire [3:0] CREDIT_ONES, CREDIT_TENS;
BCDCONV creditsBCD( credits, CREDIT_ONES, CREDIT_TENS );
always @ ( posedge CLK ) begin
if ( ENABLE ) begin
if ( ADRS[5] ) begin
if ( WR ) memc[ADRS[4:0]] <= IN;
outr <= memc[ADRS[4:0]];
end else if ( ADRS[4] ) begin
if ( WR ) memb[ADRS[3:0]] <= IN;
outr <= memb[ADRS[3:0]];
end else begin
if ( WR ) mema[ADRS[3:0]] <= IN;
outr <= mema[ADRS[3:0]];
end
end
if ( RESET ) begin
pCSTART12 <= 0;
pSTKTRG12 <= 0;
bUpdate <= 0;
bIOMode = 0;
credits = 0;
end
else begin
if ( UPDATE & (~bUpdate) ) begin
if ( mema[4'h8] == 4'h8 ) bIOMode = 1'b1; // Is running "Motos" ?
if ( bIOMode ) begin
`include "ioctrl_1.v"
end
else begin
`include "ioctrl_0.v"
end
pCSTART12 <= CSTART12;
pSTKTRG12 <= STKTRG12;
end
bUpdate <= UPDATE;
end
end
endmodule
module add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
case (in)
4'b0000: out <= 4'b0000;
4'b0001: out <= 4'b0001;
4'b0010: out <= 4'b0010;
4'b0011: out <= 4'b0011;
4'b0100: out <= 4'b0100;
4'b0101: out <= 4'b1000;
4'b0110: out <= 4'b1001;
4'b0111: out <= 4'b1010;
4'b1000: out <= 4'b1011;
4'b1001: out <= 4'b1100;
default: out <= 4'b0000;
endcase
endmodule
module BCDCONV(A,ONES,TENS);
input [7:0] A;
output [3:0] ONES, TENS;
wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;
assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
endmodule

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//------------------------------------------
// I/O Chip for "Mappy/Druaga/DigDug2"
//
// Copyright (c) 2007 MiSTer-X
//------------------------------------------
// TODO: DSW2 = DIPSW[23:16]
case ( mema[4'h8] )
4'h1: begin
mema[4'h0] <= 0;
mema[4'h1] <= 0;
mema[4'h2] <= 0;
mema[4'h3] <= 0;
end
4'h3: begin
credit_add = 0;
credit_sub = 0;
if ( iCSTART12[2] & ( credits < 99 ) ) begin
credit_add = 8'h01;
credits = credits + 1'd1;
end
if ( mema[4'h9] == 0 ) begin
if ( ( credits >= 2 ) & iCSTART12[1] ) begin
credit_sub = 8'h02;
credits = credits - 2'd1;
end else if ( ( credits >= 1 ) & iCSTART12[0] ) begin
credit_sub = 8'h01;
credits = credits - 1'd1;
end
end
mema[4'h0] <= credit_add;
mema[4'h1] <= credit_sub;
mema[4'h2] <= CREDIT_TENS;
mema[4'h3] <= CREDIT_ONES;
mema[4'h4] <= STKTRG12[3:0];
mema[4'h5] <= { CSTART12[0], iCSTART12[0], STKTRG12[4], iSTKTRG12[4] };
mema[4'h6] <= STKTRG12[9:6];
mema[4'h7] <= { CSTART12[1], iCSTART12[1], STKTRG12[10], iSTKTRG12[10] };
end
4'h4: begin
mema[4'h0] <= 0;
mema[4'h1] <= 0;
mema[4'h2] <= 0;
mema[4'h3] <= 0;
mema[4'h4] <= 0;
mema[4'h5] <= 0;
mema[4'h6] <= { CSTART12[1], CSTART12[0], 2'b00 };
mema[4'h7] <= { CSTART12[1], CSTART12[0], 2'b00 };
end
4'h5: begin
mema[4'h0] <= 4'h0;
mema[4'h1] <= 4'h8;
mema[4'h2] <= 4'h4;
mema[4'h3] <= 4'h6;
mema[4'h4] <= 4'hE;
mema[4'h5] <= 4'hD;
mema[4'h6] <= 4'h9;
mema[4'h7] <= 4'hD;
end
default: begin end
endcase
case ( memb[4'h8] )
4'h1: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
end
4'h3: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
memb[4'h4] <= 0;
memb[4'h5] <= 0;
memb[4'h6] <= 0;
memb[4'h7] <= 0;
end
4'h4: begin
memb[4'h0] <= DIPSW[11:8];
memb[4'h1] <= DIPSW[3:0];
memb[4'h2] <= DIPSW[7:4];
memb[4'h4] <= DIPSW[15:12];
memb[4'h6] <= DIPSW[7:4];
memb[4'h3] <= 0;
memb[4'h5] <= { DIPSW[3:2], STKTRG12[ 5], iSTKTRG12[ 5] };
memb[4'h7] <= { 2'b00, STKTRG12[11], iSTKTRG12[11] };
end
4'h5: begin
memb[4'h0] <= 4'h0;
memb[4'h1] <= 4'h8;
memb[4'h2] <= 4'h4;
memb[4'h3] <= 4'h6;
memb[4'h4] <= 4'hE;
memb[4'h5] <= 4'hD;
memb[4'h6] <= 4'h9;
memb[4'h7] <= 4'hD;
end
default: begin end
endcase

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//------------------------------------------
// I/O Chip for "Motos"
//
// Copyright (c) 2007 MiSTer-X
//------------------------------------------
// TODO: DSW2 = DIPSW[23:16]
case ( mema[4'h8] )
4'h1: begin
mema[4'h0] <= { 3'b00, CSTART12[2] };
mema[4'h1] <= STKTRG12[3:0];
mema[4'h2] <= STKTRG12[9:6];
mema[4'h3] <= { CSTART12[1], CSTART12[0], STKTRG12[10], STKTRG12[4] };
end
4'h8: begin
mema[4'h0] <= 4'h6;
mema[4'h1] <= 4'h9;
end
default: begin end
endcase
case ( memb[4'h8] )
4'h8: begin
memb[4'h0] <= 4'h6;
memb[4'h1] <= 4'h9;
end
4'h9: begin
memb[4'h0] <= 0;
memb[4'h1] <= 0;
memb[4'h2] <= 0;
memb[4'h3] <= 0;
memb[4'h4] <= 0;
memb[4'h5] <= 0;
memb[4'h6] <= 0;
memb[4'h7] <= 0;
end
default: begin end
endcase

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Arcade_MiST/Mappy Hardware/rtl/mc6809/cpucore.v Normal file
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module cpucore
(
input clk,
input rst,
output rw,
output vma,
output [15:0] address,
input [7:0] data_in,
output [7:0] data_out,
input halt,
input hold,
input irq,
input firq,
input nmi
);
mc6809 cpu
(
.D(data_in),
.DOut(data_out),
.ADDR(address),
.RnW(rw),
.E(vma),
.nIRQ(~irq),
.nFIRQ(~firq),
.nNMI(~nmi),
.EXTAL(clk),
.nHALT(~halt),
.nRESET(~rst),
.XTAL(1'b0),
.MRDY(1'b1),
.nDMABREQ(1'b1)
);
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:11:34 09/23/2016
// Design Name:
// Module Name: mc6809e
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module mc6809(
input [7:0] D,
output [7:0] DOut,
output [15:0] ADDR,
output RnW,
output E,
output Q,
output BS,
output BA,
input nIRQ,
input nFIRQ,
input nNMI,
input EXTAL,
input XTAL,
input nHALT,
input nRESET,
input MRDY,
input nDMABREQ
, output [111:0] RegData
);
reg [1:0] clk_phase=2'b00;
wire CLK;
assign CLK=EXTAL;
wire LIC;
wire BUSY;
wire AVMA;
reg rE;
reg rQ;
assign E = rE;
assign Q = rQ;
mc6809i cpucore(.D(D), .DOut(DOut), .ADDR(ADDR), .RnW(RnW), .E(E), .Q(Q), .BS(BS), .BA(BA), .nIRQ(nIRQ), .nFIRQ(nFIRQ),
.nNMI(nNMI), .AVMA(AVMA), .BUSY(BUSY), .LIC(LIC), .nHALT(nHALT), .nRESET(nRESET), .nDMABREQ(nDMABREQ)
,.RegData(RegData)
);
always @(negedge CLK)
begin
case (clk_phase)
2'b00:
rE <= 0;
2'b01:
rQ <= 1;
2'b10:
rE <= 1;
2'b11:
rQ <= 0;
endcase
if (MRDY == 1'b1)
clk_phase <= clk_phase + 2'b01;
end
endmodule

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module mems
(
input CPUCLKx2,
output [14:0] rom_addr,
input [7:0] rom_data,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [7:0] MCPU_DO,
output [7:0] MCPU_DI,
output IO_CS,
input [7:0] IO_O,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
input [7:0] SCPU_DO,
output [7:0] SCPU_DI,
output SCPU_WSG_WE,
input VCLKx4,
input [10:0] vram_a,
output [15:0] vram_d,
input [6:0] spra_a,
output [23:0] spra_d,
input ROMCL, // Downloaded ROM image
input [16:0] ROMAD,
input [7:0] ROMDT,
input ROMEN
);
//wire [7:0] mrom_d;
wire [7:0] srom_d;
assign rom_addr = MCPU_ADRS[14:0];
//assign mrom_d = rom_data;
scpui_rom scpui_rom(
.clk(CPUCLKx2),
.addr(SCPU_ADRS[12:0]),
.data(srom_d)
);
wire mram_cs0 = ( MCPU_ADRS[15:11] == 5'b00000 ) & MCPU_VMA; // $0000-$07FF
wire mram_cs1 = ( MCPU_ADRS[15:11] == 5'b00001 ) & MCPU_VMA; // $0800-$0FFF
wire mram_cs2 = ( MCPU_ADRS[15:11] == 5'b00010 ) & MCPU_VMA; // $1000-$17FF
wire mram_cs3 = ( MCPU_ADRS[15:11] == 5'b00011 ) & MCPU_VMA; // $1800-$1FFF
wire mram_cs4 = ( MCPU_ADRS[15:11] == 5'b00100 ) & MCPU_VMA; // $2000-$27FF
wire mram_cs5 = ( MCPU_ADRS[15:10] == 6'b010000 ) & MCPU_VMA; // $4000-$43FF
assign IO_CS = ( MCPU_ADRS[15:11] == 5'b01001 ) & MCPU_VMA; // $4800-$4FFF
wire mrom_cs = ( MCPU_ADRS[15] ) & MCPU_VMA; // $8000-$FFFF
wire mram_w0 = ( mram_cs0 & MCPU_WE );
wire mram_w1 = ( mram_cs1 & MCPU_WE );
wire mram_w2 = ( mram_cs2 & MCPU_WE );
wire mram_w3 = ( mram_cs3 & MCPU_WE );
wire mram_w4 = ( mram_cs4 & MCPU_WE );
wire mram_w5 = ( mram_cs5 & MCPU_WE );
wire [7:0] mram_o0, mram_o1, mram_o2, mram_o3, mram_o4, mram_o5;
assign MCPU_DI = mram_cs0 ? mram_o0 :
mram_cs1 ? mram_o1 :
mram_cs2 ? mram_o2 :
mram_cs3 ? mram_o3 :
mram_cs4 ? mram_o4 :
mram_cs5 ? mram_o5 :
mrom_cs ? rom_data ://mrom_d :
IO_CS ? IO_O :
8'h0;
wire [10:0] mram_ad = MCPU_ADRS[10:0];
DPRAM_2048V main_ram0( CPUCLKx2, mram_ad, MCPU_DO, mram_o0, mram_w0, VCLKx4, vram_a, vram_d[7:0] );
DPRAM_2048V main_ram1( CPUCLKx2, mram_ad, MCPU_DO, mram_o1, mram_w1, VCLKx4, vram_a, vram_d[15:8] );
DPRAM_2048V main_ram2( CPUCLKx2, mram_ad, MCPU_DO, mram_o2, mram_w2, VCLKx4, { 4'b1111, spra_a }, spra_d[7:0] );
DPRAM_2048V main_ram3( CPUCLKx2, mram_ad, MCPU_DO, mram_o3, mram_w3, VCLKx4, { 4'b1111, spra_a }, spra_d[15:8] );
DPRAM_2048V main_ram4( CPUCLKx2, mram_ad, MCPU_DO, mram_o4, mram_w4, VCLKx4, { 4'b1111, spra_a }, spra_d[23:16] );
// (SCPU ADRS)
wire SCPU_CS_SREG = ( ( SCPU_ADRS[15:13] == 3'b000 ) & ( SCPU_ADRS[9:6] == 4'b0000 ) ) & SCPU_VMA;
wire srom_cs = ( SCPU_ADRS[15:13] == 3'b111 ) & SCPU_VMA; // $E000-$FFFF
wire sram_cs0 = (~SCPU_CS_SREG) & (~srom_cs) & SCPU_VMA; // $0000-$03FF
wire [7:0] sram_o0;
assign SCPU_DI = sram_cs0 ? sram_o0 :
srom_cs ? srom_d :
8'h0;
assign SCPU_WSG_WE = SCPU_CS_SREG & SCPU_WE;
DPRAM_2048 share_ram
(
CPUCLKx2, mram_ad, MCPU_DO, mram_o5, mram_w5,
CPUCLKx2, { 1'b0, SCPU_ADRS[9:0] }, SCPU_DO, sram_o0, sram_cs0 & SCPU_WE
);
endmodule

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Arcade_MiST/Mappy Hardware/rtl/pll.v Normal file
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// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0,
c1,
locked);
input inclk0;
output c0;
output c1;
output locked;
wire [4:0] sub_wire0;
wire sub_wire2;
wire [0:0] sub_wire6 = 1'h0;
wire [0:0] sub_wire3 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire locked = sub_wire2;
wire c0 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
altpll altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0),
.locked (sub_wire2),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 9,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 9,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 2,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "6.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "6.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON

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module regs
(
input MCPU_CLK,
input RESET,
input VBLANK,
input [15:0] MCPU_ADRS,
input MCPU_VMA,
input MCPU_WE,
input [15:0] SCPU_ADRS,
input SCPU_VMA,
input SCPU_WE,
output reg [7:0] SCROLL,
output MCPU_IRQ,
output reg MCPU_IRQEN,
output SCPU_IRQ,
output reg SCPU_IRQEN,
output SCPU_RESET,
output IO_RESET,
output reg PSG_ENABLE
);
// BG Scroll Register
wire MCPU_SCRWE = ( ( MCPU_ADRS[15:11] == 5'b00111 ) & MCPU_VMA & MCPU_WE );
always @ ( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) SCROLL <= 8'h0;
else if ( MCPU_SCRWE ) SCROLL <= MCPU_ADRS[10:3];
end
// MainCPU IRQ Generator
wire MCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000001 ) & MCPU_VMA & MCPU_WE );
//wire MCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000001 ) & SCPU_VMA & SCPU_WE );
assign MCPU_IRQ = MCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
MCPU_IRQEN <= 1'b0;
end
else begin
if ( MCPU_IRQWE ) MCPU_IRQEN <= MCPU_ADRS[0];
// if ( MCPU_IRQWES ) MCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU IRQ Generator
wire SCPU_IRQWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000000 ) & MCPU_VMA & MCPU_WE );
wire SCPU_IRQWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000000 ) & SCPU_VMA & SCPU_WE );
assign SCPU_IRQ = SCPU_IRQEN & VBLANK;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_IRQEN <= 1'b0;
end
else begin
if ( SCPU_IRQWE ) SCPU_IRQEN <= MCPU_ADRS[0];
if ( SCPU_IRQWES ) SCPU_IRQEN <= SCPU_ADRS[0];
end
end
// SubCPU RESET Control
reg SCPU_RSTf = 1'b0;
wire SCPU_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000101 ) & MCPU_VMA & MCPU_WE );
wire SCPU_RSTWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000101 ) & SCPU_VMA & SCPU_WE );
assign SCPU_RESET = ~SCPU_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
SCPU_RSTf <= 1'b0;
end
else begin
if ( SCPU_RSTWE ) SCPU_RSTf <= MCPU_ADRS[0];
if ( SCPU_RSTWES ) SCPU_RSTf <= SCPU_ADRS[0];
end
end
// I/O CHIP RESET Control
reg IOCHIP_RSTf = 1'b0;
wire IOCHIP_RSTWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000100 ) & MCPU_VMA & MCPU_WE );
assign IO_RESET = ~IOCHIP_RSTf;
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
IOCHIP_RSTf <= 1'b0;
end
else begin
if ( IOCHIP_RSTWE ) IOCHIP_RSTf <= MCPU_ADRS[0];
end
end
// Sound Enable Control
wire PSG_ENAWE = ( ( MCPU_ADRS[15:1] == 15'b010100000000011 ) & MCPU_VMA & MCPU_WE );
wire PSG_ENAWES = ( ( SCPU_ADRS[15:1] == 15'b001000000000011 ) & SCPU_VMA & SCPU_WE );
always @( negedge MCPU_CLK or posedge RESET ) begin
if ( RESET ) begin
PSG_ENABLE <= 1'b0;
end
else begin
if ( PSG_ENAWE ) PSG_ENABLE <= MCPU_ADRS[0];
if ( PSG_ENAWES ) PSG_ENABLE <= SCPU_ADRS[0];
end
end
endmodule

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//
// sdram.v
//
// sdram controller implementation for the MiST board
// https://github.com/mist-devel/mist-board
//
// Copyright (c) 2013 Till Harbaum <till@harbaum.org>
// Copyright (c) 2019 Gyorgy Szombathelyi
//
// This source file is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This source file is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
module sdram (
// interface to the MT48LC16M16 chip
inout reg [15:0] SDRAM_DQ, // 16 bit bidirectional data bus
output reg [12:0] SDRAM_A, // 13 bit multiplexed address bus
output reg SDRAM_DQML, // two byte masks
output reg SDRAM_DQMH, // two byte masks
output reg [1:0] SDRAM_BA, // two banks
output SDRAM_nCS, // a single chip select
output SDRAM_nWE, // write enable
output SDRAM_nRAS, // row address select
output SDRAM_nCAS, // columns address select
// cpu/chipset interface
input init_n, // init signal after FPGA config to initialize RAM
input clk, // sdram clock
input port1_req,
output reg port1_ack,
input port1_we,
input [23:1] port1_a,
input [1:0] port1_ds,
input [15:0] port1_d,
output [15:0] port1_q,
input [15:1] cpu1_addr,
output reg [15:0] cpu1_q,
input port2_req,
output reg port2_ack,
input port2_we,
input [23:1] port2_a,
input [1:0] port2_ds,
input [15:0] port2_d,
output [15:0] port2_q,
input [15:1] snd_addr,
output reg [15:0] snd_q
);
localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 2 cycles@<100MHz
localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8
localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved
localparam CAS_LATENCY = 3'd2; // 2/3 allowed
localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed
localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write
localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH};
// 64ms/8192 rows = 7.8us -> 842 cycles@108MHz
localparam RFRSH_CYCLES = 10'd842;
// ---------------------------------------------------------------------
// ------------------------ cycle state machine ------------------------
// ---------------------------------------------------------------------
/*
SDRAM state machine for 2 bank interleaved access
1 word burst, CL2
cmd issued registered
0 RAS0 cas1
1 ras0
2 CAS0 data1 returned
3 RAS1 cas0
4 ras1
5 CAS1 data0 returned
*/
localparam STATE_RAS0 = 3'd0; // first state in cycle
localparam STATE_RAS1 = 3'd3; // Second ACTIVE command after RAS0 + tRRD (15ns)
localparam STATE_CAS0 = STATE_RAS0 + RASCAS_DELAY; // CAS phase - 3
localparam STATE_CAS1 = STATE_RAS1 + RASCAS_DELAY; // CAS phase - 5
localparam STATE_READ0 = 3'd0; //STATE_CAS0 + CAS_LATENCY + 1'd1; // 7
localparam STATE_READ1 = 3'd3;
localparam STATE_LAST = 3'd5;
reg [2:0] t;
always @(posedge clk) begin
t <= t + 1'd1;
if (t == STATE_LAST) t <= STATE_RAS0;
end
// ---------------------------------------------------------------------
// --------------------------- startup/reset ---------------------------
// ---------------------------------------------------------------------
// wait 1ms (32 8Mhz cycles) after FPGA config is done before going
// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
reg [4:0] reset;
reg init = 1'b1;
always @(posedge clk, negedge init_n) begin
if(!init_n) begin
reset <= 5'h1f;
init <= 1'b1;
end else begin
if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1;
init <= !(reset == 0);
end
end
// ---------------------------------------------------------------------
// ------------------ generate ram control signals ---------------------
// ---------------------------------------------------------------------
// all possible commands
localparam CMD_INHIBIT = 4'b1111;
localparam CMD_NOP = 4'b0111;
localparam CMD_ACTIVE = 4'b0011;
localparam CMD_READ = 4'b0101;
localparam CMD_WRITE = 4'b0100;
localparam CMD_BURST_TERMINATE = 4'b0110;
localparam CMD_PRECHARGE = 4'b0010;
localparam CMD_AUTO_REFRESH = 4'b0001;
localparam CMD_LOAD_MODE = 4'b0000;
reg [3:0] sd_cmd; // current command sent to sd ram
reg [15:0] sd_din;
// drive control signals according to current command
assign SDRAM_nCS = sd_cmd[3];
assign SDRAM_nRAS = sd_cmd[2];
assign SDRAM_nCAS = sd_cmd[1];
assign SDRAM_nWE = sd_cmd[0];
reg [24:1] addr_latch[2];
reg [24:1] addr_latch_next[2];
reg [15:1] addr_last[2];
reg [15:1] addr_last2[2];
reg [15:0] din_latch[2];
reg [1:0] oe_latch;
reg [1:0] we_latch;
reg [1:0] ds[2];
localparam PORT_NONE = 2'd0;
localparam PORT_CPU1 = 2'd1;
localparam PORT_REQ = 2'd2;
localparam PORT_SND = 2'd1;
reg [2:0] next_port[2];
reg [2:0] port[2];
reg refresh;
reg [10:0] refresh_cnt;
wire need_refresh = (refresh_cnt >= RFRSH_CYCLES);
// PORT1: bank 0,1
always @(*) begin
if (refresh) begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end else if (port1_req ^ port1_ack) begin
next_port[0] = PORT_REQ;
addr_latch_next[0] = { 1'b0, port1_a };
end else if (cpu1_addr != addr_last[PORT_CPU1]) begin
next_port[0] = PORT_CPU1;
addr_latch_next[0] = { 9'd0, cpu1_addr };
end else begin
next_port[0] = PORT_NONE;
addr_latch_next[0] = addr_latch[0];
end
end
// PORT2: bank 2,3
always @(*) begin
if (port2_req ^ port2_ack) begin
next_port[1] = PORT_REQ;
addr_latch_next[1] = { 1'b1, port2_a };
end else if (snd_addr != addr_last2[PORT_SND]) begin
next_port[1] = PORT_SND;
addr_latch_next[1] = { 1'b1, 8'd0, snd_addr };
end else begin
next_port[1] = PORT_NONE;
addr_latch_next[1] = addr_latch[1];
end
end
always @(posedge clk) begin
// permanently latch ram data to reduce delays
sd_din <= SDRAM_DQ;
SDRAM_DQ <= 16'bZZZZZZZZZZZZZZZZ;
{ SDRAM_DQMH, SDRAM_DQML } <= 2'b11;
sd_cmd <= CMD_NOP; // default: idle
refresh_cnt <= refresh_cnt + 1'd1;
if(init) begin
// initialization takes place at the end of the reset phase
if(t == STATE_RAS0) begin
if(reset == 15) begin
sd_cmd <= CMD_PRECHARGE;
SDRAM_A[10] <= 1'b1; // precharge all banks
end
if(reset == 10 || reset == 8) begin
sd_cmd <= CMD_AUTO_REFRESH;
end
if(reset == 2) begin
sd_cmd <= CMD_LOAD_MODE;
SDRAM_A <= MODE;
SDRAM_BA <= 2'b00;
end
end
end else begin
// RAS phase
// bank 0,1
if(t == STATE_RAS0) begin
addr_latch[0] <= addr_latch_next[0];
port[0] <= next_port[0];
{ oe_latch[0], we_latch[0] } <= 2'b00;
if (next_port[0] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[0][22:10];
SDRAM_BA <= addr_latch_next[0][24:23];
addr_last[next_port[0]] <= addr_latch_next[0][15:1];
if (next_port[0] == PORT_REQ) begin
{ oe_latch[0], we_latch[0] } <= { ~port1_we, port1_we };
ds[0] <= port1_ds;
din_latch[0] <= port1_d;
end else begin
{ oe_latch[0], we_latch[0] } <= 2'b10;
ds[0] <= 2'b11;
end
end
end
// bank 2,3
if(t == STATE_RAS1) begin
refresh <= 1'b0;
addr_latch[1] <= addr_latch_next[1];
{ oe_latch[1], we_latch[1] } <= 2'b00;
port[1] <= next_port[1];
if (next_port[1] != PORT_NONE) begin
sd_cmd <= CMD_ACTIVE;
SDRAM_A <= addr_latch_next[1][22:10];
SDRAM_BA <= addr_latch_next[1][24:23];
addr_last2[next_port[1]] <= addr_latch_next[1][15:1];
if (next_port[1] == PORT_REQ) begin
{ oe_latch[1], we_latch[1] } <= { ~port2_we, port2_we };
ds[1] <= port2_ds;
din_latch[1] <= port2_d;
end else begin
{ oe_latch[1], we_latch[1] } <= 2'b10;
ds[1] <= 2'b11;
end
end
if (next_port[1] == PORT_NONE && need_refresh && !we_latch[0] && !oe_latch[0]) begin
refresh <= 1'b1;
refresh_cnt <= 0;
sd_cmd <= CMD_AUTO_REFRESH;
end
end
// CAS phase
if(t == STATE_CAS0 && (we_latch[0] || oe_latch[0])) begin
sd_cmd <= we_latch[0]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[0];
if (we_latch[0]) begin
SDRAM_DQ <= din_latch[0];
port1_ack <= port1_req;
end
SDRAM_A <= { 4'b0010, addr_latch[0][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[0][24:23];
end
if(t == STATE_CAS1 && (we_latch[1] || oe_latch[1])) begin
sd_cmd <= we_latch[1]?CMD_WRITE:CMD_READ;
{ SDRAM_DQMH, SDRAM_DQML } <= ~ds[1];
if (we_latch[1]) begin
SDRAM_DQ <= din_latch[1];
port2_ack <= port2_req;
end
SDRAM_A <= { 4'b0010, addr_latch[1][9:1] }; // auto precharge
SDRAM_BA <= addr_latch[1][24:23];
end
// Data returned
if(t == STATE_READ0 && oe_latch[0]) begin
case(port[0])
PORT_REQ: begin port1_q <= sd_din; port1_ack <= port1_req; end
PORT_CPU1: begin cpu1_q <= sd_din; end
default: ;
endcase;
end
if(t == STATE_READ1 && oe_latch[1]) begin
case(port[1])
PORT_REQ: begin port2_q <= sd_din; port2_ack <= port2_req; end
PORT_SND: begin snd_q <= sd_din; end
default: ;
endcase;
end
end
end
endmodule

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/*******************************************
Wave-base Sound Generator (8CH)
Copyright (c) 2007 MiSTer-X
********************************************/
module WSG_8CH
(
input MCLK,
input [5:0] ADDR,
input [7:0] DATA,
input WE,
input SND_ENABLE,
output WAVE_CLK,
output [7:0] WAVE_AD,
input [3:0] WAVE_DT,
output reg [7:0] SOUT
);
//-------------------------------------------
// Clock Generator & Ctrl Registers
//-------------------------------------------
reg [10:0] clk24k_cnt = 0;
wire CLK_WSGx8 = clk24k_cnt[7]; // 24KHz*8
wire CLK_WSG = clk24k_cnt[10]; // 24KHz
wire CLK24M_EN = clk24k_cnt[0];
wire CLK_WSGx8_EN = clk24k_cnt[6:0] == 7'b1111111;
wire CLK_WSG_EN = clk24k_cnt[9:0] == 10'b1111111111;
reg [7:0] fl [0:7];
reg [7:0] fm [0:7];
reg [3:0] fh [0:7];
reg [2:0] fv [0:7];
reg [3:0] v [0:7];
wire [2:0] ra = ADDR[5:3];
always @( posedge MCLK ) begin
if ( CLK24M_EN & WE ) begin
case ( ADDR[2:0] )
3'h3: v[ra] <= DATA[3:0];
3'h4: fl[ra] <= DATA;
3'h5: fm[ra] <= DATA;
3'h6: begin
fh[ra] <= DATA[3:0];
fv[ra] <= DATA[6:4];
end
default: ;
endcase
end
clk24k_cnt <= clk24k_cnt+1'd1;
end
//-------------------------------------------
// WSG core (8ch)
//-------------------------------------------
reg [2:0] phase = 0;
reg [7:0] o, ot;
reg [19:0] c [0:7];
reg [7:0] wa;
reg [3:0] wm;
reg en;
wire [7:0] va = WAVE_DT * wm;
wire [19:0] cx = c[phase];
wire [19:0] fq = { fh[phase], fm[phase], fl[phase] };
assign WAVE_CLK = CLK_WSGx8;
assign WAVE_AD = wa;
always @ ( posedge MCLK ) begin
if (CLK_WSGx8_EN) begin
if ( phase ) begin
ot <= ot + (en ? { 4'h0, va[7:4] } : 8'd0);
end
else begin
o <= ot;
ot <= (en ? { 4'h0, va[7:4] } : 8'd0);
end
c[phase] <= cx + fq;
en <= (fq!=0);
wm <= v[phase];
wa <= { fv[phase], cx[19:15] };
phase <= phase + 1'd1;
end
end
wire [6:0] wsgmix = ( o[6:0] | {7{o[7]}} );
always @ ( posedge MCLK ) begin
if (CLK_WSG_EN) SOUT <= SND_ENABLE ? { wsgmix, 1'b0 } : 8'd0;
end
endmodule