Update true_dual_port_ram.vhd

2026-02-17 21:17:11 +00:00 · 2023-07-13 12:03:43 +02:00
parent 0758473c4a
commit fecc94a290
1 changed files with 1 additions and 1 deletions
--- a/Hardware/rtl/true_dual_port_ram.vhd
+++ b/Hardware/rtl/true_dual_port_ram.vhd
@@ -78,7 +78,7 @@ begin
    clock_enable_output_a         => "BYPASS",
    clock_enable_output_b         => "BYPASS",
    indata_reg_b                  => "CLOCK1",
-    intended_device_family        => "Cyclone V",
+    intended_device_family        => "Cyclone III",
    lpm_type                      => "altsyncram",
    numwords_a                    => 2**ADDR_WIDTH_A,
    numwords_b                    => 2**ADDR_WIDTH_B,