github.com/Gehstock.Mist_FPGA
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5 Commits

Author SHA1 Message Date
Marcel
cc87442fc6 New Core UniwarS 2019-06-21 11:31:31 +02:00
Gyorgy Szombathelyi
e74e5f77f8 MiST-common: add a signal to select the scandoubler pixel clock 
clk_sys/4 (default) or clk_sys/2
 2019-06-13 19:25:08 +02:00
Marcel
7814ab67db Some Changes 2019-06-11 20:31:33 +02:00
Gyorgy Szombathelyi
13f7290188 Forgot to expand non-scandoubled video input 2019-06-04 16:10:42 +02:00
Gyorgy Szombathelyi
30bf24c2dd Add common MiST components 2019-06-03 19:47:05 +02:00