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MiST-common: add a signal to select the scandoubler pixel clock

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clk_sys/4 (default) or clk_sys/2
This commit is contained in:
Gyorgy Szombathelyi
2019-06-13 19:23:29 +02:00
parent 7814ab67db
commit e74e5f77f8
3 changed files with 31 additions and 15 deletions
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1
common/mist/mist.vhd
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@@ -80,6 +80,7 @@ component mist_video
SPI_DI : in std_logic;
scanlines : in std_logic_vector(1 downto 0);
ce_divider : in std_logic := '0';
scandoubler_disable : in std_logic;
ypbpr : in std_logic;
rotate : in std_logic_vector(1 downto 0);

30
common/mist/mist_video.v
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@@ -4,7 +4,7 @@
module mist_video
(
// master clock
// it should be 4xpixel clock for the scandoubler
// it should be 4x (or 2x) pixel clock for the scandoubler
input clk_sys,
// OSD SPI interface
@@ -15,6 +15,9 @@ module mist_video
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
// non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2
input ce_divider,
// 0 = HVSync 31KHz, 1 = CSync 15KHz
input scandoubler_disable,
// YPbPr always uses composite sync
@@ -76,18 +79,19 @@ end
scandoubler #(SD_HCNT_WIDTH, COLOR_DEPTH) scandoubler
(
.clk_sys ( clk_sys ),
.scanlines ( scanlines ),
.hs_in ( HSync ),
.vs_in ( VSync ),
.r_in ( R ),
.g_in ( G ),
.b_in ( B ),
.hs_out ( SD_HS_O ),
.vs_out ( SD_VS_O ),
.r_out ( SD_R_O ),
.g_out ( SD_G_O ),
.b_out ( SD_B_O )
.clk_sys ( clk_sys ),
.scanlines ( scanlines ),
.ce_divider ( ce_divider ),
.hs_in ( HSync ),
.vs_in ( VSync ),
.r_in ( R ),
.g_in ( G ),
.b_in ( B ),
.hs_out ( SD_HS_O ),
.vs_out ( SD_VS_O ),
.r_out ( SD_R_O ),
.g_out ( SD_G_O ),
.b_out ( SD_B_O )
);
wire [5:0] osd_r_o;

15
common/mist/scandoubler.v
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@@ -25,6 +25,7 @@ module scandoubler
// scanlines (00-none 01-25% 10-50% 11-75%)
input [1:0] scanlines,
input ce_divider, // 0 - 4, 1 - 2
// shifter video interface
input hs_in,
@@ -48,8 +49,18 @@ parameter COLOR_DEPTH = 6;
// it
reg [1:0] i_div;
wire ce_x1 = (i_div == 2'b01);
wire ce_x2 = i_div[0];
reg ce_x1, ce_x2;
always @(*) begin
if (!ce_divider) begin
ce_x1 = (i_div == 2'b01);
ce_x2 = i_div[0];
end else begin
ce_x1 = i_div[0];
ce_x2 = 1'b1;
end
end
always @(posedge clk_sys) begin
reg last_hs_in;