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296 lines
9.0 KiB
VHDL
296 lines
9.0 KiB
VHDL
-------------------------------------------------------------------------------
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--
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-- T8048 Microcontroller System
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-- 8048 toplevel without tri-states
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--
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-- $Id: t8048_notri.vhd,v 1.7 2006/07/14 01:13:32 arniml Exp $
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-- $Name: $
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--
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-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
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--
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-- All rights reserved
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--
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-- Redistribution and use in source and synthezised forms, with or without
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-- modification, are permitted provided that the following conditions are met:
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--
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-- Redistributions of source code must retain the above copyright notice,
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-- this list of conditions and the following disclaimer.
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--
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-- Redistributions in synthesized form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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--
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-- Neither the name of the author nor the names of other contributors may
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-- be used to endorse or promote products derived from this software without
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-- specific prior written permission.
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Please report bugs to the author, but before you do so, please
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-- make sure that this is not a derivative work and that
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-- you have the latest version of this file.
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--
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-- The latest version of this file can be found at:
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-- http://www.opencores.org/cvsweb.shtml/t48/
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity t8049_notri is
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generic (
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gate_port_input_g : integer := 1
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);
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port (
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xtal_i : in std_logic;
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xtal_en_i : in std_logic;
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reset_n_i : in std_logic;
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t0_i : in std_logic;
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t0_o : out std_logic;
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t0_dir_o : out std_logic;
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int_n_i : in std_logic;
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ea_i : in std_logic;
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rd_n_o : out std_logic;
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psen_n_o : out std_logic;
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wr_n_o : out std_logic;
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ale_o : out std_logic;
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db_i : in std_logic_vector( 7 downto 0);
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db_o : out std_logic_vector( 7 downto 0);
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db_dir_o : out std_logic;
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t1_i : in std_logic;
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p2_i : in std_logic_vector( 7 downto 0);
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p2_o : out std_logic_vector( 7 downto 0);
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p2l_low_imp_o : out std_logic;
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p2h_low_imp_o : out std_logic;
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p1_i : in std_logic_vector( 7 downto 0);
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p1_o : out std_logic_vector( 7 downto 0);
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p1_low_imp_o : out std_logic;
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prog_n_o : out std_logic;
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--Extra inputs for MiSTer ROM loader to load embedded ROM
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ADDR_DL : in std_logic_vector(24 downto 0);
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CLK_DL : in std_logic;
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CS_DL : in std_logic;
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DATA_IN : in std_logic_vector( 7 downto 0);
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WR : in std_logic
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);
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end t8049_notri;
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library ieee;
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use ieee.numeric_std.all;
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use work.t48_core_comp_pack.t48_core;
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--use work.t48_core_comp_pack.kSND01_ROM;
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use work.t48_core_comp_pack.generic_ram_ena;
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architecture struct of t8049_notri is
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component kSND01_ROM
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port (
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CLK : in std_logic;
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CLK_DL : in std_logic;
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ADDR : in std_logic_vector(10 downto 0);
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ADDR_DL : in std_logic_vector(24 downto 0);
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DATA_IN : in std_logic_vector( 7 downto 0);
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CS_DL : in std_logic;
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WR : in std_logic;
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DATA : out std_logic_vector( 7 downto 0)
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);
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end component;
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-- Address width of internal ROM
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constant rom_addr_width_c : natural := 11;
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signal xtal3_s : std_logic;
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signal dmem_addr_s : std_logic_vector( 7 downto 0);
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signal dmem_we_s : std_logic;
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signal dmem_data_from_s : std_logic_vector( 7 downto 0);
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signal dmem_data_to_s : std_logic_vector( 7 downto 0);
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signal pmem_addr_s : std_logic_vector(11 downto 0);
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signal pmem_data_s : std_logic_vector( 7 downto 0);
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signal ea_s : std_logic;
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signal p1_in_s,
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p1_out_s : std_logic_vector( 7 downto 0);
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signal p2_in_s,
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p2_out_s : std_logic_vector( 7 downto 0);
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signal vdd_s : std_logic;
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begin
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vdd_s <= '1';
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-----------------------------------------------------------------------------
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-- Check generics for valid values.
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-----------------------------------------------------------------------------
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-- pragma translate_off
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assert gate_port_input_g = 0 or gate_port_input_g = 1
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report "gate_port_input_g must be either 1 or 0!"
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severity failure;
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-- pragma translate_on
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t48_core_b : t48_core
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generic map (
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xtal_div_3_g => 1,
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register_mnemonic_g => 1,
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include_port1_g => 1,
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include_port2_g => 1,
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include_bus_g => 1,
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include_timer_g => 1,
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sample_t1_state_g => 4
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)
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port map (
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xtal_i => xtal_i,
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xtal_en_i => xtal_en_i,
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reset_i => reset_n_i,
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t0_i => t0_i,
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t0_o => t0_o,
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t0_dir_o => t0_dir_o,
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int_n_i => int_n_i,
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ea_i => ea_s,
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rd_n_o => rd_n_o,
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psen_n_o => psen_n_o,
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wr_n_o => wr_n_o,
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ale_o => ale_o,
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db_i => db_i,
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db_o => db_o,
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db_dir_o => db_dir_o,
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t1_i => t1_i,
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p2_i => p2_in_s,
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p2_o => p2_out_s,
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p2l_low_imp_o => p2l_low_imp_o,
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p2h_low_imp_o => p2h_low_imp_o,
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p1_i => p1_in_s,
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p1_o => p1_out_s,
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p1_low_imp_o => p1_low_imp_o,
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prog_n_o => prog_n_o,
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clk_i => xtal_i,
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en_clk_i => xtal3_s,
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xtal3_o => xtal3_s,
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dmem_addr_o => dmem_addr_s,
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dmem_we_o => dmem_we_s,
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dmem_data_i => dmem_data_from_s,
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dmem_data_o => dmem_data_to_s,
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pmem_addr_o => pmem_addr_s,
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pmem_data_i => pmem_data_s
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);
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-----------------------------------------------------------------------------
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-- Gate port 1 and 2 input bus with respetive output value
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-----------------------------------------------------------------------------
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gate_ports: if gate_port_input_g = 1 generate
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p1_in_s <= p1_i and p1_out_s;
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p2_in_s <= p2_i and p2_out_s;
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end generate;
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pass_ports: if gate_port_input_g = 0 generate
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p1_in_s <= p1_i;
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p2_in_s <= p2_i;
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end generate;
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p1_o <= p1_out_s;
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p2_o <= p2_out_s;
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-----------------------------------------------------------------------------
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-- Process ea
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--
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-- Purpose:
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-- Detects access to external program memory.
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-- Either by ea_i = '1' or when program memory address leaves address
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-- range of internal ROM.
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--
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ea: process (ea_i,
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pmem_addr_s)
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begin
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if ea_i = '1' then
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-- Forced external access
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ea_s <= '1';
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elsif unsigned(pmem_addr_s(11 downto rom_addr_width_c)) = 0 then
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-- Internal access
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ea_s <= '0';
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else
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-- Access to program memory out of internal range
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ea_s <= '1';
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end if;
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end process ea;
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--
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-----------------------------------------------------------------------------
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rom_2k_b : kSND01_ROM
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port map (
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CLK => xtal_i,
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CLK_DL => CLK_DL,
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ADDR => pmem_addr_s(rom_addr_width_c-1 downto 0),
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ADDR_DL => ADDR_DL,
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DATA_IN => DATA_IN,
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CS_DL => CS_DL,
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WR => WR,
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DATA => pmem_data_s
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);
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ram_64_b : generic_ram_ena
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generic map (
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addr_width_g => 7,
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data_width_g => 8
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)
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port map (
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clk_i => xtal_i,
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a_i => dmem_addr_s(6 downto 0),
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we_i => dmem_we_s,
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ena_i => vdd_s,
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d_i => dmem_data_to_s,
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d_o => dmem_data_from_s
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);
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end struct;
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-------------------------------------------------------------------------------
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-- File History:
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--
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-- $Log: t8048_notri.vhd,v $
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-- Revision 1.7 2006/07/14 01:13:32 arniml
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-- name keyword added
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--
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-- Revision 1.6 2006/06/21 01:02:16 arniml
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-- replaced syn_rom and syn_ram with t48_rom and generic_ram_ena
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--
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-- Revision 1.5 2006/06/20 00:47:08 arniml
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-- new input xtal_en_i
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--
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-- Revision 1.4 2005/11/01 21:38:48 arniml
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-- wire signals for P2 low impedance marker issue
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--
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-- Revision 1.3 2004/12/02 22:08:42 arniml
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-- introduced generic gate_port_input_g
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-- forces masking of P1 and P2 input bus
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--
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-- Revision 1.2 2004/12/01 23:08:08 arniml
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-- update
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--
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-------------------------------------------------------------------------------
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