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https://github.com/Gehstock/Mist_FPGA.git
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47 lines
864 B
VHDL
47 lines
864 B
VHDL
library ieee;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_unsigned.ALL;
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use IEEE.numeric_std.all;
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entity spram is
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generic
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(
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DATA_WIDTH : natural := 8;
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ADDR_WIDTH : natural := 10
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);
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port
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(
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clk : in std_logic;
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addr : in std_logic_vector((ADDR_WIDTH - 1) downto 0);
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data : in std_logic_vector((DATA_WIDTH - 1) downto 0);
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q : out std_logic_vector((DATA_WIDTH - 1) downto 0);
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we : in std_logic := '0'
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);
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end spram;
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architecture rtl of spram is
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subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);
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type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t;
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shared variable ram : memory_t;
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begin
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process(clk)
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begin
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if(rising_edge(clk)) then
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if(we = '1') then
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ram(to_integer(unsigned(addr))) := data;
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q <= data;
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else
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q <= ram(to_integer(unsigned(addr)));
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end if;
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end if;
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end process;
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end rtl;
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