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163 lines
5.1 KiB
VHDL
163 lines
5.1 KiB
VHDL
-- VHDL Entity r65c02_tc.reg_sp.symbol
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 12:04:08 06.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity reg_sp is
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port(
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adr_low_i : in std_logic_vector (7 downto 0);
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clk_clk_i : in std_logic;
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ld_low_i : in std_logic;
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ld_sp_i : in std_logic;
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rst_rst_n_i : in std_logic;
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sel_sp_as_i : in std_logic;
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sel_sp_in_i : in std_logic;
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ce : in std_logic;
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adr_sp_o : out std_logic_vector (15 downto 0)
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);
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-- Declarations
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end reg_sp ;
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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--
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-- Versions:
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-- Revision 1.7 2013/07/21 11:11:00 jens
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-- - Changing the title block and internal revision history
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--
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-- Revision 1.6 2009/01/04 10:20:47 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.5 2009/01/04 09:23:10 eda
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-- - Delete unused nets and blocks (same as R6502_TC)
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-- - Rename blocks
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--
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-- Revision 1.4 2009/01/03 16:53:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.3 2009/01/03 16:42:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.2 2008/12/31 19:31:24 eda
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-- Production Release
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--
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--
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--
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-- VHDL Architecture r65c02_tc.reg_sp.struct
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 12:04:08 06.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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architecture struct of reg_sp is
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-- Architecture declarations
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-- Internal signal declarations
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signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
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signal load_o_i : std_logic;
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signal result_low1_o_i : std_logic_vector(7 downto 0);
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signal result_low_o_i : std_logic_vector(7 downto 0);
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signal sp_as_n_o_i : std_logic;
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signal val_one : std_logic_vector(7 downto 0);
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-- Implicit buffer signal declarations
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signal adr_sp_o_internal : std_logic_vector (15 downto 0);
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-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
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signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
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begin
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-- ModuleWare code(v1.12) for instance 'U_11' of 'addsub'
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u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i)
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variable temp_din0 : std_logic_vector(8 downto 0);
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variable temp_din1 : std_logic_vector(8 downto 0);
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variable temp_sum : unsigned(8 downto 0);
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variable temp_carry : std_logic;
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begin
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temp_din0 := '0' & adr_sp_low_o_i;
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temp_din1 := '0' & val_one;
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temp_carry := '0';
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if (sp_as_n_o_i = '1') then
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temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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else
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temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
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end if;
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result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
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end process u_11combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
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adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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u_0seq_proc: process (clk_clk_i, ce, rst_rst_n_i)
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begin
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if (rst_rst_n_i = '0') then
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mw_U_0reg_cval <= "00000000";
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elsif (clk_clk_i'event and clk_clk_i='1' and ce = '1') then
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if (load_o_i = '1') then
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mw_U_0reg_cval <= result_low1_o_i;
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end if;
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end if;
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end process u_0seq_proc;
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-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
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load_o_i <= ld_sp_i and ld_low_i;
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-- ModuleWare code(v1.12) for instance 'U_3' of 'buff'
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adr_sp_o_internal(15 DOWNTO 8) <= val_one;
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-- ModuleWare code(v1.12) for instance 'U_4' of 'constval'
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val_one <= "00000001";
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-- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
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sp_as_n_o_i <= not(sel_sp_as_i);
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-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
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u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
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begin
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case sel_sp_in_i is
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when '0' => result_low1_o_i <= result_low_o_i;
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when '1' => result_low1_o_i <= adr_low_i;
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when others => result_low1_o_i <= (others => 'X');
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end case;
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end process u_8combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_10' of 'tap'
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adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
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-- Instance port mappings.
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-- Implicit buffered output assignments
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adr_sp_o <= adr_sp_o_internal;
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end struct;
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