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73 lines
2.0 KiB
Verilog
73 lines
2.0 KiB
Verilog
/* This file is part of JT12.
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JT12 program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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JT12 program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with JT12. If not, see <http://www.gnu.org/licenses/>.
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Author: Jose Tejada Gomez. Twitter: @topapate
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Version: 1.0
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Date: 15-11-2018
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*/
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// Use for YM2203
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// no left/right channels
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// full operator resolution
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// clamped to maximum output of signed 16 bits
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// This version does not clamp each channel individually
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// That does not correspond to real hardware behaviour. I should
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// change it.
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module jt03_acc
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(
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input rst,
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input clk,
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input clk_en /* synthesis direct_enable */,
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input signed [13:0] op_result,
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input s1_enters,
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input s2_enters,
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input s3_enters,
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input s4_enters,
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input zero,
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input [2:0] alg,
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// combined output
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output signed [15:0] snd
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);
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reg sum_en;
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always @(*) begin
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case ( alg )
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default: sum_en = s4_enters;
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3'd4: sum_en = s2_enters | s4_enters;
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3'd5,3'd6: sum_en = ~s1_enters;
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3'd7: sum_en = 1'b1;
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endcase
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end
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localparam res=18;
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wire [res-1:0] hires;
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assign snd = hires[res-1:res-16];
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jt12_single_acc #(.win(14),.wout(res)) u_mono(
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.clk ( clk ),
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.clk_en ( clk_en ),
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.op_result ( op_result ),
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.sum_en ( sum_en ),
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.zero ( zero ),
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.snd ( hires )
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);
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endmodule
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