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408 lines
15 KiB
VHDL
408 lines
15 KiB
VHDL
-- VHDL Entity r65c02_tc.core.symbol
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--
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-- Created:
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-- by - jens.Domain Users (ENTW-7HPZ200)
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-- at - 11:09:21 08/01/13
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity core is
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port(
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clk_clk_i : in std_logic;
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : in std_logic;
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nmi_n_i : in std_logic;
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rdy_i : in std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : in std_logic;
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ce : in std_logic;
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a_o : out std_logic_vector (15 downto 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : out std_logic;
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sync_o : out std_logic;
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wr_n_o : out std_logic;
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wr_o : out std_logic
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);
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-- Declarations
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end core ;
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-- (C) 2008 - 2018 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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--
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-- Versions:
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-- Revision 1.8 2013/08/01 11:00:00 jens
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-- - Change Block names to lower case
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-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong. Adding a priority encoder.
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--
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-- Revision 1.7 2013/07/21 11:11:00 jens
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-- - Changing the title block and internal revision history
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--
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-- Revision 1.6 2009/01/04 10:20:47 eda
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-- Changes for cosmetic issues only
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--
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-- Revision 1.5 2009/01/04 09:23:10 eda
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-- - Delete unused nets and blocks (same as R6502_TC)
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-- - Rename blocks
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--
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-- Revision 1.4 2009/01/03 16:53:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.3 2009/01/03 16:42:02 eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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--
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-- Revision 1.2 2008/12/31 19:31:24 eda
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-- Production Release
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--
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--
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--
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-- VHDL Architecture r65c02_tc.core.struct
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTW-7HPZ200)
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-- at - 12:00:34 06.09.2018
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
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--
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-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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library r65c02_tc;
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architecture struct of core is
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-- Architecture declarations
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-- Internal signal declarations
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signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_o_i : std_logic_vector(15 downto 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_sp_o_i : std_logic_vector(15 downto 0);
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signal ch_a_o_i : std_logic_vector(7 downto 0);
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signal ch_b_o_i : std_logic_vector(7 downto 0);
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signal d_alu_n_o_i : std_logic;
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signal d_alu_o_i : std_logic_vector(7 downto 0);
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signal d_alu_or_o_i : std_logic;
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signal d_alu_prio_o_i : std_logic_vector(7 downto 0);
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signal d_regs_in_o_i : std_logic_vector(7 downto 0);
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signal d_regs_out_o_i : std_logic_vector(7 downto 0);
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signal ld_o_i : std_logic_vector(1 downto 0);
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signal ld_pc_o_i : std_logic;
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signal ld_sp_o_i : std_logic;
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signal load_regs_o_i : std_logic;
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signal nmi_o_i : std_logic;
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signal offset_o_i : std_logic_vector(15 downto 0);
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signal q_a_o_i : std_logic_vector(7 downto 0);
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signal q_x_o_i : std_logic_vector(7 downto 0);
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signal q_y_o_i : std_logic_vector(7 downto 0);
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signal reg_0flag_o_i : std_logic;
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signal reg_1flag_o_i : std_logic;
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signal reg_7flag_o_i : std_logic;
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signal rst_nmi_o_i : std_logic;
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signal sel_pc_in_o_i : std_logic;
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signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
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signal sel_rb_in_o_i : std_logic_vector(1 downto 0);
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signal sel_rb_out_o_i : std_logic_vector(1 downto 0);
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signal sel_reg_o_i : std_logic_vector(1 downto 0);
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signal sel_sp_as_o_i : std_logic;
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signal sel_sp_in_o_i : std_logic;
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signal var_shift_data_o_i : std_logic_vector(7 downto 0);
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-- Component Declarations
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component fsm_execution_unit
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port (
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_alu_prio_i : in std_logic_vector (7 downto 0);
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d_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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irq_n_i : in std_logic ;
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nmi_i : in std_logic ;
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q_a_i : in std_logic_vector ( 7 downto 0 );
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q_x_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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rdy_i : in std_logic ;
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reg_0flag_i : in std_logic ;
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reg_1flag_i : in std_logic ;
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reg_7flag_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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so_n_i : in std_logic ;
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ce : in std_logic ;
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a_o : out std_logic_vector (15 downto 0);
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adr_o : out std_logic_vector (15 downto 0);
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ch_a_o : out std_logic_vector ( 7 downto 0 );
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ch_b_o : out std_logic_vector ( 7 downto 0 );
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d_o : out std_logic_vector ( 7 downto 0 );
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d_regs_in_o : out std_logic_vector ( 7 downto 0 );
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ld_o : out std_logic_vector ( 1 downto 0 );
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ld_pc_o : out std_logic ;
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ld_sp_o : out std_logic ;
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load_regs_o : out std_logic ;
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offset_o : out std_logic_vector ( 15 downto 0 );
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rd_o : out std_logic ;
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rst_nmi_o : out std_logic ;
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sel_pc_in_o : out std_logic ;
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sel_pc_val_o : out std_logic_vector ( 1 downto 0 );
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sel_rb_in_o : out std_logic_vector ( 1 downto 0 );
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sel_rb_out_o : out std_logic_vector ( 1 downto 0 );
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sel_reg_o : out std_logic_vector ( 1 downto 0 );
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sel_sp_as_o : out std_logic ;
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sel_sp_in_o : out std_logic ;
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sync_o : out std_logic ;
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wr_n_o : out std_logic ;
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wr_o : out std_logic
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);
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end component;
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component fsm_intnmi
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port (
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clk_clk_i : in std_logic ;
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nmi_n_i : in std_logic ;
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rst_nmi_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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ce : in std_logic ;
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nmi_o : out std_logic
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);
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end component;
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component reg_pc
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_pc_i : in std_logic ;
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offset_i : in std_logic_vector (15 downto 0);
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rst_rst_n_i : in std_logic ;
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sel_pc_in_i : in std_logic ;
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sel_pc_val_i : in std_logic_vector (1 downto 0);
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ce : in std_logic;
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : out std_logic_vector (15 downto 0)
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);
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end component;
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component reg_sp
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port (
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adr_low_i : in std_logic_vector (7 downto 0);
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clk_clk_i : in std_logic ;
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ld_low_i : in std_logic ;
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ld_sp_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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sel_sp_as_i : in std_logic ;
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sel_sp_in_i : in std_logic ;
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ce : in std_logic ;
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adr_sp_o : out std_logic_vector (15 downto 0)
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);
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end component;
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component regbank_axy
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port (
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clk_clk_i : in std_logic ;
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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sel_rb_in_i : in std_logic_vector (1 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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ce : in std_logic ;
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_y_o : out std_logic_vector (7 downto 0)
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);
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end component;
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-- Optional embedded configurations
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-- pragma synthesis_off
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for all : fsm_execution_unit use entity r65c02_tc.fsm_execution_unit;
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for all : fsm_intnmi use entity r65c02_tc.fsm_intnmi;
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for all : reg_pc use entity r65c02_tc.reg_pc;
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for all : reg_sp use entity r65c02_tc.reg_sp;
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for all : regbank_axy use entity r65c02_tc.regbank_axy;
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-- pragma synthesis_on
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begin
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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-- eb1 1
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var_shift_data_o_i <= x"01";
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-- ModuleWare code(v1.12) for instance 'U_11' of 'add'
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u_11combo_proc: process (ch_a_o_i, ch_b_o_i)
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variable temp_din0 : std_logic_vector(8 downto 0);
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variable temp_din1 : std_logic_vector(8 downto 0);
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variable temp_sum : unsigned(8 downto 0);
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variable temp_carry : std_logic;
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begin
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temp_din0 := '0' & ch_a_o_i;
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temp_din1 := '0' & ch_b_o_i;
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temp_carry := '0';
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temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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d_alu_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
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reg_0flag_o_i <= temp_sum(8) ;
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end process u_11combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_8' of 'inv'
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reg_1flag_o_i <= not(d_alu_or_o_i);
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-- ModuleWare code(v1.12) for instance 'U_9' of 'inv'
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reg_7flag_o_i <= not(d_alu_n_o_i);
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-- ModuleWare code(v1.12) for instance 'U_10' of 'inv'
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d_alu_n_o_i <= not(d_alu_o_i(7));
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-- ModuleWare code(v1.12) for instance 'U_5' of 'lshift'
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u_5combo_proc : process (var_shift_data_o_i, ch_a_o_i)
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variable temp_shift : std_logic_vector (3 downto 0);
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variable temp_dout : std_logic_vector (7 downto 0);
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variable temp_din : std_logic_vector (7 downto 0);
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begin
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temp_din := (others=> 'X');
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temp_shift := ch_a_o_i(3 downto 0);
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temp_din := var_shift_data_o_i;
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for i in 0 to 3 loop
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if (i < 3) then
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if (temp_shift(i) = '1') then
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temp_dout := (others => '0');
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temp_dout(7 downto 2**i) := temp_din(7 - 2**i downto 0);
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elsif (temp_shift(i) = '0') then
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temp_dout := temp_din;
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else
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temp_dout := (others => 'X');
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end if;
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else
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if (temp_shift(i) = '1') then
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temp_dout := (others => '0');
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elsif (temp_shift(i) = '0') then
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temp_dout := temp_din;
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else
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temp_dout := (others => 'X');
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end if;
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end if;
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temp_din := temp_dout;
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end loop;
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d_alu_prio_o_i <= temp_dout;
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end process u_5combo_proc;
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-- ModuleWare code(v1.12) for instance 'U_7' of 'por'
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d_alu_or_o_i <= d_alu_o_i(0) or d_alu_o_i(1) or d_alu_o_i(2) or d_alu_o_i(3) or d_alu_o_i(4) or d_alu_o_i(5) or d_alu_o_i(6) or d_alu_o_i(7);
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-- Instance port mappings.
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U_4 : fsm_execution_unit
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port map (
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adr_nxt_pc_i => adr_nxt_pc_o_i,
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adr_pc_i => adr_pc_o_i,
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adr_sp_i => adr_sp_o_i,
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clk_clk_i => clk_clk_i,
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d_alu_i => d_alu_o_i,
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d_alu_prio_i => d_alu_prio_o_i,
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d_i => d_i,
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d_regs_out_i => d_regs_out_o_i,
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irq_n_i => irq_n_i,
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nmi_i => nmi_o_i,
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q_a_i => q_a_o_i,
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q_x_i => q_x_o_i,
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q_y_i => q_y_o_i,
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rdy_i => rdy_i,
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reg_0flag_i => reg_0flag_o_i,
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reg_1flag_i => reg_1flag_o_i,
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reg_7flag_i => reg_7flag_o_i,
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rst_rst_n_i => rst_rst_n_i,
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so_n_i => so_n_i,
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ce => ce,
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a_o => a_o,
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adr_o => adr_o_i,
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ch_a_o => ch_a_o_i,
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ch_b_o => ch_b_o_i,
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d_o => d_o,
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d_regs_in_o => d_regs_in_o_i,
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ld_o => ld_o_i,
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ld_pc_o => ld_pc_o_i,
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ld_sp_o => ld_sp_o_i,
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load_regs_o => load_regs_o_i,
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offset_o => offset_o_i,
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rd_o => rd_o,
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rst_nmi_o => rst_nmi_o_i,
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sel_pc_in_o => sel_pc_in_o_i,
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sel_pc_val_o => sel_pc_val_o_i,
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sel_rb_in_o => sel_rb_in_o_i,
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sel_rb_out_o => sel_rb_out_o_i,
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sel_reg_o => sel_reg_o_i,
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sel_sp_as_o => sel_sp_as_o_i,
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sel_sp_in_o => sel_sp_in_o_i,
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sync_o => sync_o,
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wr_n_o => wr_n_o,
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wr_o => wr_o
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);
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U_3 : fsm_intnmi
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port map (
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clk_clk_i => clk_clk_i,
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nmi_n_i => nmi_n_i,
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ce => ce,
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rst_nmi_i => rst_nmi_o_i,
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rst_rst_n_i => rst_rst_n_i,
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nmi_o => nmi_o_i
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);
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U_0 : reg_pc
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port map (
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adr_i => adr_o_i,
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clk_clk_i => clk_clk_i,
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ce => ce,
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ld_i => ld_o_i,
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ld_pc_i => ld_pc_o_i,
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offset_i => offset_o_i,
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rst_rst_n_i => rst_rst_n_i,
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sel_pc_in_i => sel_pc_in_o_i,
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sel_pc_val_i => sel_pc_val_o_i,
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adr_nxt_pc_o => adr_nxt_pc_o_i,
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adr_pc_o => adr_pc_o_i
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);
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U_1 : reg_sp
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port map (
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adr_low_i => adr_o_i(7 DOWNTO 0),
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clk_clk_i => clk_clk_i,
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ce => ce,
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ld_low_i => ld_o_i(0),
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ld_sp_i => ld_sp_o_i,
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rst_rst_n_i => rst_rst_n_i,
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sel_sp_as_i => sel_sp_as_o_i,
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sel_sp_in_i => sel_sp_in_o_i,
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adr_sp_o => adr_sp_o_i
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);
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U_2 : regbank_axy
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port map (
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clk_clk_i => clk_clk_i,
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ce => ce,
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d_regs_in_i => d_regs_in_o_i,
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load_regs_i => load_regs_o_i,
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rst_rst_n_i => rst_rst_n_i,
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sel_rb_in_i => sel_rb_in_o_i,
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sel_rb_out_i => sel_rb_out_o_i,
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sel_reg_i => sel_reg_o_i,
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d_regs_out_o => d_regs_out_o_i,
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q_a_o => q_a_o_i,
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q_x_o => q_x_o_i,
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q_y_o => q_y_o_i
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);
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end struct;
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